DISCUSSION CSE 140L3rd November 2010

Vikram Murali

Things we will cover

Finite State Machines -- Mealy and Moore models. -- State Encoding. -- Simple Problem.

VHDL Basics -- The Structure -- What we need !

FSM – Very Briefly

Mathematical abstraction used to design digital logic 

Behavior model composed of a finite number of states, transitions between those states, and actions, similar to a flow graph.

Actually realising a problem statement or modelling it in digital logic.

Logic Flows when certain conditions are met.

Components

States – Represent a state of the circuit (or the problem statement modelled). Characterised by the inputs that caused it to happen and the outputs it results in.

Inputs – Decide the flow between states.

Outputs.

Example.

Outputs 1 when sequence is 1011 ! Seq. Detector

Mealy and Moore Models

Another Mealy Machine

Difference.

Mealy model : Output depends on both the current state and the input.

Moore : It depends only on the current state. Imagine : In a Moore machine, the output is

associated with the state. In a mealy machine, the output is associated with the transitions.

Typically, Moore has more states, but is easier to implement. Mealy machines have less states, and also is faster in clocked systems (the output occurs right away when the inputs are detected). Moore has to wait the clock cycle to transition to the next state before the output is changed. => Mealy can give rise to race conditions. !!

State Encoding

States named as S0 , S1 … Sn are fine with us.

But implementation in Digital Logic ? Each state must be encoded in 0s and 1s Each bit has a certain state transition logic -- We need to derive this to design our

circuit that implements our model/requirement

Eg : 8 states => 2^3 = 8 => 3 bits to encode.

111 DOWNTO 000

A Quick Problem. Traffic Light Cntrler !

Solution. State Diagram.

State transition table

Circuit after logic minimisation for A+, B+ and Z. A+

B

B+

A

VHDL.

Major parts of a VHDL program

-- Entity Declaration -- Architecture Body -- Package Declaration -- Package Body -- Configuration

Synthesisable !

“Look at the following program skeleton”

Port name

Data-type

Mode

Individual Syntaxes

ENTITY

Example

ARCHITECTURE

What we want – VHDL.

States in VHDL -- Building FSMs -- State Transitions and Outputs

THANK YOU !