Dip Ipm App Note

7/30/2019 Dip Ipm App Note

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Powerex, Inc., 173 Pavilion Lane, Youngwood, Pennsylvania 15697 (724) 925-7272

DIP-IPMower ev ces

Application Note


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Powerex, Inc., 173 Pavilion Lane, Youngwood, Pennsylvania 15697 (724) 925-7272

pp cat on n ormat on

1.0 ntro uct on to t e am y ...........................1

1.1 The DIP Concept 1

1.2 System Advantages 2

2.0 Product Description ...........................................2

2.1 Numbering System ...............................................2

2.2 Line-up and Typical Applications ..........................3

2.3 Product Features ..................................................3

3.0 Electrical Characteristics ...................................5

3.1 Functional Description ..........................................5

3.2 High Voltage Level Shift ........................................6

3.3 ootstrap upp y c eme 6

3.4 n ervo tage oc out 7

3.5 Short-circuit Protection 7

3.6 Over-temperature Protection 7

3.7 Fault Output 7

3.8 Static Characteristics 8

3.9 Dynamic Characteristics 8

3.10 Voltage Ratings ................................................10

4.0 Package ..............................................................10

4.1 DIP 2 and DIP Generation 3.5ross-sect on 10

4.2 enerat on 3 ross-sect on 11

4.3 Mini DIP-IPM Cross-section 11

4.4 Super-Mini DIP-IPM Cross-section 11

4.5 n ames an unct ons 12

4.6 Installation Guidelines 13

5.0 Application Guidelines......................................15

5.1 System Connection Diagram ..............................15

5.2 Control Power Supplies Design ..........................15

5.2.1 Main Control Power Supply (V ) .....................15

5.2.2 The Logic Power Supply ..................................17

5.2.3 Main Control Power Supplyn ervo tage oc out 17

5.2.4 Bootstrap Power Supplies (V ) 17

.2.5 ootstrap ower upp y m ng agrams 18

.2.6 e ect ng t e ootstrap eservo r apac tor,es stor an o e 19

.2.7 Bootstrap Power Supply UndervoltageLockout .............................................................22

.2.8 Hybrid Circuits for Control Power Supplies ......22

.2.9 Control Power for Multiple Devices ..................22

.2.10 Ground Terminal Voltage Limits

an recaut ons 22

.3 Interface Circuits 24

.3.1 General Requirements 24

.3.2 Interface Circuit Examples ...............................25

.3.3 Decoupling Capacitor .......................................28

.4 Short-circuit Protection Function ........................28

.4.1 Recommended Wiring of Shunt Resistor .........28

.4.2 Timing Diagram of SC Protection .....................29

.4.3 Selecting the Current SensingShunt Resistor 29

.4.4 Selecting the RC Filter 31

.5 SOA 31

.5.1 Switching SOA 31

.5.2 Short-circuit SOA 32

.5.3 Active Region SOA...........................................32

.6 Thermal Considerations .....................................32

.6.1 Power Losses ...................................................32

.6.2 VVVF Inverter Loss Calculation .......................34

.6.3 Power Cycling Life ............................................36

.7 Noise Withstand Capability .................................36

.7.1 Measurement Circuit ........................................36

.7.2 Countermeasures ............................................37

6.0 ac ag ng an an ng ...................................38

Table of Contents


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owerex, nc., 173 av on ane, oungwoo , ennsy van a 15697 724 925-7272

1.0 ntro uct on to t eDIP-IPM Family

e use o nverters w t sma

motors in appliances, HVAC andlow power industrial applications isincreasing rapidly. The power stage

of these inverters is required tomeet the efficiency, reliability, size,

and cost constraints of the end ap-p cat on. resent y, many o t ese

small inverters rely on discreteIGBTs, free-wheel diodes and

HVICs (High Voltage IntegratedCircuits) for their power stage. Acommon problem with this ap-

proac s t e g manu actur ngcost assoc ate w t mount ng an

isolating multiple high voltage dis-crete components. not er equa yperp ex ng pro em s ma nta n-

ing consistent performance andreliability when the characteristics

of the HVIC drivers, IGBTs andfree-wheel diodes are not matched.

The DIP-IPM Family presented int s app cat on note s es gneto provide a cost effective solution

to these problems by combiningoptimized drive ICs and power de-

vices into a single transfer moldedcomponent. The DIP-IPMs simplify

mec an ca assem y an prov econsistent, reliable, performance

for a wide range of motor controlapp cat ons.

1.1 The DIP-IPM Concept

Conventional IPMs (Figure 1.1)with integrated power devices and

low voltage ASICs (ApplicationSpecific Integrated Circuits) provide

gate drive and protection functionsand have been widely accepted

or genera purpose motor r veapplications ranging from 200W tomore than 150kW. The success of

t ese mo u es s t e rect resu t oa vantages ga ne t roug n-

creased integration. Some of thesea vantages nc u e t e o ow-ing: (1) Reduced design time and

improved reliability offered by thefactory tested, built-in gate drive

and protection functions; (2) Lowerlosses resulting from optimization

of power chips; (3) Smaller size re-su t ng rom t e use o are powerchips and application specific con-

trol ICs; (4) Improved manufactur-a ty resu t ng rom ower externa

component count.

n ortunate y, n sp te o t esea vantages, t e convent ona s

relatively expensive IMS or DBCceramc ase pac age es gn an

optically coupled interface circuit isoften too expensive and complex tomeet the demanding cost and size

requirements of low end industrialand consumer appliance invert-

ers. In most of these applicationss gn cant cost sav ng s o ta ne

by utilizing HVICs to provide levelshifting thereby eliminating the

nee or optocoup ers. t onasavings are obtained by utilizingbootstrap power supplies for the

g -s e gate r vers rat er t anthe four isolated supplies required

by the conventional IPM.

e ey to t e - , s own

in Figure 1.2, is the integra-tion of custom HVICs to provide

level shifting and gate drive for thehigh-side IGBTs. This results in

significant cost savings by allowingdirect connection of all six IGBTcontrol signals to the MCU. The

HVIC also provides undervoltageoc out protect on to a ow s mp -

fied implementation of the requiredbootstrap power supplies. With just

a ew externa components t eentire three-phase power stagecan operate from a single 15V

GATE DRIVE

SHORT-CIRCUIT,CONTROL SUPPLY

FAILURE

PROTECTION,FAULT LOGIC

GATE DRIVE

OVERCURRENT,OVER-TEMPERATURE,

CONTROL SUPPLYFAILURE

PROTECTION,FAULT LOGIC

LV ASIC

LV ASIC POWER CHIPS

TEMPERATURESENSOR

ISOLATED CONTROLSIGNAL INTERFACE(OPTOCOUPLERS)

ISOLATED CONTROLSIGNAL INTERFACE(OPTOCOUPLERS)

ISOLATEDPOWER SUPPLY

ISOLATEDPOWER SUPPLY

USER SUPPLIED INTERFACE

CPU

LEVELSHIFT

GATEDRIVE

CURRENT SHUNT

GATE DRIVE ANDPROTECTION

SHORT-CIRCUITPROTECTION,

UNDERVOLTAGELOCKOUT

HVIC

LV ASIC

POWERCHIPS

CPU

Figure 1.2 DIP-IPM and Mini/Super-Mini DIP-IPM


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2

contro power supp y. e -a so ut zes a custom ow vo tage

integrated circuit to provide gater ve, s ort-c rcu t protect on an

undervoltage lockout for the low-side IGBTs. Incorporating the levelshifting into the DIP-IPM reduces

g vo tage spac ng requ rementson the control PCB. This leads to a

significant savings in circuit boardspace. e - pac age was

further reduced to the Mini DIP-IPM and Super-Mini DIP-IPM, each

av ng sma er pac ages t an t eformer.

1.2 ystem vantages

Figure 1.3 shows a comparison oft e components requ re n a typ -ca t ree-p ase motor r ve us ng

discrete co-packaged IGBT devicesversus a Mini DIP-IPM. Clearly,

there are significant manufactur-ing advantages to the DIP-IPM

approach. Each of the discrete de-v ces must e n v ua y mounteand isolated which typically results

in a very complex assembly andsignificant manufacturing time. On

the other hand, the DIP-IPM con-tains all six of the required IGBT/

ree-w ee o e pa rs an s u yisolated. Mounting is accomplishedwith only two screws and no addi-

t ona so at on mater a s requ re .The reduced manufacturing time

an s mp e assem y prov ey t e - w a ow mprove-

ments in both cost and reliability oft e n s e system.

Another advantage of the DIP-IPMis that the incorporated ICs gate

drive and protection functions arefactory tested with the IGBTs as a

subsystem. This eliminates uncer-ta nty a out t e cr t ca coor na-

tion of the electrical characteristicsof these components. The result

s etter, more cons stent systemperformance and reliability.

2.0 ro uct escr pt on

The original transfer molded DIP-was ntro uce y tsu s

n 1998 to a ress t e rap y

growing demand for cost effectivemotor control in consumer appli-

ance app cat ons. ese ev cessoon became the industry bench-

mark for performance and reliabilityn sma motor r ves. n t e yearsthat followed continuous improve-

ments in performance and packag-ng ave e to t e n ustr es most

advanced line-up of modules forsmall motor control. Today modules

are ava a e or motors rate rom100W to 15kW at line voltages of120VAC to 480VAC. The following

su sect ons present t e mo u eline-up and common features.

2.1 um er ng ystem

Figure 1.3 Discrete Approach vs DIP-IPM

(1) DevicePS2 = Transfer Mold

Type IPM

(2) Voltage (VCES)

1 = 600V2 = 1200V

(3) Package Style

0 = DIP 2 Package5 = Mini DIP Package

6 = DIP (Generation 3.5)Package

7 = Mini DIP (Generation 4)

Package8 = DIP (Generation 3) Package

9 = Super-mini DIP Package

(4) Factory Information

(5) Current Rating (IC)

1 = 3A2 = 5A

3 = 10A4 = 15A5 = 20A

6 = 25A7 = 30A

9 = 50A

(6) OptionsSee Table 2.1

Example:

PS21962-S is a transfer mold IPM

rated for 600 Volts and 5 Amperes.It is an open-emitter Super-mini

DIP style package with 1500Visolation.

(1) (2) (3) (4) (5) (6)

PS2 1 9 6 2 S


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2.2 ne-up an yp caApplications

gure 2.1 s ows p otograp s o

a t e ava a e - pac ages.The Mini and Super-Mini DIP-IPMare available with collector-

emitter blocking voltages of 600V.The DIP 2 is available with 600V

and 1200V ratings. The Mini DIP-s a sma er vers on o t e or g-

inal DIP-IPM and the new Super-Mini DIP-IPM is smaller still. They

all integrate IGBTs and free-wheeldiodes, along with gate drive andprotection circuits. The 600V class

s su ta e or 100 to 220motor r ves, w e t e 1200 -

IPM class is suitable for low powermotor r ves up to 480 .

pp ances an ow-en n ustr a

drives are the target markets forthe DIPs. Typical applications range

from refrigerator compressor mo-tors to blower and fan motors in

HVAC systems. They can also beuse n tness equ pment, powertools and pumps for residential

or small commercial applications.a e 2.1 an 2.2 s ows t e

product line-up of DIP-IPMs.

2.3 ro uct eatures

Figure 2.2 shows basic block

agrams o t e - ntegratefeatures. The key features include:

Three-phase IGBT bridge includ-ing six of the latest generationIGBTs and six optimized shallow-diffused soft-recovery free-

w ee ng o es.

High voltage integrated circuit(HVIC) level shifters for high-side

gate drive enables direct con-nection of all six IGBT gating

contro s gna s to t e contro er

Mini DIP(49mm x 30.5mm x 5.0mm)

Mini DIP (GENERATION 4)(52.5mm x 315mm x 5.6mm)

DIP 2(79mm x 44mm x 8.2mm)

Super-Mini DIP(38mm x 24mm x 3.5mm)

DIP (GENERATION 3)(79mm x 31mm x 7.0mm)

DIP (GENERATION 3.5)(79mm x 31mm x 8.0mm)

Figure 2.1 DIP-IPM Family

CPU

DIP-IPM

3MOTOR

RSHUNT

ACLINE

HVICLEVEL SHIFTGATE DRIVE

UV PROTECTION

LVICGATE DRIVE

UV PROTECTIONSC PROTECTION

15V

Figure 2.2 DIP-IPM Block Diagram


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4

Table 2.1 600V DIP-IPM Line-up

Package

Nominal / Peak Current

IGBT & Free-wheeling Diode

Continuous Sinusoidal

Inverter Output Current

(Tsink 80C, Tj 125C, Ipeak 1.7 IC)

(ARMS)*

Isolation

Voltage

(VRMS)

Part

Number

Options

(-Part Number Suffix)

IC/ICP Rated Voltage f w = 5kHz fsw = 15kHz

Mini DIP

5A / 10A 00V .0 5.2 2500 PS21562-P

SP Open-emitters10A / 20A 00V 10.4 7.0 2500 PS21563-P

15A / 30A 00V 12.0 7.8 2500 PS21564-P

Mini DIP

ew en. 4

20A / 40A 00V .B.D. T.B.D. 2500 PS21765(1)

ver-temperature

rotect on30A 60A 00 . . . . . . 2500 21767(1)

Super-Mini

DIP

(New Gen. 4

ec no ogy

A 6A 00 . . . . . . 2500 21961(2)

A ong (16mm) nsS Open-emitters

C Zig-zag Lead Form

ou e g ag

T Over-temperature

Protection

(New Option Available

ummer 2006

5A 10A 00 .0 6.0 1500 21962

8A 16A 00 9.6 7.4 1500 21963-

10A / 20A 00 11.2 8.1 1500 PS21963

15A / 30A 00 14.0 9.6 1500 PS21964

20A / 40A 00 16.2 11.0 1500 PS21965

30A / 60A 00V .B.D. T.B.D. 1500 PS21967(3)

DIP

20A / 40A 00V 20.0 13.5 2500 PS21265-P(4)

AP Long (16mm) Pins30A / 60A 00V 26.0 17.5 2500 PS21267-P(4)

50A / 100A 00V 37.4 23.6 2500 PS21869-P

DIP 2

20A / 40A 00V 20.0 14.0 2500 PS21065 pen-emitters

tan arPackage Compatible

with 1200V DIP-IPM

30A / 60A 00V 26.0 16.5 2500 PS21067

50A / 100A 00V 34.0 21.0 2500 PS21069

*Tj 125C and Ipeak 1.7*IC are selected according to recommended design margins. The actual device limit is Tj 150C, Ipeak I P.

(1) NEW Available Fall, 2006

(2) NEW Available Summer, 2006

(3) Under Development Spring, 2007

(4) NEW Generation .5 replaces generation 3 types (PS21865-P and PS21867-P).

Table 2.2 1200V DIP-IPM Line-up

Package

Nominal / Peak Current

IGBT & Free-wheeling Diode

Continuous Sinusoidal

Inverter Output Current

(Tsink 80C, Tj 125C, Ipeak 1.7 IC)

PF = 0.8V, VCC = 300V(ARMS)*

so a on

Voltage(VRMS)

Part

Number

Options

IC/ICP Rated Voltage f w = 5kHz fsw = 15kHz

2

5A / 10A 1200V .0 5.5 2500 PS22052

pen-emitters

Standard

10A / 20A 1200V 11.8 7.5 2500 PS22053

15A / 30A 1200V 14.1 8.6 2500 PS22054

25A / 50A 1200V 19.3 11.5 2500 PS22056

*Tj 125C and Ipeak 1.7*IC are selected according to recommended design margins. The actual device limit is Tj 150C, Ipeak I P


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an s ng e contro power supp yoperat on us ng ootstrap supp y

techniques.

P-side (high-side driver) floatingsupply undervoltage (U )lockout.

N-side (low-side driver) control

power supply undervoltage (U )oc out w t au t s gna output.

Short-circuit (SC) protection

us ng an externa s unt res storin the negative DC link with faultsignal output.

Optional over-temperature

protection

Compact low cost transfer mold

packaging allows miniaturizationof inverter designs.

High reliability due to factory

tested coordination of HVIC andpower c ps.

3.0 Electrical Characteristics

The basic electrical characteristicsand operation of the DIP-IPM fam-

y are covere n t s sect on. oredetailed design information can befound in later sections.

3.1 Functional Description

Figure 3.1 shows a general func-tional diagram for a DIP-IPM alongwith typical user supplied sup-porting circuits. All modules in the

- am y cons st o a com -nation of power chips and custom

integrated circuits for gate drivecon gure n a stan ar t ree-

phase bridge topology. This circuitconfiguration is suitable for most

t ree-p ase n uct on an rus -less DC motor drives. The internal

c rcu t es gn an p n-out var esslightly over the range of available

modules. However, the basic func-t ons, c aracter st cs an externa

c rcu t requ rements are t e samefor all modules in the family. Thiscommon functionality helps to

m n m ze t e eng neer ng tmerequired to develop a complete

family of drives for a range ofoutput power rat ngs. e on y

noteworthy variation is the open-emitter configuration in which the

t ree ower em tters are p nneout separately rather than beingconnected within the module as

s own n gure 3.1. s con gu-ration allows the use of separate

current s unts or eac eg w cis useful for some control schemes

The open-emitter configurations stan ar on some ev ces an

ava a e as an opt on on ot ers.

Each DIP-IPM contains the six

IGBT/free-wheel diode pairsrequired for a three-phase motor

drive. The IGBT chips utilize theatest ne pattern processes to

achieve high efficiency with lowswitching and conduction losses.

ree-w ee ng o es use nthe DIP-IPMs are super fast/softrecovery shallow diffused types.

ese o es ave een care u y

gure 3.1 - am y as c unct ona agram

++

AC LINE

UP

VUFB

VUFS

VP1

+

VP

VVFB

VVFS

VP1

+

+

WP

UN

VN

WN

FO

VWFB

VWFS

VP1

VN1

VNC

CIN

CFO

+15V

+3.3 to

+5V

CSFRSF

+VCC LVIC

FAULT

LOGIC

INPUT SIGNAL

CONDITIONING

UV

PROT.

DIP-IPM

OVER

CURRENT

PROTECTION

GATE

DRIVE

UV

PROT.

LEVELSHIFT

INPUT

CONDITION

HVIC

+VCC

GATE

DRIVE

UV

PROT.

LEVELSHIFT

INPUT

CONDITION

HVIC

+VCC

GATE

DRIVE

UV

PROT.

LE

VELSHIFT

INPUT

C

ONDITION

HVIC

+VCC

P

U

V

W

N RSHUNT

MOTOR

CONTROLLER

GATE

DRIVE


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6

opt m ze to ave so t recoveryc aracter stcs over a w e range

of currents in order to minimizeno se. - s are ava -

able with blocking voltage ratings ofeither 600V or 1200V. Normally the600V devices will be used for ap-

plications operating from 100VACto 240VAC and the 1200V rated

devices will be used in applicationsoperating from 360VAC to 480VAC.

The DIP-IPM also includes cus-

tom ICs to provide gate drive andprotection functions. The built-ingate drive allows direct connection

to t e ogc eve s gna s supp eby the controller. Proprietary HVIC

(High Voltage Integrated Circuit)tec no ogy s ut ze to eve s tlogic level control signals from the

low-side ground reference to thehigh-side gate drivers.

3.2 g o tage eve t

The DIP-IPMs built-in levels t e m nates t e nee or

optocoup ers an a ows rect con-nection of all six control inputs tothe CPU/DSP. The detailed opera-

tion and timing diagram for the levelshift function is shown in Figure

3.2. The falling and rising edgesof the P-side control signal (A)

activate the one shot pulse logicwhich generates turn on pulses (B,

C) for the high voltage level shiftingMOSFETs. Narrow ON pulses areused to minimize the power dis-

s pat on w t n t e . e gvoltage MOSFETs pull the input to

the high-side driver latch (D, E) lowto set an reset t e gate r ve orthe P-side IGBT (F).

3.3 ootstrap upp y c eme

Power for the high-side gate drives norma y supp e us ng externa

ootstrap c rcu ts. e ootstrapcircuit typically consists of a lowcurrent fast recovery diode that has

a oc ng vo tage equ va ent to t eVCES rating of the DIP with a small

series resistor to limit the peakc arg ng current an a oat ng

supply reservoir capacitor. In orderto avoid transient voltages and

osc at ons on t e oat ng powersupplies it is often desirable to adda low impedance film or ceramic

type capac tor n para e w t eacfloating supply reservoir capaci-

tor. The operation of the bootstrapsupp y s out ne n gure 3.3.

Figure 3.2 High Voltage Level Shift

A

B

C

D

E

F

GATEDRIVE

GATEDRIVE

ONE SHOTPULSE LOGIC

AB

C

E

R

SQ

D

PIN

NIN

HIGH VOLTAGELEVEL SHIFTERS

+15V

F

(P)

(N)

(U, V, W)

FLOATING SUPPLY

N-SIDE

IGBT

P-SIDE

IGBT

U, V, W

N

(GND)

HIGH

VOLTAGE

FAST

RECOVERY

DIODE

BOOTSTRAP

CAPACITOR

DIP BOOTSTRAP CIRCUIT

BOOTSTRAP CHARGING

TIMING CIRCUIT

LVIC

HVIC

P (VCC)

+

VDB

VD

VCIN(N)

VCIN(N)

CHARGING

CURRENT LOOP

VCC0V

VD

0V

VDB

0V

OFF

PWM

START

Figure 3.3 Bootstrap SupplyOperation


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en t e ower s turneon, the floating supply capacitor

is charged through the bootstrapo e. en t e ower s o ,

t e energy store n t e capac torprovides power for the high-sidegate drive. Using this technique it

is possible to operate all six IGBTgate drivers from a single 15V sup-

ply. The bootstrap circuit is a veryow cost met o o prov ng power

for the high-side IGBT gate drive.However, care must be exercised

to ma nta n t e g -s e supp eswhen the inverter is idle and dur-ing fault handling conditions. This

usua y means t at t e ow-s eIGBTs must be pulsed on periodi-

cally even when the inverter is notrunn ng. t power up, t e ootstrapsupplies must be charged before

the PWM is started. Normally, thisis accomplished by turning on the

low-side IGBTs for a period longenough to fully charge the float-

ing supply reservoir capacitor ass own n gure 3.3. or re er-ence, the charge time is 15ms for

a 100uF bootstrap capacitor with a50 res stor.

3.4 Undervoltage Lockout

The DIP-IPM is protected fromfailure of the 15V control power

supp y y a u t- n un ervo tagelockout circuit. If the voltage of the

control supply falls below the UV

level specified on the data sheet,the low-side IGBTs are turned offand a fault signal is asserted. Inaddition, the P-side HVIC gate

r ve c rcu ts ave n epen entundervoltage lockout circuits that

turn off the IGBT to protect againsta ure t e vo tage o t e oat ng

power supply becomes too low. Ifthe high-side undervoltage lockout

protect on s act vate , t en t erespective IGBT will be turned off,but a fault signal is not supplied.

.5 ort-c rcu t rotect on

The DIP-IPM uses the voltageacross an externa s unt res stor

(RSHUNT) inserted in the negativeDC bus to monitor the current andprovide protection against overload

an s ort-c rcu t con t ons. enthe voltage at the CIN pin exceeds

the VSC reference level specifiedon t e ev ce ata s eet t e ower

arm IGBTs are turned off and afault signal is asserted at the FO

p n. en an overcurrent or s ort-circuit condition is detected, theIGBTs remain off until the fault

t me tFO as exp re an t einput signal has cycled to its OFF

state. The duration of tFO for the- s set y an externa

timing capacitor CFO

The short-circuit protection func-

t on w e scusse n eta nthe applications section for DIP-

IPMs, specifically in Sections 5.4.2t roug 5.4.4. a e 3.1 s ows asummary of protection functions.

.6 Over-temperature Protection

Over-temperature protection is

ava a e n t e atest generat on

n - an uper- n -s. temperature etect on

circuit located on the LVIC forcesa o t e ow-s e s o w en

the OT trip temperature is reached.The low-side IGBTs remain off untilthe LVIC detects a temperature

that has fallen below the OT resettemperature which is typically 10C

below the OT trip temperature.(See Figure 3.4.)

3.7 Fault Output

The DIP-IPMs have a fault signaloutput for the N-side IGBTs. The

au t s gna s use to n orm t esystem controller if the protection

functions have been activated.

The fault signal output is in an

active low open collector configura-tion. It is normally pulled up to the

og c power supp y vo tage v a apull-up resistor. The resistor should

be selected so that the maximum

FO spec e on t e ata s eet snot exceeded. Figure 3.5 shows the

voltage at FO as a function of sinkcurrent for the DIP and Mini/Super-

Mini DIP.

LVIC

TEMPERATURE

OT TRIP TEMPERATURE RESETTEMPERATURE

OT

HYSTERESIS

LOW-SIDE INPUT

LOW-SIDE GATEOUTPUT

FO OUTPUT

Figure 3.4 Timing Chart for Over-temperature Protection


12/43


8

If the FO terminal is exposed toexcessive noise the control IC maytrigger a false fault condition. To

prevent t s, t s recommen e touse as low of a pull-up resistor as

possible and connect it as close asposs e to t e - s p ns.

When a fault occurs the fault line

pu s ow an a t e gates o t eN-side IGBTs are interrupted. If

the fault is caused by an N-side

SC condition, the output assertsa pulse (t specified on the data

sheets) and is then automaticallyreset. In the case of an N-side

control supply UV lockout fault, thes gna s ma nta ne unt t e con-trol supply returns to normal.

e nterna s ort-c rcu t protec-

tion function is designed to protectthe DIP from non-repetitive abnor-

ma current. perat on o a sguaranteed only within its maxi-mum published ratings. Therefore,

t e ev ce s ou not e cont nu-ous y stresse a ove ts max mum

ratings. As soon as a fault output

(FO) is given from the module, thesystem operat on s ou mme -ately shift to a proper fault clear-ance mode stopping all operations

o t e .

3.8 Static Characteristics

Tables 3.2 and 3.3 list the mostimportant static characteristics for

1200 an 600 examp etypes. For the other products,

please refer to the individual data

sheets.

3.9 Dynamic Characteristics

Tables 3.4 and 3.5 list the keyynam c c aracter st cs or t e

same examples of the 1200V and

600V DIP. Once again, refer to theata s eets or t e ot er types.

The switching times given on the

ata s eets as e ectr ca c arac-teristics are for half-bridge induc-tive load. This reflects the fact

t at n uct ve oa s are t e mostprevalent application for DIP-IPMs.

Figure 3.6 shows the standard half-

bridge test circuits for the DIPs.The switching waveform in Figure3.7 illustrates how the data sheetparameters are defined.

Figures 3.8, 3.9, and 3.10 are turn-

on and turn-off waveforms for theDIP, Mini DIP and Super-Mini DIP.

They were measured under thespecified conditions and are typical

o t e ev ces ste .

Function Symbol Description

Normal Drive The control inputs are active high.

CIN < th(off) turns the respective IGBT off, and VCIN > th(on) turns the respective IGBT on.

Short-circuit

Protection

SC The external shunt resistance detects current in the DC link. When the current exceeds a preset SC trip level,

short-circuit is detected and the N-side IGBTs are turned off immediately.

A fault signal is asserted from the FO terminal. Its duration is specified on the data sheet as tFO. After the FO

time expires, normal operation will resume at the next input turn-on signal.

ontro rcu t

n ervo tage

Protection

( )

nterna og c mon tors t e -s e contro supp y vo tage. t e vo tage a s e ow t e t tr p eve , nput

ignals to the N-side IGBTs are blocked and an FO signal is generated.

e au t s gna output per o s spec e on t e ata s eet as tFO. After the FO time expires and the control

upply is above the UVDr reset level, normal operation will resume at the next on pulse.

nterna ogc mon tors t e -s e oatng vo tage supp es. t e vo tage eve rops eow t e trp eve ,

input signals to the P-side IGBTs are blocked.

e protect on s reset w en t e vo tage excee s t e r reset eve .

A aut s gna s not generate or t e -s e state.

Table 3.1 Conventional IPM

FAULT OUTPUT CURRENT, IFO, (mA)

FAU

LTOUTPUT

VOLTAG

E,VFO,(VOLTS)

0.30

0.20

0.25

0.15

0 0.2 0.8

0.10

0.05

01.00.60.4

Figure 3.5 1200V DIP, 600V DIPn n uper- n

DIP Voltage CurrentCharacteristics of

erm na


13/43


Symbol Parameter Condition Rating

o ector- m tter o tage 1200 ( ax.)

CE(sat) Collector-Emitter Saturation Voltage = = 15 , CIN = 5 , C = 25A, = 25C 3.0V (Typ.)

EC FWD Forward Voltage -IC = 25A, VIN = 0V, Tj = 25C 2.0V (Typ.)

Symbol arame er Condition a ng

CES Collector-Emitter Voltage 00V (Max.)

(sat) o ector- m tter aturat on o tage = = 15 , = 5 , = 10A, = 25 1.7 ( yp.)

EC FWD Forward Voltage -IC = 10A, VCIN = 0V, Tj = 25C 1.7V (Typ.)


on/t ff Switching Times = 600 , = 15 , 25A, = 125 , 0 5 1.5/2.0s (Typ.)

tc(on) t (o ) w t c ng mes VCC = 600V, VD = 15V, IC 25A, Tj = 125C, VCIN 0 5V .4 0.4s ( yp.)

Esw(on)/Esw(off) Switching Losses = 600 , = 15 , 25A, = 125 , 0 5 3.75/2.75 mJ/pulse (Typ.)


on/t ff Switching Times = 300 , = 15 , 10A, = 125 , 0 5 1.1/1.5 s (Typ.)

tc(on) t (o ) w t c ng mes VCC = 300V, VD = 15V, IC 10A, Tj = 125C, VCIN 0 5V .4 0.5 s ( yp.)

Esw(on)/Esw(off) Switching Losses = 300 , = 15 , 10A, = 125 , 0 5 .63/0.58 mJ/pulse (Typ.)

Table 3.2 25A/1200V DIP-IPM (PS22056)

Table 3.3 10A/600V Super-Mini DIP-IPM (PS21963)

Table 3.4 25A/1200V DIP-IPM (PS22056)

Table 3.5 10A/600V Super-Mini DIP-IPM (PS21963)

VD

VCIN(P)

VB

OUT

VS

VP1

IN

COM

VNO

OUT

CIN

VCC

VN1

IN

VNC

VCIN(N)

P-SIDEIGBT

L

A

B

L

N-SIDEIGBT

* Note: B connected during P-side switching,A connected during N-side switching.

P-SIDEINPUT

SIGNAL

N-SIDEINPUT

SIGNAL

DIP-IPM

Figure 3.6 Half-bridge Evaluation Circuit

Diagrams (Inductive Load)

VCIN

td(off)

(toff=td(off)+tf)

tf

tc(on) tc(off)

10% 10% 10% 10%

90%90%

trr

Irr

VCE

IC

td(on)

(ton=td(on)+tr)

tr

Figure 3.7 Switching Test Time Waveforms


14/43


10

CONDITIONS: VCC = 300V, VD = VDB = 15V, IC = 20A, Tj = 125C,

INDUCTIVE LOAD HALF-BRIDGE CIRCUIT

VCE = 100V/DIV, IC = 10A/DIV, t = 200ns/DIV

IC

VCE VCE

IC

TURN-ON TURN-OFF


INDUCTIVE LOAD HALF-BRIDGE CIRCUIT


IC

VCE VCE

IC

TURN-ON TURN-OFF


INDUCTIVE LOAD HALF-BRIDGE CIRCUIT (L = 1mH)


IC

VCE VCE

IC

TURN-ON TURN-OFF

Figure 3.8 Typical Switching Waveform of DIP PS21865

(20A/600V) N-side

Figure 3.9 Typical Switching Waveform of Mini DIP PS215635(10A/600V) N-side

Figure 3.10 Typical Switching Waveform of Super-Mini DIP PS21964

(15A/600V)

s t e max mum susta n-able collector-emitter voltage of the

IGBT. VCC(prot) is the maximumus vo tage or w c t e

is guaranteed to turn off safelyin the case of a short-circuit. TheIGBT may be damaged if the bus

voltage exceeds this specification.

4.0 Package

The DIP-IPMs employ a revolu-tionary, low cost, rugged, transfer

mo e pac age eve ope yMitsubishi for small motor controlapplications. The packages have

een opt m ze or sma s ze ang y automate mass pro uct on.

4.1 2 an enerat on 3.5Cross-section

A cross-section diagram of the DIP

2 and DIP Generation 3.5 packageis shown in Figure 4.1. First, bare

power chips are assembled on alead frame along with custom HVICand LVIC die. Ultrasonic bond-

ing of large diameter aluminumw res ma es e ectr ca connect ons

between the power chips and leadframe. Small diameter gold wires

are on e to ma e t e s gnalevel connections between the ICdie and lead frame. The lead frame

a ong w t t e connecte powerchips, ICs and bond wires are then

encapsulated in the first of the

injection mold process. Then aneats n s o ne to t e epoxy

ng state. ra ng c rcu t s oube activated if the P-N volt-

age exceeds this specification.

surge s t e max mum -

surge vo tage n t e stat c state.snubber circuit is necessary if theP-N voltage exceeds V surge

3.10 o tage at ngs

Recommended maximum oper-at ng vo tages or t e - s

are specified on the device datasheets. VCC is the maximum P-Nvoltage in the static (not switch-

Al WIREIGBT/FWDi

IC

AI HEAT SINK

1ST. STEP MOLD

2ND. STEP MOLD

Cu FRAME

Figure 4.1 DIP 2 and DIPGeneration 3.5

Cross-section


15/43


mo , w t a t n separat on so t att s c ose to t e power c ps, to

provide good heat transfer. A sec-on n ect on mo process s t en

ma e to encapsu ate t e ent redevice along with the heatsink.

4.2 DIP Generation 3Cross-section

cross-sect on agram o t e

Generation 3 package is shown inFigure 4.2. The device is fabricated

us ng a trans er mo process ea large integrated circuit. First, barepower chips are assembled on a

ea rame a ong w t customand LVIC die. Ultrasonic bond-

ing of large diameter aluminumw res ma es e ectr ca connect onsetween t e power c ps an ea

frame. Small diameter gold wiresare bonded to make the signal

level connections between the ICdie and lead frame. The device is

then encapsulated using a singlestep n ect on mo process. cop-per block is attached to the lead

frame underneath the power chipsor eat sprea ng. t n ayer

of thermally conductive epoxy isformed between the copper block

an eats n mount ng sur ace.It allows good heat transfer andprovides 2500VRMS electrical iso-

at on. e n ect on mo processencapsulates the entire lead frame

assembly to achieve the final form.

Compared to conventional hybrid

mo u es t s process e m natesthe IMS (Insulated Metal Substrate)

or ceramic substrate and plastics e pac age t ere y su stant a y

reducing cost. The transfer moldprocess is also well suited for highvolume, automated mass produc-

tion. The superior thermal perfor-mance achieved using this process

allows fabrication of modules withIGBT ratings of 20A or more at

elevated case temperatures. Thisperformance is comparable to as-

semblies utilizing discrete TO-247style co packaged (containing bothIGBT and free-wheel diode chips)

ev ces.

4.3 Mini DIP-IPM Cross-section

e n - was eve ope

to provide reduced cost and small-er size for low power applications

that would normally utilize TO-220style discrete co packaged IGBTs.

A cross-sectional diagram of then - s s own n gure

4.3. Like the larger DIP-IPM, the

Mini DIP-IPM is fabricated using atrans er mo process e arge

integrated circuits. First, barepower chips are assembled on a

ea rame a ong w t customdie. Ultrasonic bonding using largediameter aluminum wires makes

e ectr ca connect ons etween t epower chips and the lead frame.

Small diameter gold wires are

bonded to make the signal level

connect ons etween t e eand lead frame. The device is then

encapsulated using a single stepn ect on mo process. e ea

frame is formed to produce a thin,flat, layer of thermally conductiveepoxy at the heatsink mounting

surface of the device. This thinlayer of epoxy allows good heat

transfer and provides 2500VRMSe ectr ca so at on. s process

encapsulates the entire lead frameassembly to achieve the final form.

Compared to conventional hybridmodules this process eliminatesthe IMS (Insulated Metal Sub-

strate or ceram c su strate anp ast c s e pac age t ere y

substantially reducing cost. Thes ng e step trans er mo processallows simplified, high volume,

automated mass production. Thepackages shown have been utilized

to fabricate modules with IGBT rat-ings of 5A to 15A at elevated case

temperatures. This performance iscompara e to assem es ut z ngdiscrete TO-220 style co packaged

devices.

4.4 Super-Mini DIP-IPMCross-section

The Super-Mini DIP-IPM wasdeveloped to provide an ultra-

sma s ze w t en ance t ermatransfer for low power applications.

A cross-sectional diagram of the

Super-Mini DIP-IPM is shown ingure 4.4. rst, are power c ps

are assembled on a lead framealong with custom IC die. Ultra-

son c on ng us ng arge ameteraluminum wires makes electrical

connections between the powerchips and the lead frame. Small

diameter gold wires are bonded tomake the signal level connections

between the IC die and lead frame.A thermal conductive, electricalisolating sheet is then placed be-

Al BOND WIRE

POWER CHIPSIGBT, FWDi HVIC

Au BOND WIRE

MOLD RESINCOPPER BLOCK

CONTROL PINSPOWER PINS

Figure 4.2 DIP Generation 3

Cross-section

Al BOND WIRE

POWER CHIPSIGBT, FWDi

HVIC

Au BOND WIRE

CONTROL PINSPOWER PINS

MOLD RESIN

Figure 4.3 Mini DIP-IPM

Cross-section


16/43


12

ween t e ea rame an a paneof copper foil. The device is then

encapsulated using a single stepn ect on mo process eav ng t e

copper foil exposed. This copperoil provides excellent thermal dissi-pation and the thin layer of isola-

ion material provides 1500VRMSelectrical isolation. This process

encapsulates the entire lead frameassem y to ac eve t e na orm.

he Super-Mini DIP has ratings

WIRE

FWDi IGBT IC

MOLD ISOLATED THERMAL SHEETCOPPER FOIL ANDINSULATING RESIN

FRAME LEAD

Cross-section

em Symbol escr p on

P-side Drive Supply

ermna

P-side Drive Supply

GND Terminal

VUFB-VUFS,

VVFB-V FS,

WFS

or

( )- ,

V(V )-V ,

W(VWFB)-VWFS

These are the drive supply terminals for the P-side IGBTs.

By using bootstrap circuits, no external power supplies are required for the DIP-IPM

P-side IGBTs.

Each bootstrap capacitor is charged from the N-side VD supply during ON state of the

orresponding N-IGBT in the loop.

Abnormal operation may result if this supply is not properly filtered or has insufficient current

apa ty. n or er to prevent ma uncton, t s supp y s ou e we tere w t a ow mpe -

nce e ectro ytc capac tor an a goo g requency ecoup ng capac tor connecte r g t at

he DIP-IPMs pins.

Insert a zener diode (24V/1W) between each pair of control supply terminals to help preventurge destruction.

Control Supply

erm nas

VP1

VN1

These are the control supply terminals for the built-in ICs.

* VP1 is only on the 1200V DIP, 600V DIP and Mini DIP.

A 1 an 1 termnas s ou e connecte to t e externa 15 supp y.

n or er to prevent ma uncton cause y nose an r ppe n t e suppy vo tage, t s supp y

hould be well filtered with a good high frequency decoupling capacitor connected right at the

DIPs pins.

Insert a zener diode (24V/1W) between each pair of control supply terminals to help prevent

urge destruction.

-s e ontro

ermna

-s e contro

ermna

VNC

ese are contro groun s or t e u t-n s.

VPC and VNC should be connected externally.

* The VPC pin is only on the 1200V and 600V DIP-IPM. The Mini/Super-Mini DIP-IPM P-side

rounds are connected internally.

ontro nput

ermna

, ,

UN, VN, WN

nput term nas or contro ng t e sw tc ng operaton.

Operate by voltage input signals. These terminals are internally connected to a Schmitt

r gger c rcu t compose o 5 c ass .

Each DIP-IPM signal line is pulled down to GND inside the device, therefore an external

res stor s not nee e .

e w r ng o eac nput s ou e as s ort as poss e (~2cm) to protect t e aga nst nose.

An RC filter is recommended to prevent signal oscillations.

ort-c rcu t r p

o tage ens ng

erminal

C The signal from the current sensing resistance should be connected between this terminal and

to etect s ort c rcu t.

mpe ance or term na s approx mate y 600 .

An RC filter should be connected in order to eliminate noise.

Table 4.1 Detailed Description of the DIP-IPM Input and Output Pin Functions

o 3 to 30 at e evate casetemperatures. This performance is

comparable to assemblies utilizingscrete -220 sty e co pac age

ev ces.

4.5 Pin Names and Functions

The pin names and functions for

the line of DIP-IPMs are describedn a e 4.1.


17/43


4.6 Installation Guidelines

en mount ng a mo u e to a

heatsink, it is essential to avoiduneven mounting stress that may

cause t e ev ce to e amageor degraded. The mounting stress,heatsink flatness and thermal inter-

ace must t ere ore e cons erecarefully.

It is important to avoid unevenor excess ve t g ten ng stress.Figure 4.5 shows the recom-mended torque order for mounting

screws. se a torque wrenc totighten the screws. The maximum

torque specifications are providedn a es 4.2, 4.3 an 4.4.

When selecting a heatsink for the

1200 - t s mportant toensure that the required creep-age and strike distance, outlined

Item Symbol Description

au t utput

ermna

s s t e au t output termna . A au t con t on pro uces an act ve ow output at t s term na

(SC and UV operation at N-side).

s output s open co ector. e s gna ne s ou e pu e up to t e power suppy w t

res stor.

Fault Pulse

utput Time Setting

ermna

CFO This is the terminal for setting the fault output duration.

An externa capactor s ou e connecte etween t s termna an NC to set t e aut

pulse output time on the DIP and Mini DIP.

Inverter Positive

ower upp y

ermna

P DC link positive power supply terminal of the inverter.

Internally connected to the collectors of the P-side IGBTs.

In order to suppress surge voltage caused by DC link wiring or PCB pattern inductance,onnect the main filter capacitor as close as possible to the P and N terminals. It is also

ffective to add a small film capacitor with good high frequency characteristics.

nverter

ermna

DC link negative power supply terminal of the inverter.

This terminal is connected to the emitters of the N-side IGBTs.

NU, NV and NW are used with open emitter type DIPs

Inverter Power

utput erm na

U, V, W Inverter output terminals for connection to inverter load (AC motor)

Each terminal is internally connected to the center point of the corresponding IGBT

half-bridge arm.

Low Side Output

tage ommon

VNO* It should be connected to the N terminal externally for these devices.

The VNO pin is only used on Mini DIPs PS21562 and PS21563.

Table 4.1 Detailed Description of the DIP-IPM Input and Output Pin Functions (Continued)

Recommended Tightening Order

Temporary tightening

Final tightening

(Temporary tightening torque

is 20 ~ 30% of the maximum

rating.)


18/43


14

n a e 4.5, etween t e -term na s an t e eats n are

met. This is done by mounting the

Item ConditionRatings

Min. Typ. Max. Unit

ount ng

orque

ount ng

Screw: M4

ecommen e 10.4 n- 8.67 10.4 13 n-

ecommen e 1.18 m 0.98 1.18 1.47 m

eats nFlatness

0.50 +100 m

em ConditionRatings

Min. Typ. Max. Unit

Mounting

Torque

Mounting

Screw: M3

Recommended 6.9 in-lb 5.22 6.9 8.7 in-lb

Recommended 0.78 Nm 0.59 .78 0.98 Nm

Heatsink

atness 0.50 +100 m

Item ConditionRatings

Min. Typ. Max. Unit

ount ng

Torque

ount ng

Screw: M3

ecommen e 6.0 n- 5.2 6.1 6.9 n-

ecommen e 0.69 m 0.59 .69 0.78 m

Heatsink

Flatness0.50 +100 m

Standard Clearance (mm) Creepage Distance (mm)

508

a e 34.1-A

Rating Voltage: 301V ~ 600V

9.5 12.7

- -

etween ower erm na s .16 etween ower erm na s 7.16

Between Control Terminals 5.16 Between Control Terminals 5.16

etween erm na s an n 4 (10.8) etween erm na s an n (12.7)

a e 4.5 so at on stance o -

Table 4.4 Mounting Torque and Heatsink Flatness Specification

for Super-Mini DIP-IPM


for Mini DIP-IPM


for 1200V and 600V DIP-IPM

a e 4.5 are appropr ate w en t e- s mounte to a 6.8mm

stepped heatsink similar to what iss own n t e gure.

Heatsink flatness requirementsare also listed in these tables. The

flatness is measured as prescribedin Figure 4.7, which depicts the de-

vices footprint on the heatsink. Theatness o t e eats n un erneat

the module should be measuredalong the line shown in the figure.

The heatsink should have a surfacefinish of 64 micro-inches or less.

se a un orm 4 m to 8 m coat-ing of thermal interface compound.

Select a compound that has stablec aracter st cs over t e w o e oper-at ng temperature range an oes

not change its properties over thelife of the equipment. See Table 4.6

for suggested types.

eats n to t e - a ong t eun que y es gne s ot as s own

in Figure 4.6. The data shown in

HEATSINK

Figure 4.6 Standard Satisfactionount ng et o or

Meeting ClearanceStandards


19/43


5.0 Application Guidelines

DIP-IPMs and Mini/Super-Mini- s are ase on a vance

low loss IGBT and free-wheeldiode technologies. The application

ssues an genera gu e nes areessentially the same for all productgroups. The information presented

n t s sect on s nten e to e pusers of DIP-IPMs apply the de-

vices effectively and reliably.

5.1 System Connection Diagram

Figure 5.1 shows a typical system

connection diagram for a DIP-IPMand Mini/Super-Mini DIP. Com-

ponent selection information andre evant notes are nc u e nFigure 5.1.

5.2 Control Power Supplies

Design

n most app cat ons t e - sbuilt-in gate drive, level shifting andprotection functions will be pow-

ere rom a s ng e 15 source. odo this, four additional low voltage

control power supplies must be

created. The main 15V source (V )supp es power rect y to t e ow-side IGBT gate drivers and protec-tion circuits. The common reference

o t e supp y s essent a y atthe negative DC bus. This is also

the common reference for all of the- s og c eve contro nput

signals. A 3.3V or 5V logic powersupply is used to provide power

or t e contro er. n t e caseof the 1200V DIP-IPM 5V or 15Vlogic must be used. Three float-

ing 15V power supplies (VDB) for

the high-side gate drivers can bedeveloped using external bootstrap

circuits. The following sub-sectionsdescribe the detailed operation and

timing requirements for all of thesecontro power supp es.

.2.1 Main Control Power Supply(V )

Control and gate drive power for

t e - s norma y prov eby a single 15VDC supply that isconnected at the modules VN1an term na s. or properoperat on t s vo tage s ou e

regulated to 15V 10%. Table

.1 describes the behavior of theDIP-IPM for various control sup-ply voltages. This control supplyshould be well filtered with a low

mpe ance e ectro yt c capac torand a high frequency decoupling

capacitor connected as close asposs e to t e - s p ns.

High frequency noise on the supplymay cause the internal control IC to

ma unct on an generate errone-ous fault signals. To avoid theseproblems, the maximum ripple on

t e supp y s ou e ess t an 2

peak-to-peak and the maximumdV/dt should be less than 1V/s.

n a t on, t may e necessaryto connect a 24V, 1W zener diode

across the supply to prevent surgeestruct on.

The positive side of the main con-tro supp y s a so connecte to t e

DIP and Mini DIP modules threeV 1 terminals to provide power

or t e ow vo tage s e o t eHVICs. On the DIP-IPM packageanother connection is required from

t e negat ve s e o t e contropower supp y to mo u e s PCterminal. This connection provides

the ground reference for the lowvoltage side of the three internalHVICs. In the Mini DIP and Super-Mini DIP packages this connection

s not requ re ecause t s ma einternally.

e contro c rcu t groun re er-

ence is normally established atthe upstream side of the current

sensing resistor in the negative DCbus. This means that the voltageat the modules VPC terminal is

Figure 4.7 Measurement Point for Heatsink

Table 4.6 Heatsink Compounds

Manufacturer Type

netsu con 746

Dow Corning DC340

+

-

BASE PLATE

EDGE

SURFACE

APPLIED

GREASE

HEATSINK

FLATNESS RANGE

DIP/IPM

+

-

PLACE O CONT CT

A HEA SINK

DIP-IPM

MEASUREMENT

POINT

MEASUREMENT

POINT

3MM

Mini DIP-IPM

SUPER MINI

DIP-IPM

3MM

MEASUREMENT

POINT 4.6MM

HEAT SINK

SIDE


20/43


16

LOGICINTERFACETOP

WMSOURCE(Note7)

W

P

V

U

VD

VNC

CIN

FO

WN

VN

UN

+VCC LVIC

HVIC

VUFS

+VCC

VUFB

VP1

UP

HVIC

VVFS

+VCC

VVFB

VP1

VP

HVIC

VWFS

+VCC

V

WFB

VP1

WP

NRSF

ZNR

CSF

RSHUNT

MOTOR

GATEDRIVE

FAULTLOGIC

INPUT SIGNALCONDITIONING

UVPROT.

OV

ERCURRENT

P

ROTECTION

GATEDRIVE

UVPROT.

LEVELSHIFT

INPUT

CONDITION

GATEDRIVE

UVPROT.

LEVELSHIFT

INPUT

CONDITION

GATEDRIVE

UVPROT.

LEVELSHIFT

INPUT

CONDITION

15V

+

BOOTSTRAP POWERSUPPLY CIRCUITS

(Note 6)

Component Selection:

Dsgn. Typ. Value Description

C1 200-2000F, 450V Main DC bus filter capacitor Electrolytic, long life, high ripple current, 105C

C2 0.1-0.22F, 450V Surge voltage suppression capacitor Polyester/polypropylene film (Note 1)

C3 2.2-6.5nF Common mode noise suppression fil ter Polyester/polypropylene film (Note 2)

CSF 1000pF Short-c ircu it detection fi lter capacitor Mul tilayer ceramic (Note 4, Note 5)

RSF 1.8k ohm Shor t-circuit detection filter resistor (Note 4, note 5)

RSHUNT 5-100m ohm Current sensing resistor Non-inductive, temperature stable, tight tolerance (Note 3)

ZNR Line Voltage Transient voltage suppressor MOV (Metal Oxide Varistor)

Notes:

1) The length of the DC link wiring between C1, C2, the DIP's P-terminal and the shunt must be minimized to prevent

excessive transient voltages. In particular, C2 should be mounted as close to the DIP as possible.

2) Common mode noise (dV/dt) suppression capacitors are recommended to prevent malfunction of DIP's internal

circuits.

3) Use high quality, tight tolerance current sensing resistor. Connect resistor as close as possible to the DIP's N-terminal.

Be careful to check for proper power rating. See text for calculation of resistance value.

4) Wiring length associated with RSHUNT, RSF, CSF and the CIN terminal of the DIP must be minimized to avoid improper

operation of the SC function.

5) RSF, CSF set short-circuit protection trip time. Recommended time constraints is 1.5s-2.0 s. See text for details.

6) Bootstrap circuits provide floating power supplies for high s ide gate drivers. Component values must be adjusted

depending on the PWM frequency and technique. See text and interface circuit diagrams for details.

7) Logic level control signal interface to PWM controller. See interface circuit diagram and text for details.

C2 C1

INRUSHLIMIT

CIRCUIT

+AC MAINS

C3

Figure 5.1 DIP-IPM System Connection Diagram


21/43


erent rom t at at t e powertermna y t e rop across t e

sensing resistor. It is very importantthat all control circuits and power

supplies be referenced to this pointand not to the N terminal. If cir-

cuits are improperly connected thea t ona current ow ng t rougthe sense resistor may cause im-

proper operation of the short-circuitprotect on unct on. n genera , t s

best practice to make the commonreference at VNC a ground plane in

t e pr nte c rcu t ayout.

The main control power supply is

a so connecte to t e ootstrapc rcu ts t at are use to esta s

the floating supplies for the high-

side gate drivers. The bootstrapsupp y operat on w e scussein more detail in Sections 5.2.4through 5.2.7.

5.2.2 The Logic Power Supply

e 600 - s act ve g

control inputs require 3.3V or 5Vlogic level signals to provide ON

and OFF commands for the six in-ternal IGBTs. The 1200V DIP-IPMscan only accept 5V active high

og c or contro s gna s. e con g-uration of these inputs is described

in more detail in Section 5.3. Theinputs are even suitable for opera-

t on at 15 . og c power supp yreferenced to the same common

as the main control power supplys requ re to prov e power or t econtroller in applications where the

inputs are directly connected. Inopt ca y coup e nter ace app ca-

tions the supply is still required toprovide logic level signals for the

contro nputs.

.2.3 Main Control Power Supply

n ervo tage oc out

The ICs that provide short-circuit

protection and gate drive for thethree low-side IGBTs in the DIP-IPM have an undervoltage lockoutfunction to protect the IGBTs from

nsu c ent r v ng vo tage t emain control power supply voltage

is too low. A timing diagram for thisprotect on s s own n gure 5.2.

If the main control power supply(VD) drops below the undervoltage

tr p eve t spec e on t eDIP-IPMs data sheet, gate drivefor the three low-side IGBTs is

n te an a au t output s gnas asserte . e m n mum ura-

tion of the fault signal is specifiedon the devices data sheet. The

un ervo tage oc out nc u eshysteresis and a 10s trip delay to

prevent oscillations and nuisancetr pp ng. n or er to c ear t e au t,V must exceed the undervoltage

reset level (UV r) specified on theata s eet an t e au t t mer must

expire. Once the fault is clearednormal switching will resume at

t e next on-go ng trans t on o t econtrol input signal.

5.2.4 ootstrap ower upp es(V B)

In most applications floating powersupplies for the high-side gate driv-ers will be generated from the maincontrol power supply using externa

ootstrap c rcu ts. typ ca oot-strap circuit is shown in Figure 5.3.

When the low-side IGBT (IGBT2)s turne on, current ows rom t e

low-side control power supply (VD)through the diode D and inrush-

m t ng res stor BS to c argethe high-side reservoir capacitor(CBS). CBS then supplies power

Main Control

Power Supply Voltage (V )DIP-IPM State

0V ~ 4VControl IC does not function. Undervoltage lockout and fault output do not operate. dV/dt noise on the

ma n - supp y may tr gger t e s.

4 ~ 12.5Control IC starts to function. Undervoltage lockout activates, control input signals are blocked and a fault

signal is generated.

12.5 ~ 13.5Undervoltage lockout is reset. IGBTs will turn on when control inputs are pulled low. Driving voltage is

below the recommended range so VCE(sat) and switching losses will be larger than normal.

13.5V ~ 16.5V Normal Operation. This is the recommended operating range.

6.5 ~ 20

IGBT switching remains enabled. Driving voltage is above the recommended range. Faster switching of the

s w cause ncrease system no se. ea s ort-c rcu t current may e too arge or proper operaton

of the overcurrent protection.

0 + Control circuit in DIP-IPM may be damaged.

Table 5.1 DIP-IPM Functions vs Control Power Supply Voltage


22/43


18

or t e g -s e gate r ve w eIGBT2 is off. The inrush-limiting

resistor is included to prevent thebootstrap charging current pulses

from producing excessive rippleon the control power supply. The

bootstrap diode is required toblock the full DC bus voltage whenIGBT2 is off. To do this, a device

with a reverse blocking voltage rat-ng rrm equa to or greater t an

the IGBTs VCES rating should beused. The diode (D) must also be

an u tra ast recovery type n or erto prevent reverse recovery surgevoltages and noise on the control

power supp y. e ootstrap supp yreservo r capac tor must e s ze

so that sufficient voltage is main-

tained on the high-side gate driverduring the OFF time of IGBT2.Some guidelines for selecting thiscapacitor will be provided in the fol-

ow ng sect ons.

High frequency noise on the sup-p y may cause t e nterna contro

IC to malfunction. To avoid theseproblems, the maximum ripple on

t e supp y s ou e ess t an 2peak-to-peak and the maximumdV/dt should be less than 1V/s.

n a t on, t may e necessaryto connect a 24 , 1 zener o e

across the supply to prevent surgedestruction.

5.2.5 Bootstrap Power Supply

Timing Diagrams

There are two conditions under

which the bootstrap reservoir ca-pac tor w c arge. e rst con -

tion (Case 1) is when the low-sideIGBT (IGBT 2) is on. When IGBT2

rst turns on, t e vo tage BS(VDB) is given by:

1 CE(sat)2 D x S(Dynamic Condition)

where:DB(1) = ootstrap supp y

voltage (Case 1)VD = main control supply voltage

= orwar vo tage rop acrossD at ID

VCE(sat)2 = saturation voltageof IGBT2

ID = bootstrap supply chargingcurrent

BS = nrus m t ng res stor

As the voltage on the bootstrap

reservoir capacitor increases the

c arg ng current ecreases an t estea y state vo tage B ecomes

nearly equal to the main controlsupp y vo tage

V B = VD (Steady State)

When IGBT2 is first turned off therewill be a dead time during which

neither IGBT1 or IGBT2 is on. Theinductive load (motor) will forceforward current through FWD1

bringing the voltage at VS to nearlythe positive DC bus voltage (VCC .

The bootstrap diode D becomesreverse biased cutting off the flow

o ootstrap c arg ng current .This sequence of events is shownin the timing diagram Figure 5.4.

ur ng t e t me o 1 t ebootstrap supply voltage (VDB)

gradually declines as the current

consumed in the HVIC gate drivec rcu t sc arges t e reservo rcapacitor.

e secon con t on un er w cthe bootstrap supply capacitor will

charge is when FWD2 is conduct-ing (Case 2). This mode is illus-

trated in the timing diagram shownin Figure 5.5. In this case IGBT1

s e ng turne on an o w eIGBT2 is always off. During thetime when both IGBT1 and IGBT2

DIP-IPM

3MOTOR

VD

ID

RBS D CBS VS

VDB

VCC

IGBT1FWD1

FWD2

IGBT2

N

P

HVIC

LEVEL SHIFTGATE DRIVE

UVPROTECTION15V

+

+ -CONTROLINPUT

CONTROLSUPPLY (VD)

IGBTCURRENT (IC)

FAULTSIGNAL (FO)

A1

A4

A5

A2 A7

A3A6 A8

A1: Control supply falls below UVDt level, IGBT switching is stopped, fault signal is asserted.

A2: Control supply exceeds UVDr level but no action is initiated because tFO has not expired.

A3: tFO timer expires and fault signal is cleared.

A4: Switching of IGBT resumes at the first on going transition after the fault signal is cleared.

A5: Control supply falls below UVDt, the IGBT switching is stopped and a fault signal is asserted.

A6: tFO timer expires but no action is initiated because the control supply is still below the UVDr level.

A7: The control supply exceeds the UVDr level and the fault signal is cleared.A8: Switching of the IGBT resumes at the first on going transition after the fault signal is cleared.

tFO tFO

UVDrUVDt

Figure 5.2 Main Control Power Supply (V n ervo tage oc out

Timing Diagram

Figure 5.3 Bootstrap Circuit


23/43


are o t e n uct ve oa mo-tor) current will circulate through

FWD2. When this happens the volt-age at ecomes near y equa

to t e negat ve us vo tage anbecomes forward biased allowingbootstrap charging current I to

flow from the main control powersupply. The ID will begin recharg-

ing the bootstrap supply reservoircapacitor C. For this case the

bootstrap supply voltage (VDB(2))is specified by:

VDB(2) = VD VF + VEC2where:

2 = ootstrap supp y vo tage(Case 2)

V = main control supply voltage= orwar vo tage rop across

at

V C2 = forward voltage dropacross FWD2

When IGBT1 is on, the voltage at

VS

becomes nearly equal to thepositive DC link voltage therebyreverse biasing D and stopping the

flow of charging current (ID). Theootstrap supp y vo tage

then begins to gradually decline asthe current consumed by the HVIC

gate r ve c rcu t sc arges t ereservoir capacitor.

5.2.6 e ect ng t e ootstrapReservoir Capacitor,

Resistor and Diode

or t e c arg ng sequence s ownin Case 1 the required bootstrapreservoir capacitance depends

on t e operat ng requency, t emaximum ON time of IGBT1 and

the quiescent current consumptionof the HVIC gate driver. In order to

have a stable bootstrap supply volt-age the charge lost during the ON

time of IGBT1 must be replacedduring the ON time of IGBT2. Byassuming conservation of charge

in CBS t e ootstrap capac tor canbe approximated as follows:

From Q = C x = x t

Qdischarge = IBS x t1where:

1 = max mum t me o 1IBS = current consumption of the

HVIC gate driver

Qcharge = CBS x

where:

C = bootstrap capacitance = max mum a owa e

discharge of V B

Setting Q sc arge = Qc arge ansolving for CBS yields: CBS = I S x t1/V

If the PWM technique being usedhas times when only IGBT1 is

switching with IGBT2 alwaysoff (Case 2 above), CBS will becharged only when FWD2 is

conducting. In this case C S sdischarged during the ON time of

IGBT1 just like it was in Case 1.ere ore, t e equat on s own or

CBS above applies to the case aswell.

The equation above gives theminimum capacitance needed to

avo sc arg ng t e ootstrapsupply (VDB) by more than .

However, in most applications

a larger capacitor is required toprov e es gn marg n, mprovestability and prevent power circuitsurge voltages from overcharging

t e ootstrap supp y. n a t on,CBS may need to be adjusted for

start-up, shutdown, and faultan ng con t ons.

The inrush limiting resistance

BS s ou e se ecte argeenough to prevent excessive boot-strap charging currents (ID) from

OFF

ON

OFF

ON

VS

CONTROLINPUTIGBT1

CONTROLINPUTIGBT2

BOOTSTRAPSUPPLY VOLTAGE

(VDB)

OFF

ON

OFF

ON

VS

CONTROLINPUTIGBT1

CONTROLINPUTIGBT2

BOOTSTRAPSUPPLY VOLTAGE

(VDB)

Figure 5.4 Bootstrap Supply Charging (Case 1)

Figure 5.5 Bootstrap Supply Charging (Case 2)


24/43


20

stur ng t e ma n contro powersupply (VD). It should also be small

enough to completely recharget e ootstrap reservo r capac tor

(CBS) during the minimum on timeof IGBT2 for charging Case 1 orthe minimum off time of IGBT1 for

Case 2. This requires that R S eselected so that when combined

with CBS the time constant will en-a e proper rec arg ng.

The bootstrap diode for the 600V

rate - s s ou ave awithstanding voltage of more than600V. In the DIP-IPM, the maxi-

mum rat ng o t e power supp y s450 . s vo tage s usua y m-

posed by a surge voltage of about50 ; t ere ore t e actua vo tageapp e on t e o e s 500 .

Furthermore, by considering 100Vfor the margin, then a 600V class

o e s necessary. t s a so g yrecommended for the diode to have

high speed recovery characteristics(recovery time is less than 100ns).

The 1200V DIP-IPMs maximumpower supp y vo tage rat ng s

800V. In order to allow for surgevoltages and margin a bootstrap

o e s recommen e w t at east1200V blocking capability and highspeed recovery characteristics.

After the bootstrap voltage has

been fully charged it is necessary

to apply an input pulse to reset theP-side input signal before startingPWM. In some control algorithmssuch as those for BLDCM (Brush-

less DC) or 2-phase modulation ofan induction motor the high-side

IGBT may have a large ON time.s must e cons ere w en se-

lecting the bootstrap components.In some cases, very large boot-

strap capac tors a ong w t zenerdiodes may be required to maintainacceptable regulation of the float-

ng supp es. ternate y, separateso ate power supp es or c arge

pumping schemes may be usednstea o t e ootstrap c rcu t.

The following example shows atypical calculation for the bootstrap

capac tor an res stor. e actuavalues required in a given applica-

tion may need to be adjusted con-s er ng t e contro pattern.

Example:

Bootstrap Circuit Design

Selecting bootstrap capacitor:

on t ons:

DB =1V, maximum ON pulse

width t1 of IGBT1 is 5ms,

DB = 0.35m maxTherefore:

CBS = IDB t1/ DB =1.75 x 10-6 = 1.75F

ut, ta ng nto cons erat on t ec aracter st c str ut on an re -

ability, the capacitance is generallyse ecte to e 2~3 t mes o t e

calculated one. Therefore, CBS sset to 5F.

Selecting bootstrap resistor:Conditions:

From above, CBS = 5F,=15 , =14 .

If the minimum ON pulse width t0of IGBT2, or the minimum OFFpulse width t0 of IGBT2 is 20s,then the bootstrap capacitor needs

to e c arge =1 ur ngt s per o .

ere ore:

BS = {(V ) t0}/

(CBS VDB) = 4

Table 5.2 Typical Circuit Current (mA) for 1200V DIP PS22056

Tj(C)

PWM

requency

FC (kHz)

Duty (%)

10 30 0 0 0

25

3 .94 0.94 0.94 0.94 0.94

5 1.19 1.19 1.19 1.19 1.19

7 1.44 1.44 1.44 1.44 1.44

0 1.82 1.82 1.82 1.82 1.81

5 2.44 2.44 2.44 2.44 2.44

0 .05 3.05 3.05 3.05 3.05

25

3 .85 0.85 0.85 0.85 0.85

5 1.11 1.11 1.11 1.11 1.11

7 1.37 1.37 1.37 1.36 1.36

0 1.74 1.74 1.74 1.74 1.73

5 2.38 2.38 2.37 2.36 2.36

0 .00 3.00 3.00 2.99 2.97

-20

3 .98 0.98 0.98 0.98 0.98

5 1.23 1.23 1.23 1.23 1.23

7 1.48 1.48 1.48 1.48 1.48

0 1.85 1.85 1.85 1.85 1.85

5 2.46 2.46 2.46 2.46 2.46

0 .08 3.08 3.08 3.08 3.08


25/43


temperature an sw tc ng uty.yp ca c aracter st cs are s own n

Tables 5.2 and 5.3 and Figures 5.6t roug 5.8.

s prev ous y ment one , t e cur-rent consumed by the HVIC gate

driver (IBS) inside the DIP-IPMepen s on operat ng requency,

Tj(C)

Frequency

FC (kHz)

Duty (%)

0 0 0 0 0

25

3 66 44 21 99 76

5 80 63 41 18 96

7 96 81 59 36 14

10 16 10 88 65 42

15 51 50 36 12 91

0 87 89 85 64 40

125

3 95 73 50 26 04

5 11 90 68 46 22

7 24 09 86 63 40

10 42 38 13 90 66

15 73 72 61 35 14

0 00 03 00 79 55

20

3 48 25 03 81 595 66 45 23 00 79

7 81 65 43 20 98

10 02 94 72 50 28

15 38 39 22 00 77

0 73 77 71 50 26

Table 5.3 Typical Circuit Current ( ) for 600V DIP PS21869

Figure 5.6 CharacteristicsUnder the Condition

of Tj = -20C (Typicalor DIP PS21869)

10CARRIER FREQUENCY, kHz

100

150

200

250

300

350

400

CIRCUITCURRENT,A

DUTY = 10%DUTY = 30%DUTY = 50%DUTY = 70%DUTY = 90%

Tj = -20C

10CARRIER FREQUENCY, kHz

100

150

200

250

300

350

400

450

CIRCUITCURRENT,A


Tj = 25C

10100

150

200

250

300

350

400

450


Tj = 125C

CARRIER FREQUENCY, kHz

CIRCUITCURREN

T,A


of Tj = 25C (Typicalfor DIP PS21869)


of Tj = 125C (Typicalor DIP PS21869)


26/43


22

5.2.9 ontro ower or u t p eDevices

e c rcu t n gure 5.11 s ows

the parallel connection of thecontrol power supply for two DIP-IPMs. Such an application is likely

to requ re ong w r ng. oute 1and 2 indicate the gate charging

path of low-side IGBT in DIP-IPMo.2. t e route s too ong, t e

gate voltage might drop due tolarge voltage drop from the wiring

mpe ance, w c w negat ve yaffect the operation of the secondIPM. Charging of the bootstrap

capac tor or t e g -s e w einsufficient also. In addition, noise

might be easily imposed on the wir-ng mpe ance. t ere are many

- s connecte n para e ,

the GND pattern becomes long.The fluctuation of GND potential

may influence other circuits (powersupply, protection circuit etc.).

Therefore, parallel connection oft e contro power supp y s not rec-ommended. For an application with

more than one motor, it is recom-men to use n v ua contro sup-

plies for the each DIP-IPM. Shar-ing the common DC bus among

mu t p e - s s genera y nota problem.

5.2.10 roun erm na o tageLimits and Precautions

The DIP-IPM performs short-circuitprotection by detecting DC link cur-rent with an external shunt resistor.For this method, wiring inductance

may ave n uence on t eoperation if it is too large.

When the high-side IGBT turns off,

motor currents will flow continuous-ly through the low-side free-wheel

o e. e pos t ve term na vo tageof high-side floating supply (VFB)may drop below the N terminal volt-

are g nput vo tage, non- so-lated, step-down, DC-DC convert-

ers designed to derive low voltagecontro power rect y rom t e

main DC bus. These convertersaccept input voltages of 140VDC to380VDC allowing them to operate

directly from rectified AC line volt-ages of 100VAC to 240VAC. The

M57182N-315 provides a 200mAregulated 15VDC output. The

M57184N-715 supplies a 350mA,15VDC output and a 200mA, 5VDC

output. ac c rcu t s con gurein a compact SIP (Single In-linePackage) to allow efficient layout

w t m n mum pr nte c rcu t oarspace. e owerex 57184 -715

hybrid DC-DC converter is idealor creat ng t e 15 contro powersupp y an t e 5 og c supp y

directly from the DC bus. Figure.10 shows an example applica-

t on c rcu t us ng t e 57184 -715.The figure shows how the required

power supplies are derived directlyfrom the main DC link voltage(VCC). For more detailed informa-

tion on the hybrid DC-DC con-verters see t e n v ua ev ce

data sheets and Powerex applica-tion note Product Information:

57182 -315 an 57184 -715Hybrid DC-DC Converters.

5.2.7 ootstrap ower upp yn ervo tage oc out

e r vers n t e -

prov e an un ervo tage oc outfunction to protect the high-sideIGBTs from insufficient gate driving

voltage. If the voltage on any of thebootstrap power supplies drops

below the data sheet specifiedundervoltage trip level (UV t) the

respective high-side IGBT will beturned off and input control signals

w e gnore . n or er to preventoscillation of the undervoltageprotection function hysteresis has

een prov e . or norma opera-t on to resume t e ootstrap supp y

voltage must exceed the data sheetspec e un ervo tage reset eve(UV r). Switching will resume

at the next on command after thesupply has reached UV r A tim-

ng agram s ow ng t e operat onof the HVIC undervoltage lockout is

shown in Figure 5.9.

5.2.8 Hybrid Circuits for Control

Power Supplies

Powerex has developed two hybridDC-DC converters to simplify

contro power supp y es gn. eM57182N-315 and M57184N-715

CONTROLINPUT

BOOTSTRAPSUPPLY

(VDB)

IGBTCURRENT

(IC)

FAULTSIGNAL

(FO)

A1 A4

A5A2

A3

(NO FAULT OUTPUT)

A1: The control supply exceeds the UVDBr level. Undervoltage protection is reset.

A2: Normal operation. Switching starts at next on going transition of control input.

A3: Bootstrap supply falls below UVDBt. IGBT switching is stopped.

A4: The control supply exceeds the UVDBr level. Undervoltage protection is reset.

A5: Normal operation resumes. Switching starts at next on going transition of control input.

UVDBr

UVDBt

Figure 5.9 HVIC Undervoltage Lockout Timing Diagram


27/43


age. s p enomenon s commonfor the case of switching a large

current. Generally, for HVICs usinga unct on- so ate process, t e

vo tage ecomes too negat vewith respect to the N terminal volt-age, then the IPM may malfunction.

a e 5.4 s ows t e recommen erange of the N terminal voltage with

respect to common (VNC).

en a s ort-c rcu t s etecte t eIPMs SC protection activates and

interrupts the current through theev ce. s a rupt turn-o o g

current may cause a surge vo tage.If the wiring length of the externalshunt resistor is too long, the volt-

age rop may cause t e vo tageapplied to the DIP-IPM supply ter-

minals to exceed allowable levels.

e nterna may ma unct on ore estroye y suc vo tages. o

avoid this it is necessary to mini-m ze t e s unt w r ng engt . ee

Section 5.4.1 for more details. Inaddition, inserting a zener diode(24V, 1W) between V 1 and GND

w mprove t e surge vo tage w t -stand capability of the device.

W

P+

++

1mH +

V

U

VN1

VNC

CIN

100F

50V10F450V

220F50V

COM.

FO

WN

VN

UN

+VCC LVIC

5V

14681012141618

15V

HVIC

VUFS

+VCC

VUFB

VP1

UP

HVIC

VVFS

+VCC

VVFB

VP1

VP

HVIC

VWFS

+VCC

VWFB

VP1

WP

N

MOTOR

GATEDRIVE

FAULTLOGIC


UVPROT.

OVERCURRENT

PROTECTION

GATEDRIV

E

UVPROT.

LEVELSHIFT

INPUT

CONDITIO

N

GATEDRIVE

UVPROT.

LEVELSHIFT

INPUT

CONDITION

GATEDRIVE

UVPROT.

LEVELSHIFT

INPUT

CONDITION

CONTROLLER

VCC

M57184N-715

Figure 5.10 Power Supply for DIP-IPM


28/43


24

5.3 nter ace rcu ts

The DIP-IPM has six microproces-sor compat e nputs n a t on

to a fault output signal. The built inHVIC level shifters allow all signalsto be referenced to the common

ground of the 15V control powersupply. The signals for 600V DIP

are 3.3V and 5V TTL/CMOS com-pat e n or er to perm t rect con-

nection to a PWM controller. The1200V DIP demands the user to

use a 5 og c nter ace ut a 15logic interface can be used. Theinterface circuit between the PWM

contro er an t e - can e

ma e y e t er rect connect onsor optocoup ers epen ng on t e

requirements of the application.s sect on presents t e e ectr -

cal characteristics of the DIP-IPMscontrol signal inputs and outputs,and provides detailed descriptions

of typical interface circuits.

5.3.1 General Requirements

Figure 5.12 shows the internalstructure of the DIP-IPMs control

s gna s an a s mp e sc e-matic of a typical external interfacecircuit. ON and OFF operations for

a s x o t e - s s are

contro e y t e act ve g contronputs P P, P, N N N

These inputs are pulled low with annterna res stor. o externa pu -up

or pu - own res stors are requ re .The controller commands the re-spective IGBT to turn on by pulling

the input high. Approximately 1V ofhysteresis is provided on all control

inputs to help prevent oscillationsan en ance no se mmun ty. e

optional capacitor (C) and resistor(R), shown dashed in the figure,

can e a e to urt er mprovenoise filtering. These componentsmay be required in some appli-

cat ons epen ng on t e c rcu tlayout and length of connections

to the controller. If these filters area e t s mportant to c ec t atproper ea t me s e ng ma n-

tained. In addition, a minimum ONtime is necessary for proper IGBT

turn-off operation. The requiredminimum ON time is given in Table

5.5. The control inputs should bepu e own to etween 0 an0.8V in the OFF state.

The fault signal output (FO) is in an

open collector configuration. Nor-mally, the fault signal line is pulled

g to t e og c supp y vo tagewith a resistor as shown in Figure5.12. When a short-circuit condition

or mproper contro power supp yvo tage s etecte t e -

turns on the internal open collec-

tor device and pulls the fault lineow. e max mum a owa e s ncurrent at the FO pin is specifiedon the devices data sheets. The

au t output pu -up vo tage can eup to VD+0.5V (typically 15.5V) so

connection of the pull-up resistorto t e 15 contro power supp y

is allowable. However, in most ap-plications it is desirable to use the

og c supp y so t at t e au t s gnavoltage is the same as the controlinput signals.

Table 5.4 Recommended Range of N Terminal Voltage

U, V, W

DIP-IPM #1

DIP-IPM #2

PVM

DC15V

VNC

N

PV

M

VNC

N

U, V, W

SHUNTRESISTOR

SHUNTRESISTOR

MOTOR

AC100/200V

MOTOR

1

2

Figure 5.11 Parallel Connection

Item Symbol Condition Min. Typ. Max. Unit

N Terminal

Voltage NOVoltage between VNC - N

including surge voltage5 +5


29/43


Figure 5.12 DIP-IPM Interface Circuit

RFO*

RPD*

FO

VD

FAULT

UP, VP,WP, UN,VN, WN

Vth(off)*Vth(on)*

DIP-IPM

R

R

C

C

GND

CONTROLLER

GATEDRIVE

+ +3.3V

Device PS21562 PS21563 PS21564 PS21865 PS21867 PS21869

RFO Typ. 10k ohm 10k ohm 10k ohm 10k ohm 10k ohm 10k ohm

RPD Typ. 2.5k ohm 2.5k ohm 2.5k ohm 2.5k ohm 2.5k ohm 2.5k ohm

Vth(off) Min. 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V

Vth(on) Max. 2.6V 2.6V 2.6V 2.6V 2.6V 2.6V

15V

*Values for figure above. VD = 15V, Tj = 25C

Device PS21962 PS21963 PS21964 PS22052 PS22053 PS22054 PS22056

RFO Typ. 10k ohm 10k ohm 10k ohm 10k ohm 10k ohm 10k ohm 10k ohm

RPD Typ. 3.3k ohm 3.3k ohm 3.3k ohm 2.5k ohm 2.5k ohm 2.5k ohm 2.5k ohm

Vth(off) Min. 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V

Vth(on) Max. 2.6V 2.6V 2.6V 4.2V 4.2V 4.2V 4.2V

Device DIP-IPM Mini DIP-IPM Super-Mini DIP-IPM

Minimum ON Time 00ns 00ns 500ns

a e 5.5 n mum me or s

an n uper- n . om-ponent selection information and

relevant notes are included beloweac gure.

t e an n uper- nto t e contro er. gure 5.14

shows a typical high speed opto-coup e nter ace c rcu t or t e

5.3.2 nter ace rcu t xamp es

Figure 5.13 shows a typical inter-ace c rcu t or rect connect on o


30/43


26

+C2

C1

D1R1

R2C2

C5

C5

C5

UP

VUFB

VUFS

VP1

+C2

C1

D1R1

R2C2

VP

VVFB

VVFS

VP1

+

+

C2C1

D1R1

R2C2

WP

(Note 10) NC

UN

VN

WN

FO

VWFB

VWFS

VP1

VN1

VNC

CIN

CFO

+15V

C2

C4C5C5C5

R2

R3

R2

R2

C3

+3.3 to +5V

CSF

RSF

This symbol indicatesconnection to ground plane.

+VCC LVIC

FAULTLOGIC


UVPROT.

OVERCURRENT

PROTECTION

GATEDRIVE

UVPROT.

LEVELSHIFT

INPUT

CONDITION

HVIC

+VCC

GATEDRIVE

UVPROT.

LEVELSHIFT

INPUT

CONDITION

HVIC

+VCC

GATEDRIVE

UVPROT.

LEVELSHIFT

INPUT

CONDITION

HVIC

+VCC

P

U

V

W

N RSHUNT

CO

NTROLLER

Component Selection:

Dsgn. Typ. Value Description

D1 1A, 600V Boot strap supply diode Ultra fast recovery

C1 10-100F, 50V Boot strap supply reservoir Electrolytic, long life, low Impedance, 105C (Note 5)

C2 0.22-2.0F, 50V Local decoupling/high frequency noise filters Multilayer ceramic (Note 8)

C3 10-100F, 50V Control power supply filter Electrolytic, long life, low Impedance, 105C

C4 22nF, 50V Fault lock-out t iming capacitor Multi layer ceramic (Note 4)

C5 100pF, 50V Optional input signal noise f il ter Mult ilayer ceramic (Note 1)

CSF 1000pF, 50V Short-circuit detection filter capacitor Multilayer ceramic (Note 6, Note 7)

RSF 1.8k ohm Shor t-c ircui t detection f il ter res is tor (Note 6 , No te 7)

RSHUNT 5-100m ohm Current sensing resistor Non-inductive, temperature stable, tight tolerance (Note 9)

R1 10 ohm Bootstrap supply inrush limiting resistor (Note 5)

R2 330 ohm Optional control input resistor (Note 1, Note 2)

R3 10k ohm Fault output signal pull-up resistor (Note 3)

Notes:

1) To prevent input signal oscillations, minimize wiring length to controller (2cm). Additional RC filtering (C5 etc.) may be required.

If filtering is added, be careful to maintain proper dead time and voltage levels. See application notes for details.

2) Internal HVIC provides high voltage level shifting allowing direct connection of all six driving signals to the controller.

3) FO output is an open collector type. Pull-up resistor (R3) should be adjusted to current sink capability of the module.

4) C4 sets the fault output duration and lock-out time. C4 12.2E-6 x tFO, 22nF gives 1.8ms

5) Bootstrap supply component values must be adjusted depending on the PWM frequency and technique.

6) Wiring length associated with RSHUNT, RSF, CSF must be minimized to avoid improper operation of the SC function.

7) RSF, CSF set overcurrent protection trip time. Recommend time constant is 1.5s-2.0us. See application notes.

8) Local decoupling/high frequency filter capacitors must be connected as close as possible to the modules pins.

9) Use high quality, tight tolerance current sensing resistor. Connect resistor as close as possible to the DIPs N terminal.

Be careful to check for proper power rating. See application notes for calculation of resistance value.

10) This pin is connected internally. It must not be connected to any external circuits.

GATEDRIVE

Figure 5.13 Typical Direct Connection Interface Circuit (Shown Pins Up)


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Figure 5.14 Typical High-speed Optocoupler Interface Circuit

W

V

U

P

VN1

VNC

CIN

CFO

FO

WN

VN

UN

+VCCLVIC

HVIC

VUFS

+VCC

VUFB

VP1

UP

HVIC

VVFS

+VCC

VVFB

VP1

VP

HVIC

VWFS

+VCC

VWFB

VP1

WP

NC

+

C2C1

C2

D1R1

R2

Dip Ipm App Note

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Transcript of Dip Ipm App Note