DIGITAL SYSTEMS

Programmable devices PLA-PAL

Rudolf Tracht and A.J. Han Vinck

content

• Programmable Logic

– Programmable Logic Array PLA– Programmable Array Logic PAL

Programmable Logic Array

• A PLA can implement m functions of n variables, where each function (in SoP form) can have up to k product terms

• PLA is programmed to • select the literals in each product term • and select the product terms in each function

General structure:

–For a ROM, the number of product terms is k = 2n

–For a PLA, k < 2n

NAND NAND

n-input m-output

k product lines

• • •inputs

NANDarray

• • •outputs

NANDarrayproduct

terms

Cont’d• Pre-fabricated building blocks of many NAND gates

"personalized" by making or breaking connections among the gates

n

k m

programmable array block diagram for sum of products form

Before programmingAll possible connections are available before "programming"

Note: conversion to NANDa b + c d =

((a b)‘ (c d)‘)‘

F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A

after programming

Note: conversion to NANDa b + c d =

((a b)‘ (c d)‘)‘

•Unwanted connections are "blown„

A C B

F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A

example:F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A

personality matrix 1 = uncomplemented in term0 = complemented in term– = does not participate

1 = term connected to output0 = no connection to output

input side:

output side:product inputs outputsterm A B C F0 F1 F2 F3

AB 1 1 – 0 1 1 0B'C – 0 1 0 0 0 1AC' 1 – 0 0 1 0 0B'C' – 0 0 1 0 1 0A 1 – – 1 0 0 1 reuse of terms

Shared product terms among outputs

PLA

• Two-level AND-OR device – can be programmed to realize any sum-of-products

• Limitations:– Number of inputs, outputs, product terms

• Field programmable: – attractive in a research environment– Programm can be simulated and changed immediately

ANDing and ORing

1

1

A A’ B B’

AB

A’B’

Inputs

Products

1

1

1 1

1

1 1

Example of basic functions•Multiple functions of A, B

–F1 = A B

–F2 = A + B

–F3 = A' B'

–F4 = A' + B'

–F5 = A xor B

A B F1 F2F3 F4F5

0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0

A B Homework: do the same for 3 variables

Programmable Aray Logic PALlimited connections are available before "programming"

–constrained topology

–faster and smaller OR plane

0 1 X 10 1 X 1 0 1 X X0 1 X X

D

A

B

C

minimized functions:W = A X = B + AY = BC‘ + B‘CZ = C'D + C D'

A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 0 1 1 10 1 1 0 0 1 0 10 1 1 1 0 1 0 01 0 0 0 1 1 0 01 0 0 1 1 1 0 11 0 1 – – – – –1 1 – – – – – –

0 0 x 10 0 x 1 0 0 x x0 0 x x

D

A

B

C

K-map for W K-map for X

0 1 X 00 1 X 0 1 0 X X1 0 X X

D

A

B

C

K-map for Y

example BCD to Gray code converter

K-map for Z

0 0 X 01 1 X 10 0 X X1 1 X X

D

A

B

C

decoder

0 n-1Address

2 -1n

0

1 1 1 1

word[i] = 0011

word[j] = 1010

bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches)

j

i

internal organization

word lines (only one is active – decoder is just right for this)

recall• Two dimensional array of 1s and 0s

– entry (row) is called a "word"– width of row = word-size– index is called an "address"– address is input– selected word is output

ROM vs. PLA• ROM approach advantageous when

– design time is short (no need to minimize output functions)– most input combinations are needed (e.g., code converters)– little sharing of product terms among output functions

• ROM problems– size doubles for each additional input– can't exploit don't cares

• PLA approach advantageous when– design tools are available for multi-output minimization– there are relatively few unique minterm combinations– many minterms are shared among the output functions

• PAL problems– constrained fan-ins on OR plane

structures for two-level logic• ROM – full AND plane, general OR plane

– cheap (high-volume component)– can implement any function of n inputs– medium speed

• PAL – programmable AND plane, fixed OR plane– intermediate cost– can implement functions limited by number of terms– high speed (only one programmable plane that is much smaller than ROM's

decoder

• PLA – programmable AND and OR planes– most expensive (most complex in design, need more sophisticated tools)– can implement any function up to a product term limit– slow (two programmable planes)