Digital Systems 2 MQP

Model Question Paper

Subject Code: BC0036

Subject Name: Digital systems

Credits: 4 Marks: 140

Part A (One mark questions)

1. Position of each bit in a given sequence has a numerical __________

A) Digit

B) Data

C) Error

D) Weight.

2. 1101(2) is equal to __________________in decimal number system.

A) 12(10)

B) 13(10)

C) 14(10)

D) None of the above

3. Repeated multiplication method is the more systematic method usually used

in_____________ part of decimal number in decimal to binary conversion.

A) fractional

B) Integer

C) differential


4. Binary Equivalent of (17.125)10 is ________________

A) 1 0 0 0 1 . 0 1 1 0

B) 1 0 0 1 . 0 0 1 0

C) 1 0 0 0 1 . 0 0 1 0

D) 1 0 0 1 1 . 0 0 1 0

5. In the year ____, the mathematician George Boole published a book entitled An

Investigation of the Laws of Thought on Which Are Founded the Mathematical Theories of

Logic and Probabilities.

A) 1897

B) 1854.

C) 1856

D) 1990

6. If A is an input to the NOT gate, then its output is given by

A) A

B) A

C) AII


7. If a and b are the inputs of an OR gate and x is the output, then x is given by

A) abx

B) bax

C) bax


8. The output of the NAND gate is high only when________

A) All inputs are high

B) Only one input is low

C) All inputs are low

D) One or more inputs are low

9. SOP stands for __________________

A) Sum of products

B) Set of products

C) Set of presets

D) Sound of products

10. m

Summation notation with the prefix m is used to indicate _______expression.

A) POS

B) SOP

C) Maxterm


11. To realize AND gate using only NAND gates, we require____NAND gates

A) 2

B) 3

C) 4

D) 5

12. Advantage of simplifying an expression is _____________

A) Time saving

B) Easy to remember

C) Simple gate network.

D) Simple procedure

13. Karnaugh Map consists of an arrangement of ___________

A) Gates

B) Boxes

C) Cells.


14. The cells in a __________are arranged in such a way that there is only a one bit or one

variable change between any two adjacent cells.

A) Karnaugh Map

B) Quine McClusky method

C) Truth table


15. While simplifying the expression in Karnaugh Map, Variables that appear in both

uncomplemented and complemented are_____________.

A) Retained

B) Eliminated

C) added


16. Simplification of a given logical expression with Quine McClusky method involves in the

computation of _________from which minimal sum should be selected.

A) Cells

B) Maxterms

C) Subset

D) Prime implicants

17. _____________circuit accepts two binary digits as inputs and produces two outputs sum

and carry.

A) Full adder

B) Half adder

C) Multiplexer

D) Decoder

18. __________is constructed using only one AND gate and an EX-OR gate.

A) Multiplexer

B) Encoder

C) Half adder

D) Full adder

19. Full adder can be realized using two_______

A) Multiplexers

B) Decoders

C) Half subtractors

D) Half adders

20. A logic circuit called__________ performs the subtraction of two bits with borrow generated if

any, during the previous LSB subtraction.

A) Full subtractor.

B) Half subtractor

C) Decoder

D) Encoder

21. The fundamental components of shift registers and counters are_________

A) Flip-flops

B) Subtractors

C) Adders


22. The difference between a latch and a flip-flop lies in the method used for changing

their_________

A) Input state

B) Output state

C) Circuit elements


23. When S=1 and R=0, the output of a SR latch is____________

A) Invalid

B) Reset

C) Set


24. When a HIGH voltage level on the EN pin enables or controls the output of the latch, then

gated latches are also known as __________latches

A) Edge triggered

B) Level triggered

C) Transparent


25. Flip-flops are used in____________

A) Adder

B) Multiplexer

C) Priority encoder

D) Digital counter

26. Asynchronous counters are also known as ____________

A) Ripple counters.

B) Parallel counters

C) System counters


27. A single flip-flop can be treated as a ____________

A) mod-2 counter

B) mod-1 counter

C) mod-3 counter


28. Which of the following statements is true?

A) The counting sequence of Mod-6 counter is 001 010 011 100 101 000110.

B) The number of flip-flops required to design a decade counter is 3.

C) In ripple counters all the flip-flops are made to change the states exactly at the same time.

D) With two flip-flops four output states can be counted. Hence it is referred to as mod-4

counter.

29. In synchronous counters, all the flip-flops are connected to a same clock signal and changes

state at the ___________

A) Same time.

B) Different time

C) Irregular intervals of time


30. An up/down counter is also referred as a ___________counter.

A) Double

B) Systematic

C) Bidirectional

D) Universal

31. A synchronous counter has the ____________of counting as that of a ripple counter.

A) Same time

B) Same sequence

C) Different sequence

D) Different sets

32. Most often in synchronous counter design, __________are used

A) S-R flip-flops

B) D flip-flops

C) J-K flip-flops


33. Shift registers is an example of ___________ type of logic circuits

A) Mathematical

B) Combinational

C) Sequential

D) Analog

34. Serial-in, serial-out shift registers delay data by ______ clock time for each stage.

A) Four

B) Three

C) Two

D) One

35. 74LS395 is a ________register

A) Serial in-Serial out

B) Universal

C) Parallel in Serial out

D) Serial in Parallel out

36. In ________ the output of a shift register is fed back to the input.

A) Ring Counter

B) Parallel in Serial out Register

C) Serial in Parallel out Register

D) Johnson Counter

37. The main disadvantage of the Binary weighted DAC is that

A) It requires more space

B) It is difficult to understand

C) It requires a wide range of binary weighted resistors that may not be practically available.

D) Sometimes it will not give the expected results.

38. Flash type of ADC is also called as the ____________

A) Serial ADC

B) Parallel ADC

C) Lash ADC


39. __________is the disadvantage of a single slope integrator ADC.

A) Conversion time

B) Speed

C) Calibration drift

D) Presence of an op-amp

40. If an ADC circuit has a sample frequency of 5000 Hz, the highest-frequency waveform it can

successfully resolve is

A) 10000 Hz

B) 2500 Hz

C) 500 Hz

D) 1000 Hz

Part B (Two mark questions)

41. To convert a given octal number to_______, simply replace the octal digit by its

equivalent __________representation.

A) Binary, 4-bit binary

B) Binary, 3-bit binary

C) Decimal, 4-bit binary

D) Decimal, 3-bit binary

42. The _________Number System uses base 16 and the value of D is equal to______ in

decimal.

A) Octal, 13

B) Binary, 12

C) Hexadecimal, 13

D) Hexadecimal, 14

43. If a and b are the inputs and x is the output, then the NOR gate output is equal to ________

and XOR gate output is given by _____________

A) bax , bax

B) abx , bax

C) bax , bax

D) bax , bax

44. Associative law of addition is given by_______________ and Distributive law is given

by________________

A) a . (b + c) = (a + b) + c , a . b . c = (a . b) . (a . c)

B) a + (b . c) = (a + b) + c , a . (b + c) = (a . b) + (a . c)

C) a + (b + c) = (a + b) + c , a . (b + c) = (a . b) + (a . c)


45. _________and __________ gates are called universal gates.

A) NAND and OR

B) NAND and NOR

C) AND and NOR

D) NAND and NOT

46. In Boolean algebra the product of two variables can be represented with _______function

and sum of any two variables can be represented with _________function.

A) AND, NOR

B) NAND, OR

C) AND, NAND

D) AND, OR

47. A more systematic method of minimizing expressions of larger number of variables is

____________method and is also known as ____________

A) Karnaugh Map, tabular method

B) Quine McClusky, cells method

C) Karnaugh Map, cells method

D) Quine McClusky, tabular method,

48. Which of the following statements are correct?

i. Karnaugh map can be used to simplify the expressions consisting of more than 6

variables.

ii. The simplified expression for a given logic function consists of all essential prime

implicants and one or more prime implicants.

iii. A three variable Karnaugh Map map consists of 8 cells and a four variable Karnaugh

Map map consists of 16 cells.

iv. In prime implicant chart all prime implicants found in column wise and all minterms in

row wise.

A) i and ii

B) ii and iv

C) ii and iii

D) i, ii and iv

49. Half subtractor circuit accepts two binary digits as inputs and produces two

outputs _________ and ________

A) baSum , abCarry .

B) baSum , baBorrow

C) baDiff , abCarry

D) baDiff , baBorrow

50. ____________is an un weighted code and exhibits only a _________change from one code

number to the next.

A) Gray code, single bit

B) Gray code, two bit

C) BCD code, single bit

D) BCD code, two bit

51. A ________can be thought of a ________ as it stores 1 bit of information over a specific

time.

A) Combinational circuit, shift register

B) Multiplexer, shift register

C) Decoder, memory unit

D) Flip-flop, Memory unit

52. The _______existed in SR latch is avoided in D latch because ______ gate is connected

between S and R inputs.

A) Valid condition, AND

B) Invalid condition, OR

C) SET condition, NOT

D) Invalid condition, NOT

53. __________is a 4-bit Binary Counter and it consists of one single flip-flop and a 3-bit

__________counter.

A) IC 7497, asynchronous

B) IC 7493, asynchronous

C) IC 7493, synchronous

D) IC 7496, synchronous

54. __________consists of one single flip-flop ______and a ________asynchronous counter.

A) IC 7493, mod-5

B) IC 7490, mod-5

C) IC 7493, mod-4

D) IC 7490, mod-8

55. Select the correct statements from the following.

i. In synchronous counters, all flip-flops are driven by the different clock pulses.

ii. The design complexity is more in synchronous counters than the asynchronous

counters.

iii. The sequence of states changes from a lower state to the upper state in up counters.

iv. A three-bit synchronous binary up counter counts from 100 to 110 only

A) i and iv

B) i and iii

C) ii and iv

D) ii and iii

56. A synchronous _________is one that is capable of counting in either direction through a

certain__________.

A) up-down counter, sequence

B) down counter, sequence

C) up counter, set


57.The binary number 1011 is serially shifted into an four-bit parallel out shift register that has

an initial content of 1110.What are the Q outputs after two clock pulses

A) 1100

B) 1011

C) 1111

D) 1010

58. The binary number 1011 is serially shifted into an four-bit serial out shift register that has an

initial content of 1110.What is the content of the register after two clock pulses

A) 1100

B) 1011

C) 1010

D) 1111

59. The important considerations of ADC circuitry are its ________and__________.

A) Resolution, sample frequency

B) Resolution, Speed

C) Conversion time, sample frequency

D) Conversion time, discrete steps

60. If an ADC is subjected to an analog input signal whose frequency exceeds the Nyquist

frequency for that ADC, the converter will output a digitized signal of falsely________. This

phenomenon is known as __________

A) Low frequency, aliasing.

B) High frequency, aliasing.

C) Low frequency, acquisition

D) High frequency, acquisition

Part C (Four mark questions)

61. Match the following

a) BCD i. Fraction part

b) Repeated multiplication ii. Subtraction

c) Hexadecimal Number iii. Weighted code

d) Complementary method iv. Alpha-numeric symbols

A) a-iii, b-i, c-iv, d-ii

B) a-ii, b-i, c-iv, d-iii

C) a-iii, b-i, c-ii ,d-iv

D) a-i, b-iii, c-iv, d-ii

62. State whether the following statements are True (T) or False (F)

a. The Decimal Number System uses base 10 and represented by arranging the 9 symbols

i.e. 1 through 9, where these symbols were known as digits.

b. Counting with octal number system is analogous to the counting methodology used in

decimal and in binary numbering system.

c. There are totally 7 combinations with 3-bit binary representation from 001 to 111, which

can be mapped octal symbols 0 to 6.

d. 1s complement method is useful in the sense subtraction can be carried with adder

circuits of ALU (Arithmetic logic unit) of a processor.

A) a-T, b-F, c-T, d-F

B) a-F, b-F, c-T, d-F

C) a-F, b-T, c-F, d-T

D) a-T, b-T, c-F, d-F


a) a + b = b + a i. OR rule

b) 1 aa ii. Associative rule

c) cbacba iii. Commutative law

d) iv. Demorgans Theorem






a. NAND operation can be thought as NOT of the ORed inputs.

b. Distributive law states that the net result remain same irrespective grouping of the

variables for OR operation

c. NOT function represents a logical inversion or negation.

d. Three input AND operation can be give by x = a. b. c


B) a-F, b-F, c-T, d-T




a) Clock waveform i. Gate circuitry

b) Propagation delay ii. OR function.

c) Product of two variables iii. Rectangular pulse

d) Sum of any two variable iv. AND function






a) SOP and are OSP are the two representations of a given Boolean expressions.

b) The forms of the Boolean expression doesnot determine how many logic gates are

used and what types of gates are needed for the realization and their interconnection.

c) Boolean rules and laws are used to simplify the logic function and realize the

minimized function using basic gates.

d) A most popular method of representation of SOP form is with the minterms.






a) Qunie McClusky method i. Arrangement of cells

b) Karnaugh Map ii. Not a systematic method

c) Two input variables iii. Hand computation

d) Boolean algebra iv. Four cell map






a) A four variable map consists of 24 = 16 cells.

b) For an n number of variables the total number of combinations possible are 2n,

hence Karnaugh Map consists of 2n cells.

c) Qunie McClusky method is not suitable for the soft program implementation.

d) Qunie McClusky method cannot be used for more than 4 variables.






a) BCD code i. a > b

b) Comparator ii. Data select lines

c) Gray code iii. Weighted code

d) Multiplexer iv. Un-weighted code






a) In Binary to Gray conversion, the most significant bit (MSB) in the Gray code is the same

as the corresponding digit in the binary number

b) Decimal to BCD encoder is also known as 10 lines to 4 line encoder.

c) A decoder accepts an active level on one of its inputs representing digit, such as decimal

or octal and converts it to a coded output such as binary or BCD.

d) Binary to octal encoder is also known as 3 lines to 8 line decoder; the output is activated

upon the input on its 8 lines.






a) Latch i. SR latch

b) Invalid condition ii. Negative edge triggering

c) A triangle with a bubble at the clock terminal iii. Bistable device

d) Edge triggering iv. Flip-flop



C) a-iii, b-i, c-ii, d-iv



a) IC 7490 i. Mod 4 counter

b) Two bit counter ii. 2 counter.

c) Ripple counters iii. Decade counter

d) Single flip-flop iv. Cascade connection






a) In a synchronous up-down counters, for the Up sequence, QB changes state on the next

clock pulse when QA = 1 where as for the Down sequence, QB changes state on the next

clock pulse when QA = 0.

b) In a three-bit up/down synchronous counter, the output Q of the second flip-flop cannot

be directly connected to the J and K inputs of third flip-flop.

c) In a three-bit up/down synchronous counter, up/down terminal is not required.

d) In a two bit synchronous up counter with negative edge triggering, when the negative

edge of the first clock pulse is applied, output of first flip-flop does not toggle.






a) Number of bits a flip-flop can store i. 7

b) Number of clock pulses required to ii 2

Shift a 4 bit data into and out of a four

Bit serial in-serial out shift register

c) Number of stages we need for a divide iii 4

By 2 ring counter?

d) Number of stages required to iv 1

Implement divide by 8 Johnson counter



C) a-iii, b-i, c-ii, d-iv

D) a-iv, b-i, c-ii, d-iii

75. Which of the following are the typical applications of Analog to Digital Converters?

i. Digital voltmeters,

ii. Pen drive and CRT

iii. Microprocessor interfacing

iv. LED/LCD displays

v. Memory unit, and mouse

A) i and iii only

B) ii and v only

C) i ,iii and iv only

D) ii,iii and v only

Answer Keys

Part - A Part - B Part - C

Q. No. Ans. Key Q. No. Ans. Key Q. No. Ans. Key Q. No. Ans. Key

1 D 21 A 41 B 61 A

2 B 22 B 42 C 62 C

3 A 23 C 43 A 63 C

4 C 24 B 44 C 64 B

5 B 25 D 45 B 65 A

6 B 26 A 46 D 66 B

7 C 27 A 47 D 67 A

8 D 28 D 48 C 68 D

9 A 29 A 49 D 69 A

10 B 30 C 50 A 70 D

11 A 31 B 51 D 71 C

12 C 32 C 52 D 72 A

13 C 33 C 53 B 73 D

14 A 34 D 54 B 74 D

15 B 35 B 55 D 75 C

16 D 36 A 56 A

17 B 37 C 57 C

18 C 38 B 58 D

19 D 39 C 59 A

20 A 40 B 60 A

Digital Systems 2 MQP

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