Digital System Design

Lab 0

by

Syed Ali Jabir

Verilog

• Verilog is a hardware description language (HDL)

used in the design, verification, and implementation

of digital logic chips

Always keep hardware in mind…

Modules

• The module is the basic building block in Verilog

• Modules are:

Declared

Instantiated

• Modules declarations cannot be nested

• Just like main() function in C/C++

Module declaration • C/C++

void main()

{

// data types declaration

..

…

// data manipulation

}

• Verilog

module name (portlist);

// data types declaration

..

…

// data manipulation

endmodule

Data Types in Verilog • Nets

Nets are physical connections between

components, we use the type wire

• Registers

Retains the previously stored value unless

changed

May or may not be a hardware register

It is denoted by reg

Declaration • type [size] name;

• Type == wire/reg

• Size == [msb:lsb] or [lsb:msb]

• For example o wire [7:0] w1; // 8bit wire

o wire a,b; // 2, 1bit wires

o reg [31:0] treg; // 32bit register

o reg [7:0] memory[0:1023]; // 1KB memory

constants wire [3:0] w;

reg [3:0] r;

• Decimal (default)

w = 12; r = 14;

• Binary

w = 4’b1100; r = 4’b1110;

• Octal

w = 4’o14; r = 4’o16;

• Hexadecimal

w = 4’hc; r = 4’he;

Possible values of a bit

Ports

• Ports provide means to communicate with other

modules

• Input Ports

always a wire

• Output Ports

wire/reg

• Inout Ports

Declaration module name (input in1,in2,

output out);

endmodule

module name (in1, in2,out);

input in1,in2;

output out;

endmodule

Levels of Abstraction in Verilog

4 levels of abstraction are provided by verilog

• Switch Level

• Gate Level

• Dataflow Level

• Behavioral Level

Levels of Abstraction

Levels of Abstraction in Verilog

4 levels of abstraction are provided by verilog

• Switch Level

• Gate Level

• Dataflow Level

• Behavioral Level

Dataflow Modeling

• Previously at Gate level, we were using gates, literally

• Dataflow modeling is all about expressions and

operators…

Arithmetic Operators

Condition Operator

c = cond ? a : b;

Same as C/C++ code of

if (cond)

c = a;

else

c=b;

Concatenation Operator

Replication Operator

a = 3’b110;

b = {3{a}};

Relational Operators

Bitwise Arithmetic Operators

Equality Operators

example • 4'bx001 === 4'bx001 = 1

• 4'bx0x1 === 4'bx001 = 0

• 4'bz0x1 === 4'bz0x1 = 1

• 4'bz0x1 === 4'bz001 = 0

• 4'bx0x1 !== 4'bx001 = 1

• 4'bz0x1 !== 4'bz001 = 1

Logical Operators

Shift Operators

Continuous Assignment • assign keyword is always used

• Left Hand Operand is always a wire

wire [3:0] a,b,c,d;

wire [15:0] w1,w2;

reg [15:0] r1;

assign a = b + c;

assign w2 = {a,b,c,d};

assign w1 = r1;

assign d = code ? b : c;

Behavioral Modeling High level language constructs are used

• for loop

• if else

• while etc

All statements come in a procedural block

Two types of procedural blocks

• always

• Initial

Not all constructs are synthesizable

initial/always blocks

Procedural Assignments

• Blocking assignment

“ = ”

• Non-Blocking assignment

“ <= ”

• LHS must be a reg

The Difference • LHS

• assign

• Procedural Blocks

Sensitivity List

• always @ ??

“@” Event Control

• @(expression)

• @(expression or expression or …)

• @(clk) is same as @(posedge clk or negedge clk)

“#” Time Control

• #<number> statement

• statement is not executed until <number> time units

have passed

• control is released so that other processes can

execute

• used in test code

if else

case

case (val)

1:

begin

…

end

2:

begin

…

end

default:

begin

…

end

endcase

Loops

• Repeat

• While

• For

Ports

Clock & Reset

Full Adder in Verilog

Testbench/Stimulus

• `