Digital System Design - Yola System Design.pdfDigital System Design ... intuitive for a user with a...

Federal Urdu University of Arts Science & Technology Islamabad Electrical Engineering

Digital System Design 1

DIGITAL SYSTEM DESIGDIGITAL SYSTEM DESIGDIGITAL SYSTEM DESIGDIGITAL SYSTEM DESIGNNNN

Prepared By:

Engr. Yousaf Hameed Lab Engineer

Electrical Engineering

BASIC ELECTRICAL & DIGITAL SYSTEMS LAB

DEPARTMENT OF ELECTRICAL ENGINEERING



Name: ____________________________________________

Registration No: ____________________________________

Roll No: ___________________________________________

Semester: _________________________________________

Batch: ____________________________________________



CCCOOONNNTTTEEENNNTTTSSS

LAB 1: INTRODUCTION TO MODELSIM ................................................................................................. 4

LAB 2: GATE LEVEL DESIGN ................................................................................................................ 13

LAB 3: DATAFLOW LEVEL DESIGN ...................................................................................................... 16

LAB 4: BEHAVIORAL LEVEL DESIGN .................................................................................................... 19

LAB 5: TO OBSERVE THE OPERATION OF 2 TO 1 LINE MUX ................................................................. 22

LAB 6: 16 BIT RIPPLE CARRY ADDER ................................................................................................... 23

LAB 7: BEHAVIORAL MODELS (LEVEL SENSITIVE & EDGE SENSITIVE) ................................................... 26

LAB 8: SEQUENTIAL CIRCUITS ............................................................................................................ 32

LAB 9: SEQUENTIAL CIRCUITS - II ....................................................................................................... 35

LAB 10: SEVEN SEGMENT DISPLAY ..................................................................................................... 39

LAB 11: CLOCK GENERATOR .............................................................................................................. 41

LAB 12: ASYNCHRONOUS COUNTER .................................................................................................. 43

LAB 13: SYNCHRONOUS COUNTER .................................................................................................... 45

LAB 14: Project



LAB 01

INTRODUCTION TO MODELSIM

ModelSim Tutorial

1. Start ModelSim 2. Create a new project

• Click on File, then New, then choose Project on the drop down menu

• Enter your project name, in this case the project is called “and2gate”

• Choose your project location, this project is stored at “C:\Temp\Projects\and2gate”

• The default library name should be work.

• Click OK button

3. You will be asked if want to create the project directory.

• Click OK button

4. Next you will be presented with the Add Items to Project Dialog. While you can use this dialog to create new

source files of add existing ones, we will not be using this option for the tutorial. We’ll add source files later so just click on the Close button



5. You now have a project by the name of “and2gate”.



6. Now we want to add a new file to our project.

• Click on File, choose Add to Project, and choose New File…

• Choose Verilog as the file type

• In the File name: box enter the desired file name, in this case the file is named “and2gate.v”

• Click on the OK button

7. The “and2gate.v” file has been added to your project.



8. Double-click on the and2gate.v to show the file contents. You are now ready to specify the and2gate module’s functionality.

9. We compete the and2gate specification as shown below..

• The line “`timescale 1ns/ 1ps” is located at the top of the file. The Verilog language uses

dimensionless time units, and these time units are mapped to “real” time units within the simulator.

`timescale is used to map to the “real” time values using the statement `timescale <time1> / <time2>,

where <time1> indicates the time units associated with the #delay values, and the <time2> indicates

the minimum step time used by the simulator. Note: Be sure to use the correct ` character. The ` is the

not the single quotation mark (‘) and is typically located on the same key as the ~. If you have errors

in your file, this may be the culprit.

• The and2gate module is also declared using “module and2gate();” and “endmodule”, but the ports are

left for us to define.

• Be sure to save the changes to the and2gate.v file by clicking on File and choosing Save.



10. We also want to add a testbench and again follow Steps 6 – 9 to add “and2gate_tb.v”. Then we add the

functionality of the testbench module as shown below.

11. After saving both “and2gate.v” and “and2gate_tb.v”, we want to check the syntax of both files.

• Click on the Compile Menu and select Compile All

• If the syntax was correct, a checkmark will appear next to each file

• If the syntax was incorrect, the window at the bottom will list the individual errors.



12. Now it’s time to simulate the design.

• Click on the Simulate menu and choose Start Simulation

• Expand the selection for the work library by click on the + symbol on the left.

• Select and2gate_tb and click OK button



13. Next we create a simulation waveform window.

• Click on File menu, choose New, then choose Windows, then choose Wave

• Add the signals that would like to monitor by dragging the signal from the middle pane to the

waveform window as shown below



14. We can simulate the design.

• Enter 5 ns as the length of time we would like to simulate for in the Run Length box and click the Run

icon as shown below.



15. Our simulation is complete. The simulation waveforms appear and we can check the and2gate module’s

functionality. Further, the $display statements included in the testbench appear in the lower window.



LAB 02

GATE LEVEL DESIGN

At gate level, the circuit is described in terms of gates (e.g. and, nand). Hardware design at this level is

intuitive for a user with a basic knowledge of digital logic design because it is possible to see a one-to-one

correspondence between the logic circuit diagram and the Verilog description.

Lab Overview In this lab you will:

• Learn modeling at gate level

• Half adder design

• Full adder design

• Multiplexer design

• Decoder design

Background: The simplest form of adder is called a Half-Adder (HA). The HA performs bit-wise addition between two

input bits. Depending on the result of the operation, the HA either sets or clears its Sum and Carry bit. A HA

can be expanded to include the logic for carry–in, and the modified unit is called the Full Adder (FA).



The verilog code for the half adder is

module HA(a,b,s,c);

input a,b;

output s,c;

xor(s,a,b);

and(c,a,b);

endmodule

The test bench of the half adder is

module testbench_HA();

reg a,b;

wire s,c;

HA HA_inst(a,b,s,c);

initial

begin

a=0; b=0;

#10 a=0; b=1;

#10 a=1; b=0;

#10 a=1; b=1;

end

endmodule

We can use the half adder to design a full adder as shown in figure 1.3. The full adder takes an extra bit as

input for carry in.



The verilog code of full adder is

module FA(a,b,cin,s,cout);

input a,b,cin;

output s,cout;

wire c0, s0, c1;

HA HA_inst0(a,b,s0,c0);

HA HA_inst1(cin,s0,s,c1);

or(cout, c1,c0);

endmodule



LAB 03

DATAFLOW LEVEL DESIGN

Dataflow modeling provides a powerful way to implement a design. Verilog allows a circuit to be

designed in terms of the data flow between registers and how a design processes data rather than

instantiation of individual gates.

Lab Overview

In this lab you will:

• Learn modeling at dataflow level

• Half adder design (dataflow)

• Full adder design (dataflow)

• 4-bit adder design

• 12-bit Carry Select Adder (CSA)

• Multiplexer design (dataflow)

• Decoder design (dataflow)

Background:

The simplest form of adder is called a Half-Adder (HA). The HA performs bit-wise addition between

two input bits. Depending on the result of the operation, the HA either sets or clears its Sum and Carry bit.

A HA can be expanded to include the logic for carry–in, and the modified unit is called the Full Adder (FA).



The verilog code for the half adder at dataflow level is

module HA(a,b,s,c);

input a,b;

output s,c;

assign s = a^b;

assign c = a&b;

// assign {s,c} = a+b;

endmodule



reg a,b;

wire s,c;


initial

begin

a=0; b=0;

#10 a=0; b=1;

#10 a=1; b=0;

#10 a=1; b=1;

end

endmodule



We can use the half adder to design a full adder as shown in figure 2.3. The full adder takes an extra

bit as input for carry in.

The verilog code of full adder at dataflow level is


input a,b,cin;

output s,cout;

wire c0, s0, c1;



assign cout = c1 | c0;

assign {s,cout} = a + b + cin;

endmodule



LAB 04

BEHAVIORAL LEVEL DESIGN

With the increasing complexity of digital design, it has become vitally important to make wise design decisions early in

a project. Designers need to be able to evaluate the trade-offs of various architectures and algorithms before they

decide on the optimum architecture and algorithm to implement in hardware. Thus, architectural evaluation takes

place at an algorithmic level where the designers do not necessarily think in terms of logic gates or data flow but in

terms of the algorithm they wish to implement in hardware. They are more concerned about the behavior of the

algorithm and its performance. Only after the high-level architecture and algorithm are finalized, do designers start

focusing on building the digital circuit to implement the algorithm.

Verilog provides designers the ability to describe design functionality in an algorithmic manner. In other words, the

designer describes the behavior of the circuit. Thus, behavioral modeling represents the circuit at a very high level of

abstraction.

Lab Overview

In this lab you will:

• Learn modeling at dataflow level

• Half adder design (dataflow)

• Full adder design (dataflow)

• 4-bit adder design

• 12-bit Carry Select Adder (CSA)

• Multiplexer design (dataflow)

• Decoder design (dataflow)

Background:

The simplest form of adder is called a Half-Adder (HA). The HA performs bit-wise addition between two input bits.

Depending on the result of the operation, the HA either sets or clears its Sum and Carry bit. A HA can be expanded to

include the logic for carry–in, and the modified unit is called the Full Adder (FA).

At behavioral level you don’t need to know the structural model but you are only concerned with the behavioral of a

circuit. Comments have been added in the code which give a feel for behavioral level coding.



The verilog code for the half adder at behavioral level is

module HA(a,b,s,c);

input a,b;

output s,c;

reg s,c;

always @(a or b)

begin

s= a^b;

c = a&b;

//OR {s,c} = a+b;

end

endmodule



reg a,b;

wire s,c;


initial

begin

a=0; b=0;

#10 a=0; b=1;

#10 a=1; b=0;

#10 a=1; b=1;

end

endmodule



You can use the half adder to design a full adder. The full adder takes an extra bit as input for carry in.

The Verilog code of full adder at behavioral level is


input a,b,cin;

output s,cout;

wire c0, s0, c1;



assign cout = c1 | c0;

// OR

// always @(a or b or cin)

//{s,cout} = a+b+cin;

endmodule



LAB 05

TO OBSERVE THE OPERATION OF 2 TO 1 LINE MUX

The Verilog code of 2 to 1 line multiplexer at dataflow level is

module mux(i0,i1,selct,m,n,out);

input i0,i1,selct;

output m,n,out;

assign m=i0&selct;

assign n=i1&~selct;

assign out=m|n;

endmodule

The test bench of 2 to 1 line multiplexer is

module testbench_mux;

reg i0,i1,selct;

wire m,n;

mux ff(i0,i1,selct,m,n,out);

initial

begin

i0=1'b0;i1=1'b1;selct=1'b1; //inputs a=0 and b=1

#10 i0=1'b0;i1=1'b1;selct=1'b0;

#10

$finish;

end

endmodule

Lab Tasks:

1. Write a verilog code for 2 to 1 line multiplexer in behavioral level

2. Write a verilog code for 4 to 1 line multiplexer in behavioral level.



Lab 06

16 BIT RIPPLE CARRY ADDER



DESIGN HIERARCY OF A 16-BIT RIPPLE-CARRY ADDER

module Add_rca_16 (sum, c_out, a, b, c_in);

output [15: 0] sum;

output c_out;

input [15: 0] a, b;

input c_in;

wire c_in4, c_in8, c_in12;

Add_rca_4 M1 (sum[3:0], c_in4, a[3:0], b[3:0], c_in);

Add_rca_4 M2 (sum[7:4], c_in8, a[7:4], b[7:4], c_in4);

Add_rca_4 M3 (sum[11:8], c_in12, a[11:8], b[11:8], c_in8);

Add_rca_4 M4 (sum[15:12], c_out, a[15:12], b[15:12], c_in12);

endmodule

module Add_rca_4 (sum, c_out, a, b, c_in);

output [3: 0] sum;

output c_out;

input [3: 0] a, b;

input c_in;

wire c_in2, c_in3, c_in4;

Add_full M1 (sum[0], c_in2,a[0], b[0], c_in);

Add_full M2 (sum[1], c_in3, a[1], b[1], c_in2);

Add_full M3 (sum[2], c_in4, a[2], b[2], c_in3);

Add_full M4 (sum[3], c_out, a[3], b[3], c_in4);

endmodule



module Add_full (sum, c_out, a, b, c_in);

output sum, c_out;

input a, b, c_in;

wire w1, w2, w3;

Add_half M1 (w1, w2, a, b);

Add_half M2 (sum, w3, w1, c_in);

or M3 (c_out, w2, w3);

endmodule

module Add_half (sum, c_out, a, b);

output sum, c_out;

input a, b;

wire c_out_bar;

xor M1 (sum, a, b);

and M2 (c_out, a, b);

endmodule

Test Bench

module test_Add_rca_16 ();

wire [15: 0] sum;

wire c_out;

reg [15: 0] a, b;

reg c_in;

Add_rca_16 M1 (sum, c_out, a, b, c_in);

initial

begin

#10 a = 16'h0000; b = 16'h0000; c_in = 0;

#10 a = 16'h000f; b = 16'h000c; c_in = 0;

#10 a = 16'h000f; b = 16'h000c; c_in = 1;

#10 a = 16'h0000; b = 16'h0000; c_in = 1;

#10 a = 16'h000f; b = 16'h0001; c_in = 0;

#10 a = 16'h000f; b = 16'h0001; c_in = 1;

$finish;

end

endmodule



Lab 07 BEHAVIORAL MODELS (LEVEL SENSITIVE & EDGE SENSITIVE)

A. (Continuous Assignment Statement)

Lab 5.1 (Continuous Assignment Statement)



Lab 5.2 (Continuous Assignment Statement with Conditional Operator)



Lab 5.3 (Continuous Assignment Statement with Conditional Operator)



B. Cyclic behavioral models of flip flops and latches

Cyclic behaviors are used to model (and synthesize) both levels- sensitive and edge – sensitive (synchronous) behavior (e.g flip flop) Lab 5.4



Blocking and Non-Blocking Assignment

1. Blocking (the = operator)

With blocking assignments each statement in the same time frame is executed in sequential order within their blocks. If there is a time delay in one line then the next statement will not be executed until this delay is over.

initial begin a = 4; b = 3; example 1 #10 c = 18; #5 d = 7; end

Above, at time=0 both a and b will have 4 and 3 assigned to them respectively and at time=10, c will equal 18 and at time=15, d will equal 7.

2. Non-Blocking (the <= operator)

Non-Blocking assignments tackle the procedure of assigning values to variables in a totally different way. Instead of executing each statement as they are found, the right-hand side variables of all non-blocking statements are read and stored in temporary memory locations. When they have all been read, the left-hand side variables will be determined. They are non-blocking because they allow the execution of other events to occur in the block even if there are time delays set.

integera,b,c; initial begin a = 67; #10; a <= 4; example 2 c <= #15 a; d <= #10 9; b <= 3; end

This example sets a=67 then waits for a count of 10. Then the right-hand variables are read and stored in tempory memory locations. Here this is a=67. Then the left-hand variables are set. At time=10 a and b will be set to 4 and 3. Then at time=20 d=9. Finally at time=25, c=a which was 67, therefore c=67.

Note that d is set before c. This is because the four statements for setting a-d are performed at the same time. Variable d is not waiting for variable c to complete its task. This is similar to a Parallel Block.

This example has used both blocking and non-blocking statements. The blocking statement could be non-blocking, but this method saves on simulator memory and will not have as large a performance drain.



Application of Non-Blocking Assignments

We have already seen that non-blocking assignments can be used to enable variables to be set anywhere in time without worrying what the previous statements are going to do.

Another important use of the non-blocking assignment is to prevent race conditions. If the programmer wishes two variables to swap their values and blocking operators are used, the output is not what is expected:

initial begin x = 5; y = 3; end example 3 always @(negedge clock) begin x = y; y = x; end

This will give both x and y the same value. If the circuit was to be built a race condition has been entered which is unstable. The compliler will give a stable output, however this is not the output expected. The simulator assigns x the value of 3 and then y is then assigned x. As x is now 3, y will not change its value. If the non-blocking operator is used instead:

always @(negedge) begin x <= y; example 4 y <= x; end

both the values of x and y are stored first. Then x is assigned the old value of y (3) and y is then assigned the old value of x (5).



Lab 08 SEQUENTIAL CIRCUITS

Computers and other digital systems that have memory or that execute a sequence of operations under the direction of stored information are referred to as “sequential machines” and their circuitry is modeled by sequential logic. Sequential

machines do not behave like combinational logic because the outputs of a sequential machine depend on the history of the applied inputs as well as on their present value. The history of the inputs applied to a sequential machine is represented

by the state of the machine and requires hardware elements that store information; that is, it requires memory to store

the state of the machine as an encoded binary word.

Lab Overview In this lab you will: • Flip flop designs • D_FF • JK_FF • T_FF • Sequential machine design using flip flop

Background: There are two main types of sequential circuits and their classification depends on the timing of their signals.

1. A synchronous sequential circuit is a system whose behavior can be defind from the knowledge of its signals at discrete

instant of time

2. The behavior of an asynchronous sequential circuit depends upon the input signals at any time and the order in which

the inputs change.

The storage elements used in clocked sequential circuit are called flip flops. A flip flop is a binary storage device capable

of storing one bit of information. The state of a flip flop can change only during a clock pulse transition. Latches are used

to model asynchronous circuits. A latch also holds one bit value but the state of the latch can change with changes in

inputs and does not require synchronization with clock pulse.

In this lab we will learn to model different flip flops using Verilog. D_FF, JK_FF and T_FF are the common flip flops

used in synchronous sequential circuits. Function table are used to describe different flip flops. D_FF is the simplest of

the flip-flops because its next state is equal to its present state

Table 1 D Flip-Flop

D Q(t+1)

0 0

1 1

JK_FF has its next state equal to its present state when inputs J and K are both equal to 0. When K=1 and J=0, the clock

resets the flip-flop and Q(t+1) = 0. With J=1 and K=0, the flip-flops sets and Q(t+1) =1. When both J and k are equal

to 1, the next state changes to the complement of the present state.



Table 2 JK Flip-Flop J K Q(t+1)

0 0 Q(t)

0 1 0

1 0 1

1 1 Q’(t+1)

T_FF toggles when the T=1 otherwise the state of T_ff does not change.

Table 3 T Flip-Flop T Q(t+1)

0 Q(t)

1 Q’(t+1)

Lab Tasks:

1. Write verilog code for D flip flop and write a test bench to verify the design.

2. Write verilog code for JK flip flop and write a test bench to verify the design.

3. Write verilog code for T flip flop and write a test bench to verify the design.

4. Write verilog code for the figure 1.

5. Write a test bench to verify the design as shown in the table 4.

Figure 1

Table 4 BCD to Exess-3 code Decimal Digit 8-4-2-1 code

(BCD)

Excess-3 code

0 0000 0011

1 0001 0100

2 0010 0101



3 0011 0110

4 0100 0111

5 0101 1000

6 0110 1001

7 0111 1010

8 1000 1011

9 1001 1100

Documentation

Submit the codes along with the wave diagrams for the D, JK, T flip flops and BCD to excess-3 code converter.



Lab 09 SEQUENTIAL CIRCUITS - II

Unlike combinational logic, whose output is an immediate function of only its present inputs, sequential logic depends on

the history of its inputs. This dependency is expressed by the concept of “state” The future behavior of a sequential

machine is completely characterized by its input and its present state.

Lab Overview In this lab you will learn:

• State machines

• State diagrams

• State machine design in Verilog

Background: Finite State Machines are used to model Sequential circuits since the states of the sequential circuits change depending

upon the inputs at the clock edge. A state diagram is used to describe the sequential behavior of the circuit showing the

transition of states according to the inputs. Here a traffic light controller example is presented to show the Verilog coding

of Finite state machine.

Example: Traffic light controller

The following specifications must be considered:

1. The traffic signal for the main highway gets highest priority because cars are continuously present on the

main highway. Thus, the main highway signal remains green by default.

2. Occasionally, cars from the country road arrive at the traffic signal. The traffic signal for the country road must

turn green only long enough to let the cars on the country road go.

3. As soon as there are no cars on the country road, the country road traffic signal turns yellow and then red and

the traffic signal on the main highway turn green again.

4. There is a sensor to detect cars waiting on the country road. The sensor sends a signal X as input to the

controller. X = 1 if there are cars on the country road; otherwise, X= 0.

The state machine diagram and the state definitions for the traffic signal controller are shown in the following figure



Figure 5.2 State diagram

Table 5.1 State and output signals

The traffic signal controller module can be designed with behavioral Verilog constructs module sig_control (hwy, cntry, X, clock, clear);

//I/O ports output [1:0] hwy, cntry;

//2-bit output for 3 states of signal //GREEN, YELLOW, RED;

reg [1:0] hwy, cntry;

//declared output signals are registers input X;

//if TRUE, indicates that there is car on //the country road, otherwise FALSE

input clock, clear;

parameter RED = 2'd0, YELLOW = 2'd1, GREEN = 2'd2;

//State definition HWY CNTRY parameter S0 = 3'd0, //GREEN RED

S1 = 3'd1, //YELLOW RED



S2 = 3'd2, //RED RED S3 = 3'd3, //RED GREEN S4 = 3'd4; //RED YELLOW

//Internal state variables reg [2:0] state; reg [2:0] next_state;

//state changes only at positive edge of clock always @(posedge clock)

if (clear) state <= S0; //Controller starts in S0 state

else state <= next_state; //State change

//Compute values of main signal and country signal always @(state)

begin hwy = GREEN; //Default Light Assignment for Highway light cntry = RED; //Default Light Assignment for Country light case(state) S0: ; // No change, use default S1: hwy = YELLOW; S2: hwy = RED; S3: begin

hwy = RED; cntry = GREEN;

end S4: begin

hwy = RED; cntry = YELLOW;

end endcase

end

//State machine using case statements always @(state or X)

begin case (state)

S0: if(X) next_state = S1;

else next_state = S0;

S1: begin next_state = S2;

end S2: begin

next_state = S3; end S3: if(X)

next_state = S3; else

next_state = S4; S4: begin

next_state = S0; end

default: next_state = S0; endcase

endmodule



Lab Tasks:

1. Write verilog code. 2. Write a test bench to verify the design

Documentation Submit the code along with the wave diagrams for the sequence detector



Lab 10 SEVEN SEGMENT DISPLAY



Lab 11

CLOCK GENERATOR



Lab 12 ASYNCHRONOUS COUNTER

Asynchronous Decade Counter

This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting

from "0000" until it reaches an output "1010" (decimal 10). Both outputs QA and QD are now equal to logic

"1" and the output from the NAND gate changes state from logic "1" to a logic "0" level and whose output is

also connected to the CLEAR ( CLR ) inputs of all the J-K Flip-flops.

This signal causes all of the Q outputs to be reset back to binary "0000" on the count of 10.

Once QAand QD are both equal to logic "0" the output of the NAND gate returns back to a logic level "1" and

the counter restarts again from "0000". We now have a decade or Modulo-10 counter.

Decade Counter Truth Table

Clock Count

Output bit Pattern Decimal Value QD QC QB QA

1 0 0 0 0 0

2 0 0 0 1 1

3 0 0 1 0 2

4 0 0 1 1 3

5 0 1 0 0 4

6 0 1 0 1 5

7 0 1 1 0 6

8 0 1 1 1 7

9 1 0 0 0 8

10 1 0 0 1 9

11 Counter Resets its Outputs back to Zero

Decade Counter Timing Diagram



Using the same idea of truncating counter output sequences, the above circuit could easily be adapted to other counting cycles be simply changing the connections to the NAND gate. For example, a scale-of-twelve (modulo-12) can easily be made by simply taking the inputs to the NAND gate from the outputs at "QC" and "QD", noting that the binary equivalent of 12 is "1100" and that output "QA" is the least significant bit (LSB).



Lab 13 SYNCHRONOUS COUNTER

Binary 4-bit Synchronous Counter

It can be seen that the external clock pulses (pulses to be counted) are fed directly to each J-K flip-flop in

the counter chain and that both the J and K inputs are all tied together in toggle mode, but only in the first

flip-flop, flip-flop A (LSB) are they connected HIGH, logic "1" allowing the flip-flop to toggle on every clock

pulse. Then the synchronous counter follows a predetermined sequence of states in response to the

common clock signal, advancing one state for each pulse.

The J and K inputs of flip-flop B are connected to the output "Q" of flip-flop A, but the J and K inputs of flip-

flops C and D are driven from AND gates which are also supplied with signals from the input and output of

the previous stage. If we enable each J-K flip-flop to toggle based on whether or not all preceding flip-flop

outputs (Q) are "HIGH" we can obtain the same counting sequence as with the asynchronous circuit but

without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time. As there is

no propagation delay in synchronous counters because all the counter stages are triggered in parallel the

maximum operating frequency of this type of counter is much higher than that of a similar asynchronous

counter.

4-bit Synchronous Counter Waveform Timing Diagram.



Because this 4-bit synchronous counter counts sequentially on every clock pulse the resulting outputs count upwards from 0 ( "0000" ) to 15 ( "1111" ). Therefore, this type of counter is also known as a 4-bit Synchronous Up Counter. As synchronous counters are formed by connecting flip-flops together and any number of flip-flops can be connected or "cascaded" together to form a "divide-by-n" binary counter, the modulo's or "MOD" number still applies as it does for asynchronous counters so a Decade counter or BCD counter with counts from 0 to 2n-1 can be built along with truncated sequences.

Decade 4-bit Synchronous Counter A 4-bit decade synchronous counter can also be built using synchronous binary counters to produce a count sequence from 0 to 9. A standard binary counter can be converted to a decade (decimal 10) counter with the aid of some additional logic to implement the desired state sequence. After reaching the count of "1001", the counter recycles back to "0000". We now have a decade or Modulo-10 counter. Decade 4-bit Synchronous Counter

The additional AND gates detect when the sequence reaches "1001", (Binary 10) and causes flip-flopFF3 to toggle on the next clock pulse. Flip-flop FF0 toggles on every clock pulse. Thus, the count starts over at



"0000" producing a synchronous decade counter. We could quite easily re-arrange the additionalAND gates to produce other counters such as a Mod-12 Up counter which counts 12 states from"0000" to "1011" (0 to 11) and then repeats making them suitable for clocks. Synchronous Counters use edge-triggered flip-flops that change states on either the "positive-edge" (rising edge) or the "negative-edge" (falling edge) of the clock pulse on the control input resulting in one single count when the clock input changes state. Generally, synchronous counters count on the rising-edge which is the low to high transition of the clock signal and asynchronous ripple counters count on the falling-edge which is the high to low transition of the clock signal.

It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state, but this makes it easier to link counters together because the most significant bit (MSB) of one counter can drive the clock input of the next. This works because the next bit must change state when the previous bit changes from high to low - the point at which a carry must occur to the next bit. Synchronous counters usually have a carry-out and a carry-in pin for linking counters together without introducing any propagation delays.

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