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Digital Sampling OscilloscopeMary Anne Peters & Joseph Tylka

Department of Mechanical and Aerospace EngineeringPrinceton University, Princeton, NJ 08544, USA

INTRODUCTION

This paper summarizes the construction and operationof a digital sampling oscilloscope, built from discreteanalog and digital components, featuring an Arduinomicrocontoller. In Sec. I, we provide an overview ofthe primary components of the oscilloscope. We alsoprovide some background and historical information onoscilloscopes in general. In Sec. II, we describe, in detail,the circuit theory behind each of the main componentsof the oscilloscope. We also discuss our specific imple-mentation of these circuits in our oscilloscope, as well asthe mechanisms we have implemented for user control,data retrieval, and waveform display. In Sec. III, we dis-cuss the performance of the various components of ouroscilloscope and display some captured data. Finally, inSec. IV, we summarize the oscilloscope’s performance,discuss some issues we faced in our construction processand the lessons learned. We include circuit diagrams ofour oscilloscope as well as some of the larger figuresin the Appendix. Also included in the Appendix areparts lists for our specific construction and the Arduinomicrocontroller code. We refer the interested reader tomanufacturer datasheets1 for each component in the partslist for additional information.

I. OVERVIEW

In this section we will give an overview of the digitalsampling oscilloscope’s primary functions, as well asan overview of the layout of the paper. The purpose ofthe digital sampling oscilloscope is to capture a voltagesignal and save it to memory in order to later retrieve anddisplay the signal. An oscilloscope is advantageous overa voltmeter because it extracts and displays high timeresolution waveforms of oscillating (AC) and transientsignals over a given time interval rather than providinga single time-averaged measurement.

The input stage of the oscilloscope consists of avariable DC voltage offset control and a variable gaincontrol which allow the user to best display the capturedsignal. Since the analog to digital conversion (ADC)

1Most datasheets can be found by simply performing a Googlesearch for the part numbers listed in Tab. IV in the Appendix.

process takes a finite amount of time to complete, thesignal is fed through a sample and hold circuit priorto the ADC chip. This step ensures that the voltageat the input of the ADC is constant over the durationof the conversion process. The digital representation ofthe sampled signal is then sent through a buffer to astatic RAM (SRAM) chip. The data can then be readout through two digital to analog converters (DACs),one of which converts the SRAM addresses to provide atime scale, while the other converts the data stored in theSRAM to recreate the voltage signal. The analog outputsof the two DACs are sent to an analog display whichplots the signals against each other. The data from theSRAM is also read by an Arduino Nano microcontrollerand sent to a desktop computer via USB to be displayedin National Instruments’ LabView. Figure 1 shows themain components of the oscilloscope as well as the userinputs, propagation of information and control signalsthroughout the system.

A. Background

Before discussing the details of our project it isvaluable to briefly examine the history of oscilloscopes.Andre-Eugene Blondel invented the electromagnetic os-cillograph in 1893 which used a galvanometer to trace apen across a roll of paper to capture a waveform.2 Thesefirst oscillographs were limited to a frequency range of10 to 19 Hz due to the mechanical recording limitations(i.e. how fast the pen could move across the paper). Thelight-beam oscilloscope used a mirror and photographicplates to record the data improved upon this design. Itcould capture higher frequency signals up to about 500Hz.

Ferdinand Braun invented the cathode ray tube (CRT)oscillograph in 1897. In the late 1930s, the company A.C. Cossor designed a dual-beam oscilloscope. It appliedan oscillating sawtooth reference signal to horizontaldeflector plates and the measured input signal to verticaldeflector plates, creating a “sweep” of the input signal as

2Pereira, J.M.D. The History and Technology of Oscilloscopes,IEEE Instru. & Meas. Mag., vol. 9, pp. 27-35, 2006

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INPUT STAGE

CLOCK UNIT

SAMPLE & HOLD

ADC SRAM

ARDUINO

DAC

DAC

CTRL

VIN

COUNTER

RATE SELECT SWITCHES

CLOCK

START

DATA

EOC

WRITE SWEEP PUSH BUTTON

ADDR

DATA

BIT

9 CTRL

ANALOG IN

ANALOG OUT (Y signal)

ANALOG OUT (T signal)

GAIN

OFFSET

LABVIEW USB

Fig. 1. Block diagram illustrating the primary components of the sampling oscilloscope. Boxes with solid lines correspond to the one ormore circuit components shown in each OrCAD schematic in the Appendix. Boxes with dashed lines may include user inputs (i.e. the gainand offset knobs, the sampling frequency rate selection switches, and the write sweep push button) to indicate the contents of each individualOrCAD drawing.

a function of time on a phosphor display screen. How-ever, this oscilloscope still had issues with drift becausethere was no fixed reference point for synchronizingthe horizontal and vertical signals. In order to obtain asteady, repeating the signal on the display, the user hadto tune the reference sawtooth signal until the signal nolonger drifted across the display. In 1946 this problemwas addressed by Howard Vollum’s and Jack Murdock’sinvention of the triggered oscilloscope, which synchro-nizes of oscillatory waveforms by triggering at a givenpoint on the signal. The Tektronix foundation (foundedby Vollum and Murdock) refined this design for thecommercial market and became the first manufacturerof the calibrated oscilloscope.

In 1981, Walter LeCroy filed a patent for the firstdigital oscilloscope.3 This eliminated the necessity forhorizontal and vertical plates to be used to display asweep in the analog CRT oscilloscope. A digital oscil-loscope uses an ADC to convert the analog inputs todigital signals, and saves those signals to memory tobe displayed on a digital screen (e.g. an LCD display).Modern oscilloscopes feature very high input impedance(typically ∼ 1 MΩ) to effectively isolate the circuit beingmeasured from the oscilloscope, and are able to measuresignals with frequency content up to ∼ 10 GHz. How-ever, this bandwidth is often limited by the capacitance ofthe cables used to probe the circuit. Essentially, the cableacts like a low pass filter since the conductors have someseries resistance and capacitance to ground. Anothercommon feature of modern oscilloscopes is a “scope

3LeCroy, W.O. Test Probe, US Patent 4423373, Filed March 16,1981, Issued December 27, 1983

probe” with an adjustable input impedance allowing theuser two choose between an input impedance of 1× or10× that of the oscilloscope. This probe is designedto have very little capacitance to ground, to allow ahigher frequency range than typical coaxial BNC cables.Modern day instruments also have the ability isolate theAC component of a signal, by setting the oscilloscope tothe “AC coupling” mode. This is particularly useful whenthe input signal has a large offset, but the user is onlyinterested in rapid fluctuations in the signal. However,this removal of the DC offset is often achieved bysimply introducing a “blocking” series capacitor, whichwill tend to filter out low frequency signals in additionto removing the DC offset. Alternatively, oscilloscopeshave a DC coupling mode, which does not employ aseries capacitor. Thus to maximize the bandwidth ofthe oscilloscope, users typically utilize the scope probeon the DC coupling mode. The oscilloscope we havebuilt and will discuss in this report is a digital samplingoscilloscope that operates on the same principles at theone patented by LeCroy in 1981.

II. OSCILLOSCOPE SUBSYSTEMS

In this section we will discuss the circuit theory andimplementation of each of the oscilloscope’s subsystems,as well as the principles of operation and implementationof external systems such as the Arduino and LabView.Each of the following subsections details the functionand operation of a subsystem of the oscilloscope, begin-ning with the input stage. The final paragraph in eachsubsection summarizes the various inputs and outputsof each subsystem, as well as any mechanisms for userinput.

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A. Input Stage

The input stage of the oscilloscope consists of com-ponents which allow the user to adjust the gain andDC offset of the input signal. The analog input signalis sent through a series of three operational amplifiers(op-amps), as shown in Fig. 14 in the Appendix. Thepower rails of the op-amps are connected to ±12 V,meaning the voltage range throughout the entire inputstage is ±12 V. However, as we will see in Sec. II-C,the sample and hold circuit will clip any signals outsideof the range ±5 V. Thus, our oscilloscope is capable ofaccepting signals up to a maximum amplitude of ±12V, but must fit within the range of ±5 V at the outputof the input stage by removing any DC offset, applyinga gain of < 1, or both.

The first op-amp is wired in a voltage follower config-uration. This configuration uses feedback to ensure thatthe output of the op-amp matches its input (Vout = Vin).Essentially, the op-amp works to minimize the voltagedifference between its inverting and non-inverting inputs,thus reproducing the input at the output. This step servesto increase the input impedance of the entire oscilloscopeto that of the op-amp (∼ 1 MΩ), which will effectivelyisolate our oscilloscope from whatever circuit we con-nect to the input. That is to say, the oscilloscope doesnot draw very much current from the external circuit,so the behavior of that circuit will remain essentiallyunchanged. This is the benefit of high input impedanceson voltage measuring devices.

The output of the voltage follower is sent into asecond op-amp, configured as a linear inverting summingamplifier. This circuit creates a variable DC offset, whichis controlled by adjusting the position of the knob (i.ethe wiper) of a potentiometer whose other terminals areconnected to ±5 V, allowing for a DC offset of up to ±5V. In our case, we use a 100 kΩ potentiometer, but thisvalue is not critical, provided that the power dissipatedby the potentiometer (P = ∆V 2/Rpot) is reasonable(typically < 1/2 W). The output of the voltage followerand the wiper are connected to the inverting input of thesecond op-amp through individual resistors. The outputof the op-amp is fed back to the inverting input and thenon-inverting input is grounded. Thus, the voltage at theoutput of the summing amplifier can be calculated usingthe two ideal op-amp “golden rules”:

1) The voltage difference between the inputs is zero.2) The current flow into (or out of) each input is zero.

Employing these rules requires that all current flowingfrom the potentiometer and the voltage follower mustpass through the feedback resistor. Also, the voltage at

TABLE IINPUT STAGE CHARACTERISTICS

Parameter ValueInput Signal Range ±12 VSignal Range of S/H ±5 VDC Offset Range ±5 VMaximum Gain 20×Output Signal Range ±5 V

the inverting input must be zero.4 Carrying out the circuitanalysis using Kirchhoff’s laws results in the expressiongiven in Eq. (1), shown below.

Vout = −Rf

(V1R1

+V2R2

)(1)

In this equation, Rf refers to the feedback resistanceand R1 and R2 refer to the resistances connecting theinverting input to the signals V1 and V2, respectively. Inour case, the three resistors for the summing amplifierall have the same resistance (10 kΩ), so R1 = R2 = Rf

and thus the overall gain is simply −1 (inverting). Theoutput of the voltage follower (i.e. the input signal) isV1 and the DC voltage at the wiper of the potentiometeris V2.

The third op-amp is configured as a linear invertingamplifier used for variable gain amplification. Againemploying the ideal op-amp rules and Kirchhoff’s laws,we calculate the gain of the inverting amplifier, which isgiven by Eq. (2), shown below.

Vout = −Rf

RinVin (2)

In this equation, Rin is the resistance connecting theinverting input to the signal Vin. In our case Rf is a vari-able resistor with 0 < Rf < 10 kΩ and Rin = 470 Ω,thus we can apply a maximum gain of approximately20× to the input signal. We see again that this amplifierinverts the signal, resulting in a non-inverted signal atthe output of the third op-amp, hence there is no needfor an additional inverting amplifier. Table I summarizesthe voltage range and gain characteristics of the inputstage.

We note that the variable offset and gain circuits couldhave been combined into a single op-amp circuit, simplyby making the feedback resistance of the summing am-plifier adjustable. However, we intentionally implementtwo separate op-amps to allow for more independentcontrol for both the offset and gain. Specifically, theoffset control is completely independent of the gain, yetthe gain control will amplify any DC offset as well

4The op-amp creates what is known as a “virtual ground” at theinverting input.

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TABLE IICLOCK UNIT RATE SELECTION

Rate Setting ADC Clock Sampling Frequency×1 7.2 kHz 150 Hz×8 57.6 kHz 1.2 kHz×16 115.2 kHz 2.4 kHz×64 460.8 kHz 9.6 kHz

as the signal. We also note that a more complicatedcircuit could have been used to implement completelyindependent gain and offset. This circuit would requirean initial variable DC offset summing circuit, to removeany DC offset from the original signal,5 a variablegain linear amplifier to adjust the gain only on the ACcomponent of the signal, and finally a second variableDC offset summing circuit, to add any desired offset.

To summarize, the input stage receives an analog inputsignal, and features two control knobs, allowing the userto adjust the DC offset and gain on the signal. The outputof the input stage is sent to the input of the sampleand hold circuit, to be discussed in Sec. II-C. First, wediscuss the clock unit, which will also play a role in thesample and hold circuit.

B. Clock Unit

The clock unit of the oscilloscope is responsible forproviding the relevant clocks to the digital circuits aswell as necessary control signals. The main clock signalsare provided by a bit rate generator which divides downthe frequency of the signal from a crystal oscillator togenerate many different frequency clock signals. In ourcircuit, two clock signals are taken from the bit rategenerator, the first of which is used as the clock for theADC chip, while the other sets the sampling frequency.The frequency of the ADC clock is chosen to be 48×times the sampling frequency, to allow adequate time forthe analog to digital conversion process to complete. Auseful feature of the bit rate generator is that it has fourdifferent rate selection modes, allowing the oscilloscopeto operate at any of four different sampling frequencies.The four possible clock frequency pairs are shown inTab. II. See Fig. 15 in the Appendix for the schematicof the clock and control unit circuit.

First, our circuit synchronizes the clocks by feedingthem into an edge-triggered D-type flip-flop, for whichthe data (D) input is the sampling frequency clock andthe clock input is the ADC clock. Simultaneously, theADC clock is sent to both the clock input of a 4-bit

5Alternatively, a series capacitor could be used to block the DCcomponent, but this would result in an attenuation of low frequencysignals as well.

counter and, of course, the ADC. The output of the firstflip-flop, denoted Q1, is sent to the CLR input of thecounter, to ensure that the counter is synchronized withQ1. This means that the counter only counts for thefirst 24 ADC clock pulses, and the outputs are set tological low (ground) for the next 24. The synchronizedsampling frequency clock (Q1) is also used to countthrough addresses of the SRAM, as described in Sec.II-E.

The input bits of the counter are all set to low and theoutputs are used to create the desired control signals.We denote the output bits of the counter, from leastsignificant to most significant, QA, QB, QC, and QD.Sending the signal QA ·QC to the LOAD input causesthe counter to reset to all low outputs every 6 clockpulses. This signal is also used to clock a second D-typeflip-flop, for which the data input is Q1. The output ofthe second flip-flop, denoted Q2, is a signal which is lowfor 6 ADC clock periods, high (+5 V) for the next 18,and then low again for the next 24, and repeats. Notethat we refer to Q1 and Q2 as the outputs of the firstand second D-type flip-flop chips, respectively, not to beconfused with the outputs of the first and second flip-flopcircuits on a single chip, as seen in Fig. 15. The use oftwo flip-flop chips is necessary since each chip uses asingle clock for all of its flip-flops.

The signal Q1 · Q2 creates a “window” pulse 6ADC clock periods long, which we use to gate thecontrol signals. This signal is sent simultaneously totwo “AND” gates. The first “AND” gate combines thissignal with QC to create a 4 ADC clock period longpulse, which is used by the sample and hold circuit tosample the incoming analog signal. The second “AND”gate uses QC to create a 2 ADC clock period longpulse, immediately after the first pulse, which is usedas the “start conversion” signal for the ADC. All of thetimings of the signals described above are depicted inFig. 2. The last signal shown in the figure is the “endof conversion” signal being created by the ADC, whichwill be discussed in Sec. II-D.

We note that the operation of this circuit is onlypossible due to the propagation delay inherent to thedigital logic gates. The QA ·QC signal (used to clockthe second flip-flop) has a rising edge slightly after thesynchronized sampling frequency clock has its fallingedge. Without the propagation delay, Q2 would remainhigh indefinitely, since the only rising edges arriving tothe clock input of the flip-flop would occur while thedata input (Q1) is high. This would eliminate the windowpulse, meaning no control signals would be sent throughtheir “AND” gates.

To summarize, the clock unit generates four signals

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Fig. 2. Simulated timing diagram showing the relative timings of various signals in the clock and control unit.

that are used elsewhere in the oscilloscope. One suchsignal is the ADC clock, used to clock the ADC, andchosen to have a frequency 48× times that of thesampling frequency clock. The sampling frequency clockis also generated by the clock unit, and is used to countthrough the addresses of the SRAM. The clock unit alsogenerates two consecutive control pulses at the start ofeach sampling frequency clock period. The first pulsehas a width equal to 4 ADC clock periods and is usedto control the sample and hold circuit, while the secondpulse has a width equal to 2 ADC clock periods andis used to start the analog to digital conversion process.The user is able to select the sampling frequency withtwo digital switches, yielding four different frequencies.

C. Sample and Hold

The sample and hold circuit is necessary to ensurethat the voltage at the input to the ADC is held constantover the duration of the conversion process, as anyfluctuations may result in errors in the conversion. Thecircuit consists of two voltage followers, a bilateralCMOS transistor switch, and a capacitor, as shown inFig. 16 in the Appendix. The op-amps are again poweredfrom ±12 V, and the bilateral switch is powered withVDD = +5 V and VSS = −5 V. The signal from theinput stage passes through the first voltage follower andis sent to the input of the bilateral switch. Thus anysignal outside of the range ±5 V will be clipped by

the bilateral switch. The voltage follower is necessary toisolate the bilateral switch from the input stage, so thatcurrents from the input stage are not run directly throughthe switch.

The output of the bilateral switch is connected by acapacitor to ground and also to the input of the secondvoltage follower. Thus, when the switch is closed, thefirst voltage follower charges the capacitor until thevoltage across it matches the voltage at the non-invertinginput of the first op-amp. This process is known as the“sampling” phase, since the voltage across the capacitoris continually being adjusted to match the input signal.When the switch is open, the capacitor maintains thatvoltage at the non-inverting input of the second op-amp.This state is known as the “holding” phase. The secondvoltage follower serves to isolate the capacitor from thesubsequent electronics.

The bilateral switch is electronically controlled, mean-ing setting the control voltage equal to VDD closes theswitch and setting the control voltage equal to VSS opensthe switch. In fact, due to the nature of a transistorswitch, any control voltage less than VDD−VT , where VTis some threshold voltage (typically ∼ 0.7 V), will openthe switch. Therefore, we can use a TTL level signal (+5V and 0 V), to control the switch. Thus by sending thecontrol signal from the clock unit (discussed in Sec. II-B)to the control input of the bilateral switch, we sample theinput signal for four ADC clock periods, and hold the

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final sampled voltage for forty four periods. Figure 6shows some examples of the output of the sample andhold circuit with a sinusoid input at various samplingfrequencies.

Ideally, the capacitor would be able to maintainthe held voltage constant indefinitely, but due to non-idealities such as bias currents through the op-amps(typically ∼ 80 nA), the voltage can only be held for ashort time. The voltage decay rate is given by the formulabelow.

dVCdt

=ibiasC

(3)

In this equation, VC is the voltage across the capacitorand ibias is the bias current through the op-amp. Clearly,increasing the capacitance C would decrease the voltagedecay rate, but we must also consider the charging rateof the capacitor, whose time constant is given in theequation below.

τ = (Rswitch +Ro)C (4)

In this equation, Rswitch is the resistance of the bilateralswitch in the closed position, typically ∼ 110 Ω, andRo is the output resistance of the op-amp, typically ∼75 Ω. Thus, as expected, increasing the capacitance willincrease the charging time. Hence, the capacitance valuemust be chosen to simultaneously optimize the chargingspeed and the hold time for a given sampling frequency.

In our case, we chose C to be 68 nF, which gives usa charging time constant of ∼ 13 µs. At an ADC clockspeed of 57.6 kHz (the ×8 setting), the capacitor is given∼ 70 µs to charge, which, compared to the time constant,is plenty of time. Also, the capacitor holds the voltagefor ∼ 770 µs. The voltage decay rate for this capacitanceis ∼ 1.18 V/s, yielding a total loss of ∼ 0.9 mV over theentire hold period. As our input signal range is only ±5V, this loss corresponds to a ∼ 0.01% error, which wecan tolerate, bearing in mind that the calculations aboveare based on nominal values given in the datasheets.

When the bilateral switch is closed, the capacitor alsoacts like a low pass filter. The cutoff frequency of alow pass filter is specified as the frequency at which theamplitude of the input signal is attenuated by −3 dB. Theformula for calculating the cutoff frequency is given theequation below.

fc =1

2πτ(5)

Therefore, using the time constant calculated above, thecutoff frequency of our circuit should occur around ∼12.5 kHz. We will see in Sec. III-A that the actual cutofffrequency of our circuit occurs around 16 kHz, which iseasily within the tolerance of the nominal values we usedin the above calculations.

To summarize, the sample and hold circuit receivesthe output of the input stage and the control signal fromthe clock unit as inputs, and outputs a sampled version ofthe input signal. This signal is then passed to the ADC,as will be discussed in the next subsection.

D. Analog to Digital Converter

The analog to digital converter (ADC) receives theoutput of the sample and hold circuit and calculates abinary number to represent that voltage. There are manymethods that can be used to perform this calculation,which vary in speed, accuracy, and complexity. Forexample, a “direct conversion” or “flash” ADC is rathercomplex but has a very fast conversion time. This type ofADC consists of 2N resistors and 2N − 1 comparators,where N is the number of output bits (binary digits).The ADC functions by feeding the input signal, Vin, toall of the comparators simultaneously, while the otherinputs of the comparators are connected to a discretizedrange of reference voltages, Vref . For example, an 8-bitflash ADC would have 256 resistors of equal resistancein series, with each node between resistors connecting toa different comparator’s reference input. Essentially, the255 comparators compare the input signal to all of thereference voltages and output a logical high (or “true”) ifVin > Vref or a logical low (“false”) if Vin < Vref . Theoutputs of the comparators are sent to a logic circuitwhich (almost) instantaneously determines the digitaloutput.

On the other hand, a ramp comparison ADC is verysimple but can take a long time to convert. One im-plementation of this type of ADC uses an N -bit binarycounter fed into an N -bit DAC (see Sec. II-G) to createa staircase-like ramp. The input signal is compared tothe ramp signal using a comparator so that the instantwhen the output of the comparator changes correspondsto the ramp voltage crossing the input signal voltage.Thus the output bits of the counter at that instant areprecisely the digital representation of the analog inputsignal. Clearly, this method will be much slower thanthe flash ADC, since this ADC must count through allof the possible digital values. Therefore the speed of theADC depends on the clock speed of the counter, and theconversion time increases as the resolution (number ofbits) increases.

In our oscilloscope, we use a clocked 8-bit successiveapproximation ADC, which systematically determinesthe 8-bit number which corresponds to the input signalvoltage, Vin, by generating various reference voltagesand comparing them to the input signal. To do this,the ADC uses a comparator, a resistor network, analog

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switches, and control logic. The resistor network consistsof 256 resistors of equal resistance in series, whichdivide the total voltage difference across the network intoevenly spaced discrete voltages, each of which is sent toone end of an analog switch. The control logic closesone of the switches to send a certain voltage, Vref , tothe reference input of the comparator, while Vin is sent tothe other input. The result of the comparison is used bythe control logic to decide which switch to close next. Byrepeating this process several times, the ADC is able todetermine which of the 256 reference voltages is nearestto that of the input signal, and represents that referencevoltage with an 8-bit number.

Our ADC determines the 8-bit output in exactly 40clock periods, which explains our choice for the ADCclock to be 48× our sampling frequency. Also, asspecified in the datasheet, the ADC requires a “startconversion” pulse between 1 and 3.5 clock periods long,which justifies our choice for a 2 clock period longpulse. This pulse tells the ADC to begin converting Vin,and causes the ADC’s output called “end of conversion”(EOC) to transition to logical low. The EOC outputremains low for the duration of the conversion process(40 clock periods) and then transitions to logical high toindicate, as the name suggests, the end of the conversionprocess. The EOC signal is simultaneously sent to thecontrol logic of the SRAM (to be discussed in Sec.II-E) and fed back to the “output enable” (OE) inputof the ADC. This input controls the data outputs on theADC, where a logical low at the OE input prevents datafrom being transmitted out from the ADC and a logicalhigh at the input allows transmission. See Fig. 17 in theAppendix for the schematic of the ADC.

The data outputs are what are known as “Tri-State”6

outputs, indicating that the output pins are always in oneof three possible states. When the OE input is high, i.e.the data outputs are enabled, the ADC sets the voltageat those pins to their designated voltages, either logicalhigh or low, as determined by the conversion process.However, when the OE input is low, i.e. the outputs aredisabled, the output pins may take on an intermediatevoltage level or a level not determined by the ADC. Thesignificance here is that the output pins are no longer“driven” to a particular value by the ADC itself, meaningthe ADC is not attempting to control the voltages at theoutputs. This allows those pins to be driven by othercomponents. For example, the outputs of the ADC couldbe connected directly to the inputs of the SRAM, whichare also its outputs. The Tri-State property of the ADC

6Tri-State is a registered trademark of National SemiconductorCorp.

outputs ensures that if the ADC’s output is disabled,those data pins can be driven by the SRAM withoutaffecting the ADC.

This feature alone does not solve every problem. Forexample, if the ADC’s outputs were enabled and theSRAM were outputting the saved data at a given address,both devices would be trying to drive their output pinsto certain levels. Thus, if, on a certain pin, the twolevels were conflicting (e.g. the ADC says high whilethe SRAM says low), we end up shorting one of thedevices, and possibly damaging one or both of the chips.Therefore, care must be taken to ensure that the outputsof the ADC will never be in conflict with another device.We discuss the steps we have taken towards this goal inSec. II-E.

To summarize, the ADC takes as inputs an analogvoltage (Vin) from the sample and hold circuit, a clocksignal from the clock unit, a start conversion pulse alsofrom the clock unit, and an output enable (OE) signalwhich is fed back directly from the end of conversion(EOC) output. The ADC passes the 8-bit data valuesto the buffer for the SRAM and the EOC signal to theSRAM’s control logic.

E. Data Storage (Buffer, Memory, and Address Counter)

The SRAM is responsible for storing a sequence of8-bit values computed by the ADC, so that the sequencemay be retrieved and displayed. The 8 digital signalsbeing sent from the ADC are passed through digitalbuffers to the data pins of the SRAM to be stored tomemory. The lowest 8 output bits of a 12-bit counter areconnected to the lowest 8 address bits of the SRAM tocount through the different addresses of the SRAM. Bysynchronizing the counter and the ADC, we can ensurethat each 8-bit value is written to a single address in theSRAM before the counter moves on to the next address.The SRAM and buffers are controlled by a “NAND”gate to coordinate the transmission of data through thebuffers and the writing and reading of data to and fromthe SRAM. The operation of the SRAM and the 12-bit counter is intimately related to the functions of theArduino, which will be touched on here, and discussedin more detail in Sec. II-F. The schematic for the SRAM,the buffers and the 12-bit counter is shown in Fig. 18in the Appendix. Note that the data input pins of theSRAM are also its data output pins.

As mentioned above, the data outputs of the ADC areconnected to the inputs of eight digital buffers. Thesebuffers are controlled such that when the voltages at thegate pins (denoted by OE in Fig. 18) are low, the outputsare enabled, meaning the buffers drive their outputs to

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TABLE IIISRAM CONTROL TRUTH TABLE

CS WE OE Operation ModeHigh × × Not SelectedLow Low × WriteLow High Low ReadLow High High Inactive

match their respective inputs. If the voltages at the gatepins are high, the outputs are disabled, and are said to bein a “high impedance” state, in that they are essentiallytreated as open circuits. Our buffer chip has two gatepins, each controlling four of the eight buffers. However,we send the same signal to both gate pins so all eightbuffers are controlled simultaneously. The control logicthat we have implemented controls both the gates on thebuffers as well as the write enable pin on the SRAM, sowe will discuss the operation of the SRAM first.

The SRAM has three control inputs which are used toput the SRAM in one of three operational modes. Thethree inputs are chip select (CS), write enable (WE,and output enable (OE). Note that each of these pinsare noted with a bar over the letters, signifying that alogical low level at the input “activates” that function.For example, the CS input requires a low level in orderto “select” (or enable) the chip. If a high level is sent tothe CS input, the chip cannot be used. In our case, wehave connected the CS input directly to ground, so thatour chip is always selected.

Provided that the chip is selected (i.e. CS is low), theWE determines if the chip is in read mode or writemode. When the WE input is low, the OE input isignored, and the chip is in write mode. In this mode,any signals arriving to the data inputs will be stored tomemory at the address specified by the signals at theaddress pins. When the WE input is high, the chip mayeither read out the data, or do nothing, depending on thestate of the OE input.

Provided that the chip is selected and is not in writemode (i.e. WE is high), if the OE input is low, theoutputs are enabled, and the SRAM reproduces, at thedata outputs, the digital values saved in memory. Thesevalues are equal to those stored at the address specifiedby the signals at the address pins. If the OE input ishigh, then the chip is essentially inactive, since it is inneither read nor write mode. The truth table describingthe different operational modes of the SRAM is given inTab. III.

The control logic for both the gates of the buffers andthe write enable input of the SRAM is a “NAND” gate.The inputs to this “NAND” gate come from the ADC

and the Arduino. Recall that a “NAND” gate produces alow voltage only if both inputs are high. If either inputis low, the other input is irrelevant and the output ofthe “NAND” gate must be high. The signal from theArduino is high for exactly the time it takes for thecounter to cycle through all of the addresses7 in theSRAM. The other input of the “NAND” gate is the end ofconversion (EOC) signal from the ADC, which goes highas soon as the conversion is complete, and returns lowagain at the start of the next conversion. Recall that thissignal is fed back to the output enable (OE) input of theADC, meaning that the data is only fed into the buffersduring that gap between conversions. Therefore, whenthe Arduino signal (from pin D13, to be discussed in Sec.II-F) is high, the control signal from the “NAND” gatewill go low for the exact same gap between conversions.Thus for that small window of time, the ADC’s outputsare enabled, the buffers’ outputs are enabled, and theSRAM is put into write mode. Conversely, for theentire duration of the conversion processes, the ADC’sand buffers’ outputs are disabled, and the SRAM isin read mode. We note that this causes the SRAM toessentially “hold” those values which were just writtenuntil the SRAM’s address inputs are changed. However,when the D13 signal from the Arduino is low, no datacan be written to SRAM, and the buffers’ outputs arealways disabled. Therefore, the outputs of the SRAMwill continue to read out the values stored in memory atwhatever addresses are being specified.

As mentioned above, the first 8 output bits of thecounter are connected to the first 8 address bits on theSRAM. The other 3 address bits are all connected toground. Therefore, we are essentially only using oneeighth of our memory capacity. This choice is necessarysince we use an 8-bit DAC to convert the outputs ofthe counter into a sawtooth wave. The purpose of thissawtooth wave will be explained in Sec. II-G. Thecounter is clocked by the sampling frequency clockgenerated by the clock unit, as discussed in Sec. II-B.The clock input is denoted by CLK, indicating that thefalling edge of the clock signal triggers the transition tothe next value. As can be seen from the timing diagramin Fig. 2, the SRAM’s address changes long after the datahas been written to the previous address, which occursduring the high pulse of the EOC signal.

The reset input of the counter is connected to the writesweep push button, shown in Fig. 19 in the Appendix.This means that when the user presses the button, all

7Strictly speaking, we only use a subset of the possible SRAMaddresses since we also use an 8-bit DAC to convert the addressesto an analog signal. See Sec. II-G for more details.

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of the outputs of counter are set and held low. Whenthe user releases the push button, the counter may beginto count through the addresses. The push button is alsoconnected to the Arduino input D3 (see Sec. II-F), whichmonitors that pin for a rising edge. When a rising edgeis detected, the Arduino changes its D13 output to high,indicating that the SRAM may be written to. The 9th

output bit of the counter, Q9, is sent to the Arduinoinput D2, which also monitors that pin for a rising edge.For this pin, when a rising edge is detected, the Arduinochanges its D13 output to low. Therefore, the counterbegins to count up indefinitely as soon as the push buttonis released, but once Q9 transitions from low to high, theD13 output of the Arduino becomes low, which preventsany more data from being written to the SRAM. In thisway, the SRAM is guaranteed to only cycle throughall of its addresses once without overwriting any storeddata. We note that the counter simply continues to countthrough all of its possible values, and repeats once itreaches its maximum. Therefore, Q9 will experiencemany rising edges, but this has been accounted for thein the Arduino code, as we will discuss in Sec. II-F.

The data inputs/outputs of the SRAM are connectedboth to the data inputs of an 8-bit DAC and to 8 digitalinputs of the Arduino, to be discussed in Sec. II-G andSec. II-F, respectively. The lowest 8 output bits of thecounter are also connected to an 8-bit DAC (also in Sec.II-G). These connections will allow us multiple ways ofdisplaying our captured waveforms.

To summarize, the digital outputs of the ADC aresent via the digital buffers into the data inputs of theSRAM. The data inputs of the SRAM are simultaneouslyconnected to the data inputs of an 8-bit DAC and 8digital inputs of the Arduino. The “NAND” gate receivesan input from the Arduino’s D13 output as well asthe ADC’s EOC signal. This control logic coordinatessending data through the buffers as well as writing thatdata to the SRAM. The 12-bit counter which countsthrough the addresses of the SRAM is clocked by thesampling frequency clock generated in the clock unitand is reset when the user presses the write sweep pushbutton. The addresses of the SRAM are also sent to an8-bit DAC, and the Q9 output of the counter is sent tothe Arduino.

F. Arduino Nano Microcontroller

As is evident in the previous section, the Arduinoplays an integral role in the operation of our oscilloscope.It is responsible for initializing the procedure to fill theSRAM with data corresponding to one sweep of the inputsignal. Additionally, the Arduino reads the data that is

present at the data input/output pins of the SRAM andsends those 8 bits as a byte across a serial line to thecomputer. The data can then be viewed in LabView,as will be discussed in Sec. II-H. The write sweeppush button is connected to the Arduino, which the userpresses to start the writing process. The schematic forthe Arduino is shown in Fig. 19.

Before discussing our specific Arduino code, we willdiscuss the Arduino programming environment and codestructure in general. The Arduino programming envi-ronment is very similar to C and C++, but with manyunique built-in functions. The primary purpose of the Ar-duino is to repeatedly execute the code within the mainloop, called with void loop(), while the Arduino ispowered on. Of course, as with any other programmingenvironment, some initialization steps must be taken. Thevery first lines of code are the variable declaration andinitialization commands.

Immediately following the variable declarations isthe setup routine, called with void setup(). Manyimportant actions are performed inside this function.For example, the programmer may specify which ofthe digital pins on the Arduino will be used as digitalinputs (reading digital signals) and which will be digitaloutputs (producing digital signals). Similarly, the analogpins can be declared as analog inputs (reading analogsignals through and ADC) or analog outputs (producingpulse-width modulated analog signals). Also, the com-munication settings on the Arduino are declared in thesetup function, such as initializing a serial connectionand specifying its baud rate.

A useful feature of the Arduino are its “interrupt”pins. These pins may function as regular digital pins,or as interrupts, which are given special priority in theArduino’s processing. To function as an interrupt, theinterrupt pin must be configured to detect a certain signalfeature, such as a low to high transition (using RISING),a high to low transition (using FALLING), or eithertransition (using CHANGE). The interrupts may also beconfigured to detect when the signal is either high or lowusing HIGH or LOW, respectively. When the specifiedfeature is detected, the Arduino immediately abandonswhatever processing it was running, and executes theinterrupt’s designated function. Once the interrupt taskis completed, the Arduino returns to the main loop. Notethat the interrupts are given numbers (typically 0 and 1)which may differ from the digital pins on which they areenabled (typically 2 and 3, respectively).

Digital pin D13 is unique in that it is connected toan LED on the Arduino’s circuit board in addition tofunctioning as a regular digital pin. This makes pin D13especially useful for debugging, as visual feedback can

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READ BYTE

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Fig. 3. Block diagram of Arduino code. Boxes with dashed linesindicate independent functions within the code.

be given the user immediately. Once the Arduino codehas been compiled, it must be uploaded to the devicevia USB. All subsequent communication between theArduino and the PC (such as data being sent to the serialport) also takes place across the USB.

We will now discuss the control code we have imple-mented in the Arduino. The pseudocode version of thecode is given in Alg. 1 and the actual code is reproducedin Fig. 9 in the Appendix. Line numbers given in thissection refer to the pseudocode in Alg. 1. Also, Fig. 3depicts the structure of the Arduino code as a blockdiagram.

Algorithm 1 Arduino Control Code1: loop2: Read inputs D5 through D123: Compile data into byte4: Send byte across the serial line5: end loop6: interrupt (D3: low → high)7: Set D13 = high8: end interrupt9: interrupt (D2: low → high)

10: if D13 == high then11: Set D13 = low12: end if13: end interrupt

For capturing data with the Arduino, we have 8 digitalpins, D5 through D12, configured as digital inputs. Theprimary loop of the Arduino begins by reading thesignals at those digital inputs (line 2). The Arduino thencompiles those 8 bits of data into a single byte (line3) which is sent over the serial line to the PC (line 4).This data can then be viewed using LabView, as we willdiscuss in Sec. II-H.

We have two digital pins, D2 and D3, which areconfigured as digital inputs and are used as interrupts.Both interrupts are set to monitor their respective inputsfor a rising edge, i.e. a low to high transition (lines

6 and 9). We also have the D13 digital pin configureas a digital output. The write sweep push button isconnected to D3, so when the user presses the button,the Arduino immediately executes the function specifiedas the interrupt response. In our case, the function thatwe execute sets the D13 pin to high (line 7), which, asdiscussed in Sec. II-E, enables the SRAM control logicso that data may be written to memory. Also from Sec.II-E, the Q9 output of the counter is sent to D2, so whenthe last address is reached by the counter and Q9 goeshigh, the second interrupt function is executed. In ourcase, the function begins by checking the state of D13(line 10) and, if D13 is currently high, the function setsit to be low8 (line 11). When D13 returns low, data mayno longer be written to memory.

We note that, regardless of the interrupt functions, theArduino is always streaming the data from the outputsof the SRAM to the PC. This means that even when datais no longer being written to memory, the Arduino willcontinue to stream the same waveform to the PC, sincethe counter will continue to cycle through addresses andthe SRAM will be locked in read mode until the userpresses the write sweep push button.

To summarize, the Arduino has two interrupt pins,D2 and D3, which monitor the Q9 output of the 12-bitcounter and the write sweep push button, respectively,for rising edges. The output D13 sends a control signalto the SRAM’s control logic to indicate that data may bewritten to the SRAM. Also, the data pins on the SRAMare connected to 8 digital inputs on the Arduino, D5through D12, so that the Arduino may send that data tothe PC. The write sweep push button essentially startsa chain reaction of events to facilitate the writing of asingle sweep of the input signal to memory. First, the12-bit counter is cleared, so that the SRAM will beginwriting at the very first address. Simultaneously, the D13output of the Arduino is set high, so that the SRAM’scontrol logic may allow data to be sent through thebuffers and written to memory. When the user releasesthe push button, the counter begins to count and theADC begins filling the memory. Exactly 256 samplingfrequency clock periods after the push button is released,Q9 goes high and the D13 output is set low, so that datamay no longer be written to memory.

G. Analog Display

The digital to analog converters (DACs) that we useallow us to view the sweep of the input signal that isbeing written to, or already stored in the SRAM on an

8Without that “if” statement, the Arduino would waste processingtime by setting the D13 pin low when it is already low.

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analog display. As mentioned previously, we have twoDACs, one which converts the addresses being sent tothe SRAM to create a sawtooth wave, while the otherconverts the data saved in memory at those addresses.The schematic for the wiring of the two DACs is shownin Fig. 20 in the Appendix, and the circuit design canbe found in the “Typical Application” section of thedatasheet9 with power and reference voltages changedfrom ±10 V to ±5 V. Note that each of our DACsare wired in the exact same configuration, with the onlydifferences being the data bits coming in, and thereforethe analog signals coming out.

The DAC receives 8 bits of data and determines, inapproximately 100 ns, the appropriate output relative toits reference voltages. In our case, we give the DACreferences to +5 V and ground (inputs VR+ and VR−,respectively), and the DAC assumes symmetry about theground reference. Thus the DAC produces −5 V whenall inputs are low, and +5 V when all inputs are high.Strictly speaking, the DAC operates using a referencecurrent, and drawing relative amounts of current fromthe outputs. For example, the +5 V reference voltageis connected to the DAC through a 5.1 kΩ resistor.This corresponds to a reference current of ∼ 1 mAflowing into the DAC from VR+. Also, the outputs ofthe DAC are connected through 10 kΩ resistors to +5 V.Therefore, when all of the data inputs are high, the DACdraws ∼ 1 mA from the IOUT output while drawing nocurrent from the IOUT output. Conversely, when all datainputs are low the DAC draws no current from the IOUT

output while drawing ∼ 1 mA from the IOUT output. Inboth cases, the current flows through a 10 kΩ resistor,yielding either a voltage drop of 10 V from 1 mA, or novoltage drop. Therefore, the voltage at the IOUT outputis exactly the digital input values mapped to an analogvoltage range of ±5 V. The voltage at the IOUT outputis the same signal but inverted (i.e. a gain of −1).

To display the outputs of the DACs, we send theconverted addresses to channel 1 of a commerciallyavailable, professionally built oscilloscope10 and we sendthe converted data to channel 2. The professional oscil-loscope has the ability to plot these two functions againsteach other, known as “X-Y mode”, which produces thesweep as a function of address. The result is exactlythe sweep of the input signal that we have captured andstored to memory being displayed on the screen of theprofessional oscilloscope. We emphasize that the purposeof using a professional oscilloscope is simply for the

9Texas Instruments DAC0800 Datasheet, June 1999, revised Febru-ary 2013.

10We used the Tektronix TDS 210.

ease of access to an LCD display. Figure 8 shows theoutput of each DAC as well as the X-Y mode output.We refer to the analog signal produced by converting theaddresses as the “T” signal, indicating that this sawtoothwave acts as our time base, and we refer to the analogsignal produced by converting the data as the “Y” signal,since it is exactly the captured waveform. We note thatour T signal exhibits some flattening near the ends of thediagonal ramp, which will be discussed in Sec. III-A.

As discussed in Sec. I-A, the professional oscillo-scope generates its own internal “sweep” to displaythe incoming signals on the screen. In its standardoperational mode, known as “Y-T mode”, each channelis plotted as an independent function of time. However,the oscilloscope triggers its internal sweep by settinga threshold on one of the channels. Hence when theincoming signal crosses the trigger threshold, the signalis swept across the screen. An oscillating signal maycross the threshold many times, and thus if we have arepeating portion of a signal which does not match upexactly at the start and end of the sweep, the result onthe screen is the same signal being overlaid many times,but starting at different points in the sweep. In our case,the signal being sent to the professional oscilloscope isexactly a repeating portion of the input signal, since weare reading through the SRAM continuously. Of course,our sweep of the input signal need not match up at thebeginning and the end, so we will have discontinuitiesin the signal. This behavior can be seen in the top panelsof Figs. 12 and 13 in the Appendix.

In X-Y mode, this is not the case. The T signalthat we are providing is used as the sweep for thedisplay, meaning a negative voltage (e.g. −5 V) wouldcorrespond to the left half of the time axis, while apositive voltage (e.g. +5 V) would correspond to theright half of the time axis. Essentially, the voltage of theT signal maps directly to the horizontal position of thesignal seen on the screen. Simultaneously, the voltage ofthe Y signal directly controls the vertical position of thesignal on the screen.

To summarize, the DACs take as inputs the 8-bitaddress used for the SRAM and the 8-bit values storedat those addresses, and produce two analog signals, Tand Y, respectively. The T signal is simply a sawtoothwave corresponding to a linear progression through allof the addresses. The Y signal is exactly the portion ofthe input signal we have stored in memory.

H. LabView

Once the byte of data has been sent from the Arduinoto the PC via USB, we display the data using National

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Instruments’ LabView program. The overall goal of theprogram is to plot the data on a graph in real-time. Todo this, we use the Arduino as a serial device (see Sec.II-F) which communicates through a COM port on thePC. We refer the interested reader to other referenceson serial port devices and communication for a moredetailed explanation on their operation and functionality.LabView monitors the COM port for data, and convertsthe bytes it receives to decimal, to be plotted as afunction of time.

The two main components of all LabView programsare the block diagram and the front panel. The blockdiagram is essentially the programming environment forLabView, where the program’s instructions are defined.The front panel is essentially the graphical user interface(GUI) that is displayed while the program is running.Many blocks in the block diagram correspond exactly toelements on the front panel, which the user may interactwith.

Fig. 10 in the Appendix shows the block diagram forour LabView program and the front panel. The blockson the left side of the block diagram (external to thethick black box) are responsible for retrieving the datafrom the serial port and passing it elsewhere in theprogram. The pink, left most block titled “Serial PortSettings” corresponds to a selection of drop-down boxeson the front panel, where the user may specify theserial port settings. The information is passed from theserial port settings block and separated by the yellowblock to its immediate right. This block passes theserial port settings to a LabView VISA11 block whichcommunicates directly with the COM port, using the portsettings specified by the previous blocks.

The VISA passes the bytes of data arriving at the serialport and passes them to the instrument block (denoted“Instr”) inside the outer of the two black boxes. Theouter of the two black boxes is a programming loop,while the inner of the two is a case structure. The loopruns continuously while the program is running, andthe case structure checks a condition in order for itscontents to be evaluated. Our case structure is checkingto see if the number of bytes at the serial port is greaterthan zero. If the number of bytes at the serial port isgreater than zero, three events are triggered. First, thebytes of data are converted to ASCII characters, andsent to the block titled “RAW ASCII”. These ASCIIcharacters are displayed on the front panel when theprogram is running. We note that since we are sendingbytes of data that correspond to a waveform, the ASCII

11Visit the National Instruments website for more information onVISA structures.

characters are essentially meaningless. However, the userwill be able to see the characters change if data is indeedflowing to the serial port. Simultaneously, the bytes ofdata are converted to decimal and sent to “WaveformChart”, which displays the real time values of the data onthe front panel. The “Waveform Chart” block is locatedoutside of the case structure so that chart will continueplotting, even if no new data is arriving at the port.Finally, the number of bytes at the port are plotted on“Waveform Chart 2”, thereby displaying the real timedata rate through the serial port. This chart is also shownon the front panel. The loop also has an “Iterations”counter, which, like the RAW ASCII block, serves asa debugging tool, since the counter will continuouslyincrease if the loop is running. The pseudocode for thisLabView program is given in Alg. 2.

Algorithm 2 LabView Code1: loop2: if Bytes at Port > 0 then3: Convert data to ASCII and decimal4: Display ASCII data5: Plot data rate6: end if7: Plot decimal data8: Increment counter9: end loop

To summarize, LabView receives a stream of bytesof data from the Arduino via the USB COM port anddisplays the decimal equivalents of that data on a graphin real-time. LabView also displays its incoming data rateas a function of time. The user may adjust the serial portsettings in LabView to match those set by the Arduino.

III. RESULTS

In this section we present collected data from ouroscilloscope and measurements of the oscilloscope’sperformance. The first set of measurements discussedin Sec. III-A were collected using a professional benchtop oscilloscope, captured with Tektronix’s WaveStarprogram, exported as .csv files and plotted in MATLAB.These signals were measured at the output of the sampleand hold circuit, prior to digital conversion, and areintended to illustrate the capabilities and limitations ofour oscilloscope. Thus, we have assumed that the analogto digital conversions will be completed accurately andthat the resulting digital values will be stored to memorywithout errors. Unless otherwise stated, the input signalto the oscilloscope was a sine wave with frequency 72Hz.

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Fig. 4. Variable DC offset capabilities of the oscilloscope. The bluedotted line is the input signal, the solid lines correspond to an offsetof −5 V (red line), 0 V (blue line) and +5 V (green line). Theinversion of the signal is due to the measurement location and is notpresent in the final signal produced by the input stage.

To demonstrate the end-to-end oscilloscope perfor-mance, we obtained oscilloscope captures with LabViewvia the Arduino along with the outputs of the DACsviewed on the professional oscilloscope for comparison.The LabView data is presented in Sec. III-B. Please notethat many of the larger figures have been placed in theAppendix consolidate the bulk of the text.

A. Measured Performance and Limitations

Our oscilloscope has adjustable gain and offset asdiscussed in Sec. II-A. The output of the summingamplifier is shown for three different offset values (−5V, 0 V and +5 V) in Fig. 4. These signals were obtainedprior to the variable gain linear amplifier, so the signalis inverted relative to the input signal. This also meansthat an offset of +5 V shifts the signal down to −5 V,and vice-versa. This inversion is of course corrected bythe variable gain amplifier as discussed before. Figure4 displays the maximum (+5 V) and minimum (−5 V)range of the offset circuit. The noise added to the signalfrom the offset circuit is minimal (< 1%).

Fig. 5 shows the output of the linear amplifier forseveral different gain settings compared to the inputsignal (shown in the top panel of Fig. 5). The oscillo-scope is capable of applying a 20× gain (second panel)to the input signal, but unless the signal has a verysmall amplitude (∼ 0.25 V), this amount of amplificationwill lead to clipping in the sample and hold circuit(see Sec. II-C). The third panel displays the maximum

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Full gain with clipping (~20x)

Full gain without op-amp clipping (20V pk-to-pk)

Full gain without sample and hold clipping (10V pk-to-pk)

Fig. 5. Variable gain capabilities of the oscilloscope. The inputsignal is shown on the top panel. Panels two through six show thesignal with various gain settings in decreasing order. The gain settingis given on the left side of each panel.

gain the op-amp can tolerate without clipping the signalitself (i.e. within ±12 V). The forth panel shows themaximum gain without clipping from any componentsin the oscilloscope (i.e. within ±5 V). The fifth paneldisplays the signal with unity gain (0 dB), the sixth with0.5× gain (−6 dB) and the sixth with zero gain (−∞dB). The noise in the zero gain data has a standarddeviations of σG = 0.1 V. As this noise is constantamplitude noise, this results in a signal-to-noise ratio(SNR) of ∼ 30 dB for a 10 V peak-to-peak signal.

As discussed in Sec. II-B, the oscilloscope is capableof sampling the input signal at four different frequencies.Figure 6 shows the same signal sampled at each of thefour different sampling frequencies (150 Hz, 1.2 kHz,2.4 kHz and 9.6 kHz) compared to the original inputsignal, shown in the top panel. Note that the sampleand hold circuit produces an apparent delay equal to thehold time. This is due to the fact that the output of thesample and hold is exactly equal to the input signal onlyfor the very brief window of time when the circuit is“sampling” the signal (see discussion in Sec. II-C). Ifthe sampling frequency is less than twice the frequency

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Fig. 6. The output of the sample and hold circuit at various samplingfrequencies for the same input signal. The top panel shows inputsignal, while the remaining panels show sampled signals from lowestto highest sampling frequency.

of the input signal, aliasing will occur. We note that the150 Hz sampling frequency shown in the second panelof Fig. 6 is close to the Nyquist rate of ∼ 144 Hz forthe input signal.

To obtain the frequency response of the analog portionof the oscilloscope, we send sine waves of variousfrequencies into the system and then measure the peak-to-peak voltage of the signal at the output of the sampleand hold circuit. This data set was collected at a samplingfrequency of 2.4 kHz. Figure 7 shows the peak-to-peakvoltage (normalized) as a function of frequency. Our os-cilloscope begins attenuating the signal at approximately5 kHz and the amplitude continues to decay as the signalfrequency increases. The “cutoff frequency” of a systemoccurs when the signal is attenuated by −3 dB, which,for our oscilloscope, is at approximately 16 kHz. Thisattenuation is due to the capacitor in the sample and holdcircuit (see Fig. 16). The amplitude falloff is consistentwith that of a low pass filter, as discussed in Sec. II-C.

Fig. 8 shows the output from the sample and hold (toppanel) compared with the output of the DACs (bottomtwo panels). Recall that the signal from the sample andhold circuit is converted to digital and then back toanalog. It is this signal which has been reverted to analogthat is shown in Fig. 8 in the center panel (green line).The address signal that counts up while the input signalis recorded is also converted to analog (center panel,blue line). Plotting the blue line (T signal) against thegreen line (Y signal) gives the analog output of ouroscilloscope (bottom panel, red line). As discussed inSec. II-G, the bottom panel is the X-Y mode output.

101 102 103 104 105−6

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Fig. 7. The oscilloscope’s frequency response (peak-to-peak voltageas a function of frequency), measured with a sine wave at frequenciesranging from 20 Hz up to 21 kHz. Sampling frequency is 2.4 kHz.Signal attenuation of −3 dB occurs at ∼ 16 kHz.

Clearly, this output in good agreement with the sampleand hold output signal. Although it is not shown here,Figs. 12 and 13 in the Appendix show the T signalflattening near the start and end of the linear ramp.We are unsure of the source of this flattening, but wehave noticed a similar clipping pattern on other devicesregardless of power supply voltage. The flattening causesthe ends of the sweep of the input signal stored inmemory to be “squished” in X-Y mode, since the Ysignal is changing while the T signal is essentiallyconstant.

The timing diagram shown in Fig. 11 in the Appendixis the measured version of the simulated timing diagramshown previously in Fig. 2 and discussed in Sec. II-B.The timing signals in this diagram correlate well tothe modeled version. One noticeable difference in thenoise present in the signal with a standard deviation ofapproximately 0.06 V or ∼ 1% of the 5 V digital signal.This noise level corresponds to a 35 dB SNR for a 5 Vdigital signal.

B. Measurements with LabView

Prior to this point, the data shown in this section werecaptured using the professional oscilloscope and replot-ted with MATLAB. Here we discuss data captured withLabView via the Arduino which is the end product ofour oscilloscope. Capturing data with LabView is a threestep process described in Sec. II-E, II-F and II-H. Figure12 in the Appendix shows the LabView capture witha sampling frequency of 1200 Hz. The bottom plot is

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Student Version of MATLAB

Fig. 8. The outputs of the DACs. The top panel shows the sampleand hold output signal. The center panel shows the time output fromthe DAC (T signal) and the data output from the DAC (Y signal).The bottom panel shows the T and Y signals plotted against eachother on the X and Y axes, respectively.

taken from LabView while the top plot was captured withthe bench top oscilloscope for comparison. LabViewrepeatedly plots the same data stored in memory untilthe user writes new data to the memory. Approximatelytwo sweeps through the memory are shown in Fig. 12.A discontinuity is visible when the signal repeats (thisoccurs twice in the figure) indicating that the input signalwas at different points in its period at the beginning ofthe sweep and at the end. The top plot shows the Tsignal counting up (blue line) and the Y signal (greenline) being produced by the DACs. Note that time onthe X axis in LabView is in milliseconds. The durationof one sweep of the data is approximately 213 ms(256 periods/1200 Hz) for this case. The amplitude ofthe sampled signal can be at maximum ±5 V whichwould correspond to a minimum of 0 counts (−5 V)or a maximum of 255 counts (+5 V) on the Y axis(labeled amplitude) of the LabView plot. In our case,the sampled signal has a max/min of roughly of ±2 Vwhich corresponds to an amplitude between 80 and 180counts in LabView, which is what we observe. Thus, touse the LabView display as an oscilloscope, one simplyreads the X axis as time in milliseconds and the Y axiscan be converted to a voltage by subtracting 128 fromthe amplitude and multiplying the resulting value by the

ratio 5 V/128 counts.Fig. 13, also in the Appendix, shows a second wave-

form captured in LabView, now with a sampling rate of9600 Hz. In both of these LabView measurements, thefrequency of the input signal was ∼ 65 Hz. Notice thatthe higher sampling rate makes the discretization fromthe sample and hold circuit less noticeable. However,the consequence of higher temporal resolution is thatfewer oscillations are captured to memory for a giveninput signal frequency, as the size of the memory isfixed. In this case, only slightly more than one periodof the input signal is captured and stored to memory.At a sample rate of 9600 Hz, approximately 27 ms(256 periods/9600 Hz) of the signal is captured.

IV. CONCLUSIONS AND LESSONS LEARNED

In this report we discussed the construction, perfor-mance, and operation of our homemade digital samplingoscilloscope. Our final product was a fully operationaloscilloscope that allowed the user to adjust the gain andoffset of an input signal, sample the signal at one offour possible sampling frequencies, convert the signalto digital and write the data to memory to retrieve anddisplay it in LabView via the Arduino. Our oscilloscopecan capture waveforms with a SNR of 30 dB for fre-quencies up to ∼ 16 kHz with ≤ −3 dB amplitudeattenuation and up to 4.8 kHz without aliasing. At thehighest sampling frequency (9.6 kHz), the memory canhold ∼ 27 ms worth of data, while the lowest samplingfrequency (150 Hz) allows 1.7 seconds worth of datato be stored in memory. We believe that this samplingfrequency flexibility gives this oscilloscope a uniqueability to sample waveforms of various frequencies atthe required fidelity.

There were several lessons learned looking back at theproject. During the oscilloscope construction, we ran intoa couple of technical hitches. For instance, the occasionalconnection was omitted while wiring up analog compo-nents. The lesson learned here is that if a component isnot operating properly it is most likely due to humanerror (such as a missing wire or insufficient power),and not a broken component, although the latter mightbe the instinctive first guess. There is certainly an artto troubleshooting and isolating problems to individualcomponents and eventually finding the problematic (ormissing) connection. By the completion of our projectwe had come to appreciate the importance of colorcoding our wires to ease troubleshooting and visualcomprehension of our circuit board. We also learnedthat it is essential to have a big picture understanding ofhow all the components will integrate and work togetherwhile still in the planning phase of the circuit. Initially,

16

we considered each component (e.g. the sample and holdcircuit) as an individual module, and began building theoscilloscope by completing one module and then movingon to the next. We soon learned that if we did notplan ahead and take into account the interaction betweenvarious modules, we would often have to rebuild orrearrange components.

APPENDIX

TABLE IVINTEGRATED CIRCUIT COMPONENTS

Component Quantity Part #Arduino Nano 1 ATmega328Op-Amp (package of 2) 3 UA747CNBilateral Switch (package of 4) 1 TC4066BPNAND Gate (package of 4) 1 SN7400NNOT Gate (package of 6) 1 SN7404NAND Gate (package of 4) 1 SN74LS08NDigital Buffer (package of 8) 1 SN74LS244ND-Type Flip-Flop (package of 4) 2 SN74S175NAnalog to Digital Converter 1 ADC0800PCDDigital to Analog Converter 2 DAC0800LCN4-Bit Counter 1 SN74LS163AN12-Bit Counter 1 CD4040BEStatic RAM 1 HM6116PBit Rate Generator 1 MC14411

TABLE VDISCRETE COMPONENTS

Component Quantity ValueResistor 1 470 ΩResistor 4 5.1 kΩResistor 7 10 kΩResistor 1 15 MΩVariable Resistor 1 10 kΩPotentiometer 1 100 kΩCapacitor 2 10 nFCapacitor 1 68 nFCapacitor 4 100 nFCrystal 1 1.8432 MHzPush Button Switch 1 –SPDT Switch 2 –

17

Fig. 9. The Arduino control code.

18

Fig.

10.

Top:

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ckdi

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Measured Timing Diagram

0 50 100 150 200 250Time (microseconds)

Student Version of MATLAB

ADC clock (48x)

Q_1 (1x)

QA

QC

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Q_2

Q_1 * ~Q_2

S/H CTRL

ADC Start

ADC EOC

Fig. 11. Measured timing diagram. Shows the measured timing pulses used to control the Sample and Hold circuit and to start the ADCconversion. The timing diagram and the modeled timing signals are discussed in Sec. II-B.

20

Lab View Capture

signal repeats

0 25 50 75 100 125 150 175 200 225 250−5−4−3−2−1

012345

Oscilloscope Capture with 1200Hz Sampling Frequency

Time (milliseconds)

Volta

ge (V

)

T signal (time signal)Y signal (data signal)

Student Version of MATLAB

Fig. 12. Oscilloscope data taken with LabView via the Arduino (bottom) compared with data measured after analog conversion via thebench top oscilloscope. Sampling rate: 1200Hz.

21

signal repeats

Lab View Capture

0 5 10 15 20 25 30 35 40−5−4−3−2−1

012345

Oscilloscope Capture 9600Hz Sampling Frequency

Time (milliseconds)

Volta

ge (V

)

T signal (time signal)Y signal (data signal)

Student Version of MATLAB

Fig. 13. Oscilloscope data taken with LabView via the Arduino (bottom) compared with data measured after analog conversion via thebench top oscilloscope. Sampling rate: 9600Hz.

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