Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister...
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Transcript of Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister...
![Page 1: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/1.jpg)
Digital Logic
![Page 2: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/2.jpg)
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Abstractions in CS (gates)
• Basic Gate: Inverter
I O01
10
I O
GND I O
Vcc
Resister (limits conductivity)
Truth Table
![Page 3: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/3.jpg)
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Abstractions in CS (gates)
I O01
10
I OTruth Table
![Page 4: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/4.jpg)
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Abstractions in CS (gates)
• Basic Gate: NAND (Negated AND)
A B0011
0101
1110
Y AB
Y
GND A B Y
Vcc
Truth Table
![Page 5: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/5.jpg)
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Abstractions in CS (gates)
• Basic Gate: AND
A B0011
0101
0001
Y
AB Y
Truth Table
![Page 6: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/6.jpg)
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Abstractions in CS (gates)
• Other Basic Gates: OR gate
A B0011
0101
0111
Y
AB Y
Truth Table
![Page 7: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/7.jpg)
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Abstractions in CS (gates)
• Other Basic Gates: XOR gate
A B0011
0101
0110
Y
AB Y
Truth Table
![Page 8: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/8.jpg)
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Logic Blocks
• Logic blocks are built from gates that implement basic logic functions– Any logical function can be constructed using AND
gates, OR gates, and inversion.
![Page 9: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/9.jpg)
Adder
• In computers, the most common task is add.• In MIPS, we write “add $t0, $t1, $t2.”
The hardware will get the values of $t1 and $t2, feed them to an adder, and store the result back to $t0.
• So how the adder is implemented?
![Page 10: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/10.jpg)
Half-adder
• How to implement a half-adder with logic gates?
• A half adder takes two inputs, a and b, and generates two outputs, sum and carry. The inputs and outputs are all one-bit values.
a
b carry
sum
![Page 11: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/11.jpg)
Half-adder
• First, how many possible combinations of inputs?
![Page 12: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/12.jpg)
Half-adder
• Four combinations.
a b sum carry
0 0
0 1
1 0
1 1
![Page 13: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/13.jpg)
Half-adder
• The value of sum should be? Carry?a b sum carry
0 0
0 1
1 0
1 1
![Page 14: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/14.jpg)
Half-adder
• Okay. We have two outputs. But let’s implement them one by one.
• First, how to get sum? Hint: look at the truth table.
a b sum0 0 00 1 11 0 11 1 0
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Half-adder
• Sum
ab
sum
![Page 16: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/16.jpg)
How about carry?
• The truth table is
a b carry0 0 00 1 01 0 01 1 1
![Page 17: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/17.jpg)
Carry
• So, the circuit for carry is
ab
carry
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Half-adder
• Put them together, we get
ab
sum
carry
![Page 19: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/19.jpg)
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1-Bit Adder• 1-bit full adder– Also called a (3, 2) adder
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Constructing Truth Table for 1-Bit Adder
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Truth Table for a 1-Bit Adder
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Sum?
• Sum is `1’ when one of the following four cases is true:– a=1, b=0, c=0– a=0, b=1, c=0– a=0, b=0, c=1– a=1, b=1, c=1
![Page 23: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/23.jpg)
Sum• The idea is that we will build a circuit made of and gates and or gate
faithfully according to the truth table.– Each and gate corresponds to one ``true’’ row in the truth table. The
and gate should output a ```1’’ if and only if the input combination is the same as this row. If all other cases, the output is ``0.’’
– So, whenever the input combination falls in one of the ``true’’ rows, one of the and gates is ``1’’, so the output of the or gate is 1.
– If the input combination does not fall into any of the ``true’’ rows, none of the and gates will output a ``1’’, so the output of the or gate is 0.
![Page 24: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/24.jpg)
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Boolean Algebra
• We express logic functions using logic equations using Boolean algebra– The OR operator is written as +, as in A + B.– The AND operator is written as ·, as A · B.– The unary operator NOT is written as . or A’.
• Remember: This is not the binary field. Here 0+0=0, 0+1=1+0=1, 1+1=1.
![Page 25: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/25.jpg)
Sum
![Page 26: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/26.jpg)
Carryout bit?
• Carryout bit is ‘1’ also on four cases. When a, b and carryin are 110, 101, 011, 111.
• Does it mean that we need a similar circuit as sum?
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Carryout bit
• Actually, it can be simpler
![Page 28: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/28.jpg)
Delay
• Hardware has delays.• Delay is defined as the time since the input is
stable to the time when the output is stable.• How much delay do you think the one-bit half
adder is and the one-bit full adder is?
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1-Bit Adder
![Page 30: Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO 0101 1010 IO GNDI O Vcc Resister (limits conductivity) Truth Table.](https://reader030.fdocuments.in/reader030/viewer/2022032722/56649f495503460f94c6aad4/html5/thumbnails/30.jpg)
32-bit adder
• How to get the 32-bit adder used in MIPS?
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32-bit adder