Digital Integrated Circuitsesc.inu.ac.kr/~kcm/epc6055/Lab1.pdfSimulation Tool ModelSim PE 10.4a...
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Jaeyong Chung SoC Laboratory Incheon National University Digital Integrated Circuits Lab1
Transcript of Digital Integrated Circuitsesc.inu.ac.kr/~kcm/epc6055/Lab1.pdfSimulation Tool ModelSim PE 10.4a...
Jaeyong Chung
SoC Laboratory
Incheon National University
Digital Integrated Circuits
Lab1
Contents
Toolchain Installation
Modelsim
Download
Installation
License
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Simulation Tool
ModelSim PE 10.4a
ModelSim is an HDL Verification Tool
Developed by Mentor Graphics, an
EDA Tool Expert Company.
Both VHDL and Verilog Descriptions
can be Simulated.
ModelSim can Simulate Designs which
are Described in Mixed Languages (V
HDL, Verilog, and SystemC).
A Free Version can be Downloaded
from http://www.model.com
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Install program
Install modelsim-pe_student_edition
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Fill out the form and click the Request License button
Download License File
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Download License File
License file is attached to email.
Download license file.
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Download directory
C:\Modeltech_pe_edu_10.4a
Download License File
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Contents
Toolchain Installation
Modelsim
Download
Installation
License
Simulation
Half Adder
Full Adder
4 bit Adder
4 bit Adder/Subtractor
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Create New Project
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Create a new project
EPC6055
Create New Project
Click the “Create New File” icon.
File Name
halfAdder.v
Add file as type
Verilog
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Half adder
Create Verilog File
x y 0
0 0 1 1 1 0 1 0 1 0 1 1 0 c s 0 0
carry sum
Carry Sum
x y c s
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
x
y s
c
x
y
s
c HA
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Select the “halfAdder.v” file.
Enter the code into the source window.
Create Verilog File
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Create Test Bench File
Project -> Add to Project -> New File
Filename
halfAdderTb.v
Add file as type
Verilog
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Test bench source
Create Test Bench File
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Compile Project
Click the “Compile All” button.
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Start Simulation
Simulation -> Start Simulation
Select halfAdderTb
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Start Simulation
Wave window
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Start Simulation
Select all objects.
Right click and select Add Wave.
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Start Simulation
Objects are added to wave window.
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Start Simulation
Enter run into command line
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Start Simulation
Simulation result
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Full Adder
Full Adder
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Module code
Full Adder
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Test bench
Full Adder
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Simulation result
Full Adder
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4 bit Adder
4 Bit Adder
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4 Bit Adder
Hierachy structure
fourBitAdder0 (4 bit Adder)
bit3
(Full Adder)
halfAdder2 (Half Adder)
halfAdder1 (Half Adder)
halfAdder2 (Half Adder)
halfAdder1 (Half Adder)
halfAdder2 (Half Adder)
halfAdder1 (Half Adder)
halfAdder2 (Half Adder)
halfAdder1 (Half Adder)
27
bit2
(Full Adder)
bit1
(Full Adder)
bit0
(Full Adder)
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4 Bit Adder
Hierachy structure
fourBitAdder0 (4 bit Adder)
halfAdder1 (Half Adder)
bit3
(Full Adder)
halfAdder1 (Half Adder)
halfAdder2 (Half Adder)
halfAdder1 (Half Adder)
bit2
(Full Adder)
halfAdder1 (Half Adder)
halfAdder2 (Half Adder)
halfAdder1 (Half Adder)
bit1
(Full Adder)
halfAdder1 (Half Adder)
halfAdder2 (Half Adder)
halfAdder1 (Half Adder)
bit0
(Full Adder)
halfAdder1 (Half Adder)
halfAdder2 (Half Adder)
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4 Bit Adder
Module code
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Test bench
4 Bit Adder
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4 Bit Adder
Simulation result
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4 bit Adder/Subtractor
4 Bit Adder/Subtractor
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Module code
4 Bit Adder/Subtractor
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Test bench
4 Bit Adder/Subtractor
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Simulation result
4 Bit Adder/Subtractor
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Homework
Put correct operators in each blank, and complete a 4
bit Adder/Subtractor.
Verify it through simulation.
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