Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

The InverterThe Inverter

IntroductionIntroduction

q The inverter is the simplest of all digital logic gates

q However, building an understanding of its properties and operation is crucial for the design and analysis of larger/ more complex logic gates.

q We will discuss: General properties of an inverter (and logic gates), and inverter implementation issues in CMOS technology.

General PropertiesGeneral Properties

q Small area is a desirable property for a digital logic gateq Larger packing densityq Small parasitic capacitancesq Shorter interconnectsq Smaller chip area, hence higher number of devices per wafer (lower

cost)

q Fewer transistors for a logic gate usually results into smaller area.Hence, minimum possible number of transistors for a given gate is important.

The CMOS Inverter: A First GlanceThe CMOS Inverter: A First Glance

V in Vout

CL

VDD

CMOS Inverter CMOS Inverter -- FirstFirst--Order DC AnalysisOrder DC Analysis

VOL = 0VOH = VDD

VM = f(Rn, Rp)

VDD VDD

Vin = VDD Vin = 0

VoutVout

Rn

Rp

Properties1) High and low outputs = VDD and Ground.

Voltage swing= VDD. High Noise Margins.2) Logic Levels are independent of device sizes

(ratioless logic)3) In steady state, a path exists from O/P to VDD

or GND. Thus, low output impedance. Less sensitive to noise.

4) Input resistance is extremly high, since MOS gate draws no dc input current. Steady-state input current ~ zero. An inverter can theoretically drive infinite number of gates and be functionally operational. This degrades the transient response.

5) In steady-state, no direct path exists between supply and ground rails. No static power (ignoring leakage)

Voltage TransferVoltage TransferCharacteristicCharacteristic

PMOS Load LinesPMOS Load Lines

VDSp

IDp

VGSp=-2.5

VGSp=-1VDSp

IDnVin=0

Vin=1.5

Vout

IDnVin=0

Vin=1.5

Vin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

DDoutDSpoutDSn

DDinGSpinGSn

DSnDSp

VVVVV

VVVVV

II

−==

−==

−=

;

;

CMOS Inverter Load CharacteristicsCMOS Inverter Load CharacteristicsID n

Vout

Vin = 2.5

Vin = 2

Vin = 1.5

Vin = 0

Vin = 0.5

Vin = 1

NMOS

Vin = 0

Vin = 0.5

Vin = 1Vin

= 1.5

Vin = 2

Vin = 2.5

Vin = 1Vin

= 1.5

PMOS

For a dc operating point to be valid, the currents through NMOS and PMOS devices must be equal (intersections) {Vin = 0, 0.5, 1, 1.5, 2, 2.5}

Operating points are located either at the high or low output levels. The Voltage Transfer Characteristics (VTC) exhibit a very narrow transition zone (high gain during switching transient – a small change in the input voltage results in a large output variation)

CMOS Inverter VTCCMOS Inverter VTC (V(VDDDD=2.5V)=2.5V)

Vout

Vin0.5 1 1.5 2 2.5

0.5

11.

52

2.5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS satPMOS res

NMOS resPMOS sat

Vout=Vin

VM = switching threshold

Switching Threshold as a function of Transistor RatioSwitching Threshold as a function of Transistor Ratio

100 1010.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

MV(V

)

Wp/Wn

Vin=VoutPMOS and NMOS are saturated since VDS=VGS. Equate current through NMOS and PMOS.

rrV

V DDM +

≈1

VM=VDD/2 for comparable high and low noise margins. Thus, r=1.

)/()()/()/( ''pDSATpnDSATnnp kVkVLWLW =

Increasing strength of NMOS (sizing it up), moves VM closer to GND. Vice versa for PMOS case.Note: When designing CMOS circuits, it is advisable to balance the strengths of the transistors by making PMOS wider than NMOS, to obtain large noise margins + symmetrical characteristics.

Switching Threshold as a function of Transistor RatioSwitching Threshold as a function of Transistor Ratio

Points

q VM is relatively insensitive to variations in the device ratio. Small variations of the ratio do not disturb the VTC that much. Setting ratio of Wp/Wn to {3, 2.5, 2} yields switching thresholds of {1.22V, 1.18V, 1.13V}

q VM shifts towards VDD or GND depending on strength of NMOS and PMOS. Asymmetrical VTC is sometimes desirable in some designs.Example in Page 187.

Noise Margin Noise Margin -- Determining VDetermining VIHIH and Vand VILIL

VOH

VOL

Vin

Vout

VM

VIL VIH

A simplified approach

In real life applications, output voltage of a gate may not have the nominal value, owing to load, high switching speed..etc.Hence, it is desirable to define an acceptable voltage range for logic “1” and logic “0”

These expressions make it clear that a high gain in the transition region is very desirable. For infinite gain: NMH=VDD-VM, NML=VM

Logic gates have the property to restore the proper output logic values despite of non-ideal input levels.

Inverter GainInverter Gain

0 0.5 1 1.5 2 2.5-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Vin (V)

gain

NMOS and PMOS are in saturation. Equate currents. Differentiate and solve for dVout/dVin

The gain is almost purely determined by technology parameters, especially the channel-length modulation.

Gain as a function of VGain as a function of VDDDD

0 0.05 0.1 0.15 0.20

0.05

0.1

0.15

0.2

Vin (V)

Vou

t (V

)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin (V)

Vou

t(V

)

Gain=-1

The gain of the inverter actually increases with a reduction of VDD . At a VDD =0.5V, which is just 100mV above VT of the transistors. So why can’t we operate all digital circuits at low VDD values?

• Yes, you get lower power consumption. But the delay of the gate drastically increases.• DC characteristics become very sensitive to variations in device parameters such at VT once VDD and intrinsic voltages become comparable.

• The signal swing is reduced. Although this is good for internal noise (crosstalk), this is bad for external noise sources that do not scale.

Impact of Process VariationsImpact of Process Variations

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin

(V)

Vou

t(V)

Good PMOSBad NMOS

Good NMOSBad PMOS

Nominal

A CMOS inverter remains functional under a wide range of operating conditions. We showed that variations in device sizes have minor impact on switching threshold.

This robust behavior, which ensures functionality of the gate over a wide range of conditions, has contributed in a big way to the popularity of the static CMOS gate.

Propagation DelayPropagation Delay

CMOS Inverter: Transient ResponseCMOS Inverter: Transient Response

tpHL = f(Ron.CL)

= 0.69 RonCL

VoutVout

R n

Rp

VDDV DD

V in = VDDV in = 0

(a) Low-to-high (b) High-to-low

CLCL