Digital IC Introduction

Digital Integrated Circuits

A Design Perspective Designing Combinational

Logic Circuits Fuyuzhuo

School of Microelectronics,SJTU � 

Digital IC Introduction EE141

2

Dynamic Logic

Digital IC 3

Dynamic logic outline � •  Dynamic logic principle � •  Dynamic logic properties � •  Dynamic logic design issues � •  Dynamic logic cascade solution � 

Digital IC 4

A first glance of dynamic logic

•  Basic components •  PDN,just like CMOS and

pseudo-NMOS � •  Clock control transistors，

seperate circuit to two phases � 

•  Dynamic logic’s two phases � •  precharge •  evaluation � 

Digital IC 5

Dynamic CMOS •  In static circuits at every point in time (except when

switching) the output is connected to either GND or VDD via a low resistance path. •  fan-in of n requires 2n (n N-type + n P-type) devices

•  Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. •  requires on n + 2 (n+1 N-type + 1 P-type) transistors

Digital IC 6

Dynamic Gate

In1

In2 PDN

In3

Me

Mp

Clk

Clk

Out CL

Out

Clk

Clk

A

B

C

Mp

Me

Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

Digital IC 7

Dynamic Gate

In1

In2 PDN

In3

Me

Mp

Clk

Clk

Out CL

Out

Clk

Clk

A

B

C

Mp

Me

Two phase operation Precharge (Clk = 0) Evaluate(Clk = 1)

on

off

1

off

on

((AB)+C)

Digital IC 8

Conditions on Output •  Once the output of a dynamic gate is discharged, it

cannot be charged again until the next precharge operation.

•  Inputs to the gate can make at most one transition during evaluation.

•  Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

Digital IC Slide 9

Dynamic Logic •  Dynamic gates uses a clocked pMOS pullup •  Two modes: precharge and evaluate

1

2A Y

4/3

2/3

AY

1

1

AY

φ

Static Pseudo-nMOS Dynamic

φ Precharge Evaluate

Y

Precharge

Digital IC Slide 10

The Foot •  What if pulldown network is ON during precharge? •  Use series evaluation transistor to prevent fight.

AY

φ

foot

precharge transistorφ

Y

inputs

φY

inputs

footed unfooted

f f

Digital IC Slide 11

Logical Effort

Inverter NAND2 NOR2

1

1

AY

2

2

1

B

AY

A B 11

1

gd =pd =

gd =pd =

gd =pd =

Yφ

φ

φ

2

1

AY

3

3

1

B

AY

A B 22

1

gd =pd =

gd =pd =

gd =pd =

Yφ

φ

φ

footed

unfooted

32 2

Digital IC Slide 12

Logical Effort

Inverter NAND2 NOR2

1

1

AY

2

2

1

B

AY

A B 11

1

gd = 1/3pd = 2/3

gd = 2/3pd = 3/3

gd = 1/3pd = 3/3

Yφ

φ

φ

2

1

AY

3

3

1

B

AY

A B 22

1

gd = 2/3pd = 3/3

gd = 3/3pd = 4/3

gd = 2/3pd = 5/3

Yφ

φ

φ

footed

unfooted

32 2

Digital IC Slide 13

Monotonicity •  Dynamic gates require monotonically rising inputs during

evaluation •  0 -> 0 •  0 -> 1 •  1 -> 1 •  But not 1 -> 0

φ Precharge Evaluate

Y

Precharge

A

Output should rise but does not

violates monotonicity during evaluation

A

φ

Digital IC Slide 14

Monotonicity Woes •  But dynamic gates produce monotonically falling outputs

during evaluation •  Illegal for one dynamic gate to drive another!

A X

φ Yφ Precharge Evaluate

X

Precharge

A = 1

Y

Digital IC Slide 15

Monotonicity Woes •  But dynamic gates produce monotonically falling outputs

during evaluation •  Illegal for one dynamic gate to drive another!

A X

φ Yφ Precharge Evaluate

X

Precharge

A = 1

Y should rise but cannot

Y

X monotonically falls during evaluation

Digital IC 16

Dynamic logic outline � •  Dynamic logic principle � •  Dynamic logic properties � •  Dynamic logic design issues � •  Dynamic logic cascade solution � 

Digital IC 17

Properties of Dynamic Gates

•  Logic function is implemented by the PDN only •  number of transistors is N + 2 (versus 2N for static complementary

CMOS)

•  Full swing outputs (VOL = GND and VOH = VDD) •  Non-ratioed

•  sizing of the devices does not affect the logic levels

•  Faster switching speeds •  reduced load capacitance due to lower input capacitance (Cin) •  reduced load capacitance due to smaller output loading (Cout)

Digital IC 18

Properties of Dynamic Gates •  Overall power dissipation usually higher than static

CMOS •  no static current path ever exists between VDD and GND

(including Psc) •  No glitching •  higher transition probabilities •  extra load on Clk

•  PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn •  low noise margin (NML)

•  Needs a precharge/evaluate clock

Digital IC 19

Dynamic logic outline � •  Dynamic logic principle � •  Dynamic logic properties � 

•  Dynamic logic design issues •  Charge-leakage •  Charge-sharing

•  Backgate Coupling

•  Clock feedthrough

•  Dynamic logic cascade solution � 

Digital IC 20

Issues in Dynamic Design 1: Charge Leakage

CL

Clk

Clk

Out

A

Mp

Me Leakage sources

CLK

VOut

Precharge

Evaluate

Dominant component is subthreshold current

Digital IC 21

Solution to Charge Leakage

CL

Clk

Clk

Me

Mp

A

B

Out

Mkp

Same approach as level restorer for pass-transistor logic

Keeper Width:min Length:L

Option!

Digital IC 22

Dynamic logic outline � •  Dynamic logic principle � •  Dynamic logic properties � 

•  Dynamic logic design issues •  Charge-leakage

•  Charge-sharing •  Backgate Coupling

•  Clock feedthrough

•  Dynamic logic cascade solution � 

Digital IC 23

Issues in Dynamic Design 2: Charge Sharing

CL

Clk

Clk

CA

CB

B=0

A

Out Mp

Me

Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

Could we move it to there?

Digital IC Slide 24

Charge Sharing •  Dynamic gates suffer from charge sharing

B = 0

AY

φ

x

Cx

CY

A

φ

x

Y

Charge sharing noise

x YV V= =

Digital IC Slide 25

Charge Sharing •  Dynamic gates suffer from charge sharing

B = 0

AY

φ

x

Cx

CY

A

φ

x

Y

Charge sharing noise

Yx Y DD

x Y

CV V VC C

= =+

Digital IC 26

Solution to Charge Redistribution

Clk

Clk

Me

Mp

A

B

Out Mkp

Clk

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

Digital IC 27

Dynamic logic outline � •  Dynamic logic principle � •  Dynamic logic properties � 

•  Dynamic logic design issues •  Charge-leakage

•  Charge-sharing

•  Backgate Coupling •  Clock feedthrough

•  Dynamic logic cascade solution � 

Digital IC 28

Issues in Dynamic Design 3: Backgate Coupling

CL1

Clk

Clk

B=0

A=0

Out1 Mp

Me

Out2

CL2 In

Dynamic NAND Static NAND

=1 =0

-1

0

1

2

3

0 2 4 6

Volta

ge

Time, ns

Clk

In

Out1

Out2

Digital IC 29

Dynamic logic outline � •  Dynamic logic principle � •  Dynamic logic properties � 

•  Dynamic logic design issues •  Charge-leakage

•  Charge-sharing

•  Backgate Coupling

•  Clock feedthrough •  Dynamic logic cascade solution � 

Digital IC 30

Issues in Dynamic Design 4: Clock Feedthrough

CL

Clk

Clk

B

A

Out Mp

Me

Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.

Digital IC 31

Clock Feedthrough

-0.5

0.5

1.5

2.5

0 0.5 1

Clk

Clk

In1

In2

In3

In4

Out

In & Clk

Out

Time, ns

Volta

ge

Clock feedthrough

Clock feedthrough

Digital IC 32

Dynamic logic outline � •  Dynamic logic principle � •  Dynamic logic properties � 

•  Dynamic logic design issues

•  Charge-leakage

•  Charge-sharing

•  Backgate Coupling

•  Clock feedthrough

•  Dynamic logic cascade solution � 

Digital IC Slide 33

Domino Gates •  Follow dynamic stage with inverting static gate

•  Dynamic / static pair is called domino gate •  Produces monotonic outputs

φ Precharge Evaluate

W

Precharge

X

Y

Z

A

φ

B C

φ φ φ

C

AB

W X Y Z =X

ZH H

A

W

φ

B C

X Y Z

domino AND

dynamicNAND

staticinverter

Digital IC 34

Designing with Domino Logic

M p

M e

V DD

PDN

Clk

In 1 In 2 In 3

Out1

Clk

M p

M e

V DD

PDN

Clk

In 4

Clk

Out2

M r

V DD

Inputs = 0 during precharge

Can be eliminated!

Digital IC 35

Footless Domino

•  The first gate in the chain needs a foot switch •  Precharge is rippling – short-circuit current •  A solution is to delay the clock for each stage

VDD

Clk MpOut1

In1

1 0

VDD

Clk MpOut2

In2

VDD

Clk MpOutn

InnIn3

1 0

0 1 0 1 0 1

1 0 1 0

Digital IC 36

np-CMOS

In1

In2 PDN

In3

Me

Mp

Clk

Clk Out1

In4 PUN

In5

Me

Mp Clk

Clk

Out2 (to PDN)

1 → 1 1 → 0

0 → 0 0 → 1

Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUN

Digital IC Slide 37

Domino Summary •  Domino logic is attractive for high-speed circuits

•  1.5 – 2x faster than static CMOS •  But many challenges:

•  Monotonicity •  Leakage •  Charge sharing •  Noise

•  Widely used in high-performance microprocessors

Digital IC

Summary •  Static CMOS gates are very robust

•  Logic effect •  Fan-in relate to the delay •  Power evalutation

•  Other circuits suffer from a variety of pitfalls •  Pseodu NMOS logic •  Pass transistor

•  cascade problem ,restorer(keeper),some pass logic

•  Dynamic logic •  Characteristic •  Cascade issue •  Domino logic •  Some pitfalls of dynamic logic

Slide 38