Digital IC Design record

7/27/2019 Digital IC Design record

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Sri Vidyaniketan Engineering College 301

Comparative Analysis of Low Power 4-bit Multipliers Using 120nm CMOS

Technology

Abstract:

Multiplication is one of the most commonly used arithmetic operations in various applications like, DSP

processor, math processor and in various scientific applications. Based on the simplifications of theaddition operations in a low power bypassing-based multiplier, a low cost, low power bypassing-based

multiplier is proposed. This paper shows the comparison between row bypassing multiplier, column

bypassing multiplier and 2-Dimensional bypassing-based multiplier.

Keywords: Multiplier, bypassing multiplier, 2- dimensional multiplier.

Braun Multiplier:

Circuit Diagram:

Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bm is

Port ( x : in STD_LOGIC_vector(3 downto 0);

y : in STD_LOGIC_vector(3 downto 0);

p : out STD_LOGIC_vector(7 downto 0));

end bm;

architecture Behavioral of bm is

component and21 is

Port ( x1 : in STD_LOGIC;

y1 : in STD_LOGIC;


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z1 : out STD_LOGIC);

end component;

component fa is


y1 : in STD_LOGIC;

z1 : in STD_LOGIC;sum, carry : out STD_LOGIC);

end component;

signal q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14,q15,c1,c2,c3,c4,

c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,s1,s2,s3,s4,s5,s6:std_logic;

begin

a1:and21 port map(x(0),y(0),p(0));

a2:and21 port map(x(1),y(0),q1);



a5:and21 port map(x(0),y(1),q4);a6:and21 port map(x(1),y(1),q5);










a16:and21 port map(x(3),y(3),q15);b1:fa port map(q1,'0',q4,p(1),c4);

b2:fa port map(q5,'0',q2,s1,c5);

b3:fa port map(q6,'0',q3,s2,c6);

b4:fa port map(q8,c4,s1,p(2),c7);

b5:fa port map(q9,c5,s2,s3,c8);

b6:fa port map(q10,c6,q7,s4,c9);

b7:fa port map(q12,c7,s3,p(3),c10);

b8:fa port map(q13,c8,s4,s5,c12);

b9:fa port map(q14,c9,q11,s6,c14);

b10:fa port map(c10,'0',s5,p(4),c11);

b11:fa port map(c11,c12,s6,p(5),c13);b12:fa port map(c13,c14,q15,p(6),p(7));

end Behavioral;

---------------------------------------------------------------------------------------------

library IEEE;





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entity fa is


y1 : in STD_LOGIC;

z1 : in STD_LOGIC;

sum, carry : out STD_LOGIC);

end fa;architecture dataflow of fa is

begin

sum


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# IBUF : 8

# OBUF : 8

=========================================================================

Timing report:

Clock Information:------------------

No clock signals found in this design

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 10.574ns

Timing Detail:

All values displayed in nanoseconds (ns)

=========================================================================

Timing constraint: Default path analysis

Total number of paths / destination ports: 330 / 8

-------------------------------------------------------------------------

Delay: 10.574ns (Levels of Logic = 7)

Source: y (PAD)

Destination: p (PAD)

Data Path: y to p

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 7 1.106 0.754 y_0_IBUF (y_0_IBUF)

LUT4:I0->O 2 0.612 0.532 b2/carry1 (c5)

LUT4:I0->O 2 0.612 0.532 b5/carry1 (c8)

LUT4:I0->O 2 0.612 0.532 b8/carry1 (c12)

LUT4:I0->O 2 0.612 0.532 b11/carry1 (c13)

LUT4:I0->O 1 0.612 0.357 b12/carry1 (p_7_OBUF)

OBUF:I->O 3.169 p_7_OBUF (p)

----------------------------------------


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Total 10.574ns (7.335ns logic, 3.239ns route)

(69.4% logic, 30.6% route)

=========================================================================

Total REAL time to Xst completion: 10.00 secs

Total CPU time to Xst completion: 10.91 secs

Total memory usage is 142012 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 3 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

Rowbypassing Multiplier:

Circuit diagram:

Code:

library IEEE;




---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity row is

Port ( a,b : in STD_LOGIC_VECTOR (03 downto 0);

p : out STD_LOGIC_VECTOR (07 downto 0));


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end row;

architecture Behavioral of row is

component ac is

port(a,b,c,d,e:in std_logic;

s,ca:out std_logic);end component;

component fa is

Port ( x : in STD_LOGIC;

y : in STD_LOGIC;

z : in STD_LOGIC;


end component;

component and21 is

Port ( x : in STD_LOGIC;y : in STD_LOGIC;

z : out STD_LOGIC);

end component;

signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15:std_logic;

signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,cc1,cc2,a1,a2,a3,a4,a5,a6,a7,a8:std_logic;

begin

an1:and21 port map(a(0),b(0),p(0));

an2:and21 port map(a(1),b(0),s1);an3:and21 port map(a(2),b(0),s2);

an4:and21 port map(a(3),b(0),s3);












ac1:ac port map(s4,s1,'0',b(1),'0',p(1),c1);

ac2:ac port map(s5,s2,'0',b(1),'0',a1,c2);


ac4:ac port map(s8,a1,c1,b(2),c2,a3,c4);


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ac6:ac port map(s10,s7,c3,b(2),'0',a5,c6);




an17:and21 port map(c1,not b(2),cc1);an18:and21 port map(c4,not b(3),cc2);

fa1:fa port map(a3,'0',cc1,p(2),c10);

fa2:fa port map(a6,cc2,c10,p(3),c11);

fa3:fa port map(a7,c7,c11,p(4),c12);


fa5:fa port map(s15,c9,c13,p(6),p(7));

end Behavioral;

----------------------------------------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

entity ac isport(a,b,c,d,e:in std_logic;

s,ca:out std_logic);

end ac;

architecture arc of ac is

signal a1,b1,c1,s1,ca1:std_logic;

begin

a1


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end dataflow;

------------------------------------------------------------------------------------------------------------------

library IEEE;


entity and21 isPort ( x : in STD_LOGIC;

y : in STD_LOGIC;

z : out STD_LOGIC);

end and21;

architecture dataflow of and21 is

begin

z


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Timing report:

Clock Information:

------------------


Asynchronous Control Signals Information:----------------------------------------


Timing Summary:

---------------

Speed Grade: -5





Timing Detail:

--------------


=========================================================================



-------------------------------------------------------------------------


Source: b (PAD)Destination: p (PAD)

Data Path: b to p

Gate Net


---------------------------------------- ------------

IBUF:I->O 29 1.106 1.224 b_1_IBUF (b_1_IBUF)

LUT3:I0->O 3 0.612 0.603 fa2/Mxor_sum_xo71 (N20)

LUT3:I0->O 1 0.612 0.509 fa2/carry167 (fa2/carry167)



LUT4:I0->O 2 0.612 0.532 fa2/carry211 (c11)

LUT3:I0->O 2 0.612 0.410 fa4/Mxor_sum_xo11 (N1)

LUT3:I2->O 2 0.612 0.449 fa4/carry1 (c13)

LUT4:I1->O 1 0.612 0.357 fa5/Mxor_sum_xo1 (p_6_OBUF)


----------------------------------------



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(64.3% logic, 35.7% route)

=========================================================================

Total REAL time to Xst completion: 12.00 secsTotal CPU time to Xst completion: 11.31 secs





Column-bypassing Multiplier:

Circuit diagram:

Code:

library IEEE;




entity column isPort ( a,b : in STD_LOGIC_vector(3 downto 0);

p : out STD_LOGIC_vector(7 downto 0));

end column;

architecture Behavioral of column is

component and21 is



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y1 : in STD_LOGIC;

z1 : out STD_LOGIC);

end component;

component buffer21 is

port (x:in std_logic;c:in std_logic;

z:out std_logic);

end component;

component mux is

Port ( a,b : in STD_LOGIC;

c : in STD_LOGIC;

z : out STD_LOGIC);

end component;

component fa is


y : in STD_LOGIC;z : in STD_LOGIC;


end component;

signal

s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s27,s28,s29,s30,s31,s3

2,s33,s34,s35,s36,s37,s38,s39,s40,s41,s42,s43,s44,s45,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14,q15,q16,

q17,q18:std_logic;

begin

a1:and21 port map(a(0),b(0),p(0));

a2:and21 port map(a(1),b(0),s2);a3:and21 port map(a(2),b(0),s3);

a4:and21 port map(a(3),b(0),s4);









a13:and21 port map(a(0),b(3),s13);a14:and21 port map(a(1),b(3),s14);



a17:and21 port map(a(0),s31,s34);



a20:mux port map(s2,s45,a(0),p(1));


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a21:mux port map(s3,s17,a(1),s39);


a23:mux port map(s39,s22,a(0),p(2));



a26:mux port map(s41,s28,a(0),p(3));a27:mux port map(s42,s29,a(1),s35);


a29:fa port map('0',q1,q2,s45,s19);



a32:fa port map(s19,q7,q8,s22,s25);





a37:fa port map(s27,q17,q18,s30,s33);a38:fa port map('0',s34,s35,p(4),s43);

a39:fa port map(s43,s37,s36,p(5),s44);

a40:fa port map(s44,s38,s16,p(6),p(7));

u1:buffer21 port map(s2,a(0),q1);







u8:buffer21 port map(s9,a(0),q8);u9:buffer21 port map(s40,a(1),q9);










end Behavioral;----------------------------------------------------------------------------

library IEEE;




entity fa is



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y : in STD_LOGIC;

z : in STD_LOGIC;


end fa;

architecture dataflow of fa is

begin

sum


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end process;

end behv;

-----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;


entity buffer21 is

port(x,c:in std_logic;

z:out std_logic);

end buffer21;

architecture structural of buffer21 is

begin

process(x,c)

beginif(c='1')then

z


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# MUXF5 : 10

# MUXF6 : 3

# MUXF7 : 1

# IO Buffers : 16

# IBUF : 8

# OBUF : 8=========================================================================

Timing report:

Clock Information:

------------------



----------------------------------------


Timing Summary:

---------------

Speed Grade: -5





Timing Detail:

--------------


=========================================================================



-------------------------------------------------------------------------


Source: b (PAD)


Data Path: b to p

Gate Net


---------------------------------------- ------------


LUT4:I0->O 1 0.612 0.387 a24/z_SW3 (N49)

LUT4:I2->O 2 0.612 0.383 a24/z (s41)

LUT4:I3->O 2 0.612 0.532 a17/z11 (s34)


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LUT2:I0->O 3 0.612 0.603 a39/Mxor_sum_xo21 (N121)

LUT4:I0->O 3 0.612 0.603 a40/carry11 (N01)

LUT4:I0->O 1 0.612 0.000 a40/carry51_F (N56)

MUXF5:I0->O 1 0.278 0.426 a40/carry51 (a40/carry51)

LUT2:I1->O 1 0.612 0.357 a40/carry61 (a40/carry61)

OBUF:I->O 3.169 p_7_OBUF (p)----------------------------------------


(66.7% logic, 33.3% route)

=========================================================================







Row-column bypassing multiplier:

Circuit diagram:

Code:

library IEEE;




entity mul_2d is



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end mul_2d;

architecture Behavioral of mul_2d is

component and21 isport(a,b: in std_logic;

z:out std_logic);

end component;

component ac1 is

Port (a,b: in std_logic;

s,c:out std_logic);

end component;

component ac2 is

Port (a,b,c: in std_logic;s,ca:out std_logic);

end component;

component fa is

Port (a,b,c: in std_logic;


end component;

Signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15: std_logic;

signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,a1,a2,a3,a4,a5,a6: std_logic;

beginan1:and21 port map(a(0),b(0),p(0));















ca11:ac1 port map(s1,s4,p(1),c1);

c22:ac1 port map(s2,s5,a1,c2);


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c33:ac1 port map(s3,s6,a2,c3);

c44:ac2 port map(a1,c1,s8,p(2),c4);

c55:ac2 port map(a2,c2,s9,a3,c5);

c66:ac2 port map(s7,c3,s10,a4,c6);

c77:ac2 port map(a3,c4,s12,p(3),c7);

c88:ac2 port map(a4,c5,s13,a5,c8);c99:ac2 port map(s11,c6,s14,a6,c9);

fa1:fa port map(a5,c7,'0',p(4),c10);



end Behavioral;

----------------------------------------------------------------------------------------------------

Library ieee;

Use ieee.std_logic_1164.all;

Entity ac1 is

Port (a,b: in std_logic;

s,c:out std_logic);end ac1;

architecture arc of ac1 is

signal s1,c1:std_logic;

begin

c1


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library ieee;


entity fa is

port(a,b,c: in std_logic;

s,ca: out std_logic);

end fa;architecture arc of fa is

begin

s


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=========================================================================

Timing report:

Clock Information:

------------------No clock signals found in this design


----------------------------------------


Timing Summary:

---------------

Speed Grade: -5





Timing Detail:


=========================================================================



-------------------------------------------------------------------------


Source: b (PAD)


Data Path: b to p

Gate Net


---------------------------------------- ------------


LUT4:I1->O 2 0.612 0.532 c33/s1 (a2)

LUT4:I0->O 2 0.612 0.383 c55/ca1 (c5)

LUT4:I3->O 2 0.612 0.532 c88/s1 (a5)

LUT4:I0->O 2 0.612 0.532 fa1/ca1 (c10)

LUT3:I0->O 2 0.612 0.532 fa2/ca1 (c11)

LUT4:I0->O 1 0.612 0.357 fa3/ca1 (p_7_OBUF)



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----------------------------------------


(68.6% logic, 31.4% route)

=========================================================================



-->





2-Dimensional multiplier:

Circuit diagram:

Code:

library IEEE;




entity bypass_mul is



end bypass_mul;


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architecture Behavioral of bypass_mul is

component ac is



end component;

component fa is


y : in STD_LOGIC;

z : in STD_LOGIC;


end component;

component and21 is


y : in STD_LOGIC;

z : out STD_LOGIC);end component;

signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15:std_logic;

signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,cc1,cc2,a1,a2,a3,a4,a5,a6,a7,a8:std_logic;

begin

an1:and21 port map(a(0),b(0),p(0));















ac1:ac port map(s4,s1,'0',b(1),'0',p(1),c1);ac2:ac port map(s5,s2,'0',b(1),'0',a1,c2);








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an17:and21 port map(c1,not b(2),cc1);

an18:and21 port map(c4,not b(3),cc2);

fa1:fa port map(a3,'0',cc1,p(2),c10);

fa2:fa port map(a6,cc2,c10,p(3),c11);

fa3:fa port map(a7,c7,c11,p(4),c12);fa4:fa port map(a8,c8,c12,p(5),c13);


end Behavioral;

----------------------------------------------------------------------------------------------------------------

library ieee;


entity ac is



end ac;

architecture arc of ac issignal a1,b1,c1,s1,ca1:std_logic;

begin

a1


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entity and21 is


y : in STD_LOGIC;

z : out STD_LOGIC);

end and21;architecture dataflow of and21 is

begin

z


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TIMING REPORT:

Clock Information:

------------------



----------------------------------------


Timing Summary:

---------------

Speed Grade: -5





Timing Detail:

--------------


=========================================================================



-------------------------------------------------------------------------


Source: a (PAD)


Data Path: a to p

Gate Net


---------------------------------------- ------------

IBUF:I->O 10 1.106 0.902 a_1_IBUF (a_1_IBUF)

LUT4:I0->O 2 0.612 0.532 ac2/ca1 (c2)


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LUT4:I0->O 4 0.612 0.651 ac4/ca (c4)

LUT4:I0->O 2 0.612 0.532 ac7/s1 (a6)

LUT4:I0->O 2 0.612 0.532 fa2/carry1 (c11)

LUT3:I0->O 2 0.612 0.532 fa3/carry1 (c12)

LUT3:I0->O 2 0.612 0.532 fa4/carry1 (c13)

LUT4:I0->O 1 0.612 0.357 fa5/carry1 (p_7_OBUF)


----------------------------------------


(65.2% logic, 34.8% route)

=========================================================================








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Comparative analysis of 4-bit multipliers

Table 1

Dynamic

Multiplier name Power Delay Area

Consumption

BRAUN 0.43mw

10.574ns

14666

MULTIPLIER m

BRAUN

MULTIPLIER 0.82mw

14.273ns

24821

WITH ROW m BYPASSING

BRAUN

MULTIPLIER 0.40mw

13.239ns

15354

WITH COLUMN m BYPASSING

BRAUN 2-

DIMENSIONAL 0.31mw

11.581ns

13863

BYPASSINGm

2

MULTIPLIER

BRAUN

MULTIPLIER0.49mw 16895

WITH ROW AND 13.128ns m COLUMN

BYPASSING

Conclusion:

From the comparison table I, it is clear that Braun 2-dimensional bypassing multiplier has least power

consumption at 1GHz and also it is most effective in terms of area.


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