Digital Electronics Concepts

CS2201 Switching Circuits and Logic Design

Rajiv Gandhi University of Knowledge Technologies Sk.Riyaz Hussain

Module-1

DIGITAL AND ANALOG SIGNALS

An electrical signal can be defined as the variation of electrical quantity i.e

voltage or current with respect to time.That means the signal which does not vary with

respect to time is not a signal.For example D.C is constant with respect to time even

though it is a signal.

Fig:Analog Signal

An analog signal is a signal which takes any value from the given by taking the values

of electrical signal at different time intervals.

A system can be defined as a physical device that performs an operation on a signal.

Signals can be categorized in various ways:for example, discrete time signals and

continuous time signals.Even when the signal functions are not continous,continuous



time signals can be referred as continuous signals.Another category of signals discrete-

valued and continuous-valued otherwise known as digital and analog signals.The analog

signals can have an infinite no.of values.

Analog systems can be called wave systems.The digital signals are specified as one

of the two possibilities such as 1 or 0, HIGH or LOW, TRUE or FALSE.Digital is a method

of storing, processing, and transmitting information through the use of discrete

electronic pulses that represent the binary digits 0 and 1.While the no.of recording

intervals of analog signal increases, the accuracy of signal increases.There are many

advantages with digital signals over analog signals, that is the reason why we use digital

signals more.

Advantages of Digital signals:-

Noise Margin:

Digital signals are less effected by noise.If the noise is below a certain level

all.However if the noise exceeds this level, the digital circuit can not give correct results.

Error correction and detection:

Digital signals can be regenerated to achieve lossless data transmission, which contain

limits.Analog signals transmission and processing , by contrast always introduces noise.

Digital systems interface well with computers and are easy to control with software.It

is often possible to add new features to a digital system without changing hardware

and to do this remotely, just by uploading new software.

Cheap electronic circuits:

More digital circuitary can be fabricated per sqare millimeter of integrated circuit

material.Information storage can be much easier in digital systems than in analog

ones.In an analog system, aging and wear and tear will degrade the information in

storage, but in digital systems as long as the wear and tear is below a certain level, the

information canbe recovered perfectly.Theoritically,there is no data loss when copying

digital data.This is a great advantage over analog systems which faithfully reproduce



every bit of noise that makes its way into the signal.

Disadvantages:-

The world in which we live is analog, and signals from this world such that light,

temperature, sound, electrical conductivity, electric and magnetic fields and

phenomenon of such as flow of time, are of most particular purpose continuous and

thus analog quantities rather than discrete digital ones.

For a digital system to do useful things in real world, translation from continuous

realm to the discrete digital realm must occur, resulting in quantization errors.This

problem can usually be integrated by designing desired degree of fredility.The nyquist

shannon theorem provides an important guide lines as to how much digital data is

needed to accurately portray a given analog signal.

Digital systems can be fragile, in that if a single piece of data is loss or

misinterpreted, the meaning of large blocks of related data can completely change.This

problem can be diminished by desigining the digital system for robustness. Digital

circuitry use more energy than analog circuits to accomplish the same calculations and

signal processing takes, thus producing more heat as well. In portable or battery

powered systems this can be a major limiting factor. Digital systems cause problems

such as "glitches", pulses do not reach valid switching voltages or unexpected

combinations of logic states.

A corollary of the fact that digital circuits are made from analog components is the

fact that digital circuits are slower to perform calculations than analog circuits that

occupy a similar amount of physical space.However the digital circuit will perform the

calculation with much better repeatability due to the high noise immunity of digital

circuitry.

Reference Books:

1.Digital Design 3rd Edition by M.M.Mono,2002.

2.Fundamentals of logic design by C.H.Roth, Jaico Publisher,1998.



Module-2

NUMBER SYSTEM

A Digital D

D System A

C C

Analog in Computer Analog out

In conventional arithmetic, a number system based upon 10 units(0-9) is used.

However arithmetic and logic circuits used in computers and other digital systems

operate only on 0”s and 1”s.Because it is very difficult to design circuits that require 10

distinct states. The number system with the basic symbols 0”s and 1”s is called binary i.e

a binary system uses just two discrete values.

A group of bits which is used to represent the discrete elements of information is a

symbol .The mapping of symbols to a binary value is known as binary code. This

mapping must be unique.

Decimal numbers:

The decimal system has 10 symbols: 0,1,2,3,4,5,6,7,8,9. In other words it has a base

of 10.

The number 2734 can be interpreted as



2X1000 + 7X100 + 3X10 + 4X1

= 2000+700+30+4

4 is the LSD and 2 is the MSD

In general in a number system with a base or radix r, the digits used are from 0 to r-1

and the number can be represented as

N=anrn+an-1r

n-1+-------------+a1r

1+a0r

0 where n=0,1,2,3,------------------

r= base or radix

a = no.of digits having values between 0 and r-1

The above equation holds for all integers. For the fractions the following equation holds

N=a-1r-1

+ a-2r-2

+-----------------+ a-n+1r-n+1

+ a-nr-n

Thus for decimal fraction 0.7123

N = 0.7000 + 0.0100 + 0.0020 + 0.0003

Where a-1 = 7

a-2 = 1

a-3 = 2

a-4 = 3

Binary numbers:

The binary number has a radix of 2. As r = 2, only wo digits are needed.These are 0 and

1.For the decimal system, radix is 10 which needs 10 digits.

Example:The decimal equivalent of the binary number 101010

N = (101010)2

= 1X25+0X2

4+1X2

3+0X2

2+1X2

1+0X2

0



= 43

For N symbols to be represented, the minimum no.of bits required is the lowest

integer “r” that satisfies the relationship

2r > N

For example If N=26, minimum ’ r ‘ is 5 since 24=16 and 2

5=32

Octal numbers:

Octal systems use a base or radix of 8.Thus it has digits from 0 t0 7(r-1)

Ex:- The decimal equivalent of the octal number 15.2

N = (15.2)8

= 1X81

+ 5X80

+ 2X8-1

= 13.25

Hexadecimal numbers:

The hexadecimal numbering system has a base of 16.There are 16 symbols.The

decimal digits 0 to 9 are used as the first ten digits in the decimal system, followed by

the letters A,B,C,D,E,F which represents the values 10,11,12,13,14 and 15 respectively.

Below table shows a relatioship between decimal, binary, octal and hexadecimal

number systems.



Decimal Binary Octal Hexadecimal

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0

1

2

3

4

5

6

7

10

11

12

13

14

15

16

17

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F



Number base conversions:-

Radix divide and multiply method is generally used for conversion.If the number

includes a radix point, it is necessary to separate the number into an integer part and

fraction part, since each part must be converted differently.The conversion of decimal

integer to a number in base r is done by dividing the number and succesive quotients by

r and accumulating the remainders . The conversion of a decimal fraction is done by

repeated multiplication by r and the integers are accumulated instead of remainders.

Integer part:

Repeated divisions by r yield LSD to MSD

Fraction part:

Repeated multiplications by r yield MSD to LSD.

Ex: Conversion of decimal 23 to binary is by divide decimal value by ( 2 the base) until

the value is 0.

2 23

2 11 1 ---- LSD

2 5 1

2 2 1

2 1 0

0 1 ----- MSD

The answer is 2310 = (10111)2

Ex: Convert (0.7854) to binary

0.7854X2=1.5708 ; a-1 = 1

0.5708X2=1.1416; a-2=1



0.1416X2=0.2832; a-3=0

0.2832X2=0.5664; a-4=0

For converting a binary number to octal, the following procedure can follow

1. Group the no.of bits into 3’s starting at least significant symbol. If the no.of bits

are not evenly divisible by 3, then add o’s at the most significant bit.

2. Write the corresponding 1 octal digit for each group

Ex: 100 010 011

4 2 3

For converting a binary number to hexadecimal, the following procedure can follow

1. Group the no.of bits into 4’s starting at least significant symbol.If the no,of bits is

not evenly divisable by 4, then add 0’s at the most significant end.

2. Write the corresponding 1 hex digit for each group.

Ex: 1001 1110 0111 0000 (binary)

9 E 7 0 (hexadecimal)

Assignment:

Convert any given decimal number into a binary form.



Module-3

LOGIC GATES

Digital signal takes discrete level, we realize this by taking switch as an example “on “and” off”

represents two different states in the case of switch. If we have two level signal than we call it as

binary signal. We can convert analog signal into digital signal by using “analog to digital” converter. We

can represent the output signal in analog to digital converter by using multiple bits

In case of switch or in binary signals we represent “ON state’ as 5V “OFF state as 0V.

0V→ “ 0” level

Nominally 5V→”1” level

I am saying 5v nominally because of present technology we say 3.1v also as 1 level.

TYPES OF LOGIC:-

POSITIVE LOGIC;-

If “0” level represents low level and “1” level represents high level than we call such type of logic as

positive logic.

Level “0” →0v or -5v

Level ”1” →5v or 0v

“1” level value of the variable is greater than the “0” level value.

i.e 5 level 1>0 level 0

NEGATIVE LOGIC :-

If “0” level represents high value and “1” level represent low value than we call such type of logic as

negative logic.

Level “0” → 5v

Level “1” →0v

“1” level value of the variable is less than the “0” level value.

i.e 0 level 1 < 5 level 0


Rajiv Gandhi University of Knowledge Technologies

system always work on signals. We can develop systems with the help of subsystems. Subsystems contain

modules as basis. Each module contain several function, contain logic level.

The hierarchy diagram is

TYPES OF FUNCTIONAL BLOCKS:

The basic of functional blocks is logic. Two type of logic functions are present, these are

1. Combinational

2. Sequential

In digital systems we use both combinational and sequential function.

1.COMBINATIONAL FUNCTION:

witching Circuits and Logic Design


nals. We can develop systems with the help of subsystems. Subsystems contain

modules as basis. Each module contain several function, contain logic level.

systems

↓

Subsystems

↓

Modules

↓

Functions

↓

Logic levels

TYPES OF FUNCTIONAL BLOCKS:-


In digital systems we use both combinational and sequential function.


Sk.Riyaz Hussain

nals. We can develop systems with the help of subsystems. Subsystems contain




Output value depends only on the current input. No memory is needed to store or

remember any value

2.SEQUENTIAL FUNCTION:-

Output values are depends on the current inputs and past outputs. Memory element is required to

store the previous output. Sequential logic contains combinational logic also.

BASIC COMBINATIONAL BULDING BLOCK:-

Basic combinational building block in digital circuits is logic gates.

LOGIC GATES;-

A logic gate is an electric circuit that performs a particular logic function. Logic gates

have one or more inputs terminals and one output terminal. Each input terminals represents an

independent variable. At any given instance of time every terminal is one of the two binary

conditions as high or low. In most logic gates, low state is approximately 0 or high state is 5v.

Logic gates are different types depending upon the logical function preformed by the gate.

The different types are AND, OR, NOT, NAND, NOR, XOR, XNOR, gates.

AND GATE:-

The output is true if both inputs are true. Other wise the output is false.

SYMBOL:- the symbol of AND gate is given below

F=A*B is read as F is equal to A and B.

TRUTH TABLE:-

Previously I am considering 1 as “TRUE” 0 as “FALSE”



A B F

0 0 0

0 1 0

1 0 0

1 1 1

OR GATE:-

The output is true when one of the input is true and when the both inputs are true other wise the

output as false.

SYMBOL:-

F=A+B→OR gate representa on using input variables.

A+B can read as A OR B

TRUTH TABLE

A B F

0 0 0

0 1 1

1 0 1

1 1 1



NOT GATE:-

It has one input and one output terminal. When the input is high, output is low and when

input is low, output is high

TRUTH TABLE:-

NAND GATE;-

It has two or more inputs terminals and one output terminals. The output is an inversion of

output of AND gate. If A and B are inputs, output is NOT (A and B)

SYMBOL

TRUTH TABLE

A B

1 0

0 1



NOR GATE;-

It has two or more input terminals and one output terminal. The output of a NOR gate is an

inversion of the output of an OR gate i.e, if A and B are the inputs the output is NOT (A OR B)

SYMBOL;

TRUTH TABLE;-

A B F

0 0 1

0 1 1

1 0 1

1 1 0

A B Y

0 0 1

1 0 0

0 1 0

1 1 0



EX-OR GATE:-

It has two or more input terminal, and one input terminal when both inputs are low or high the

output is low. If both inputs differ it is high.

SYMBOL:-

TRUTH TABLE

EX-NOR GATE;-

It has two or more inputs terminals, and one output terminal. The output of EX-NOR gate is an

inversion of output of an EX-NOR gate. i.e, if A and B are the inputs and the Output of and EX-NOR

gate is NOT (A+B)

A B A

0 0 0

1 0 1

0 1 1

1 1 0



SYMBOL; -

TRUTH TABLE

A B F

0 0 1

0 1 0

1 0 0

1 1 1



Module-4

Universal Gates

Both NAND and NOR gates are called as universal gates , because we design any gate by

using any one of the two gates. First of all we see the construction of AND, OR, NOT, XOR, XNOR

gates by using NAND.

Universal NAND gate

See the NOT gate construction using NAND gate. The NOT gate truth table is

A

0

1

1

0

In the

implementation of NOT using NAND we have to take only one input A.

TRUTH TABLE OF NAND

A B C

0 0 1

1 0 1

0 1 1



1 1 0

Eliminate 2 and 3 rows from the NAND truth table and make B=A. we get NOT gate.

AND

We get AND with the help of NAND by inverting the output of the NAND gate.

Replace NOT gate with equivalent NAND then we get AND gate.

The truth table of the above circuit diagram is same as AND gate.

A B F

0 0 0

0 1 0

1 0 0

1 1 1

0R



Invert both inputs A and B and provide it to NAND gate as inputs and we get OR gate as output

write equivalent NAND representation of NOT

NOR GATE

Invert output of OR then we can get NOR gate by using NAND gate.

The truth table of OR and NOR as same as previous. Because now we are constructing these gates

by using NAND GATE

X-OR GATE



Implementation of X-OR given above by using NAND gates.

X-NOR GATE

Inverting X-OR gives X-NOR gate.

UNIVERSAL NOR GATE:-



NOR

A B F

0 0 1

1 0 0

0 1 0

1 1 0

NOT GATE designing;-

Remove 2 and 3 and make B=A and give A as input to NOR then we get NOT gate as the output

TRUTH TABLE

A

0 1

1 O

OR GATE:-



Inversion of NOR gate gives OR gate

AND GATE:-

We design AND gate using NOR by inverting the both inputs A and B to the NOR gate.

Replace NOT gate by equivalent NOR circuit.

NAND GATE:-

Inversion of AND gate gives NAND gate.



X-NOR USING NOR:-

X-OR USING NOR:-



By inverting the output of X-NOR we get X-OR.



MODULE -5

BOOLEAN ALGEBRA

1. Boolean algebra works with binary variables.

2. A Boolean algebra is an algebraic system consisting of the set {0,1} the binary operations called OR,AND,NOT and denoted by the symbols "+","." and "prime" respectively.

3. Boolean algebra enables the logic designer to simplify the circuit used achieving economy of construction and reliability of operation.

4. Boolean algebra suggests the economic and straight forward way of describing the circuitary used in any computer system.

5. Boolean algebra is unique in the way that , it takes only two different values either 0 or 1

a. it doesn't have negative number.

b. it doesn't have fraction number.

6. the basic boolean postulates

a. logical multiplication based on AND function.

* 0 . 0 =0 * 0 . 1 = 0 * 1 . 0 = 0 * 1 . 1 = 1

b. logical additions based on OR function.

* 0 + 0 = 0 * 0 + 1 = 1 * 1 + 0 = 1 * 1 + 1 = 1

c. complement based on NOT function.

* 0 = 1 * 1 = 0.

7. boolean properties.

a. properties of AND function

1. x . 0 = 0 2. 0 . x = 0 3. x . 1 = x 4. 1 . x = x.

b. properties of OR function.

5. x+ 0 =x 6. 0 + x = x 7. x + 1 = 1 8. 1 + x = 1 9. 0 + ᶲ = ɸ



c. combining a variable with itself OR its compliment.

10 . x . x = o 11. x . x = x 12. x + x = x 13. X + x = 1 14. X = x

d. commutative laws.

15. x . y = y . x 16. x + y = y + x

e. distributive laws.

17. x(y+z) = x.y + x.z 18. X + y.z = (x+y) (x+z)

f. associative laws.

19. x(y.z) = (x.y)z 20. X+(y+z)= (x+y)+z

g. absorption laws

21. x+xy=x 22. x(x+y) =x 23. x+ x y = x+y 24. x(x+ y)= xy

h. demorgans laws.

25.(x+y) = x . y 26. (x.y) = x + y

8. In boolean algebra ‘’ 1’’ is called multiplicative identity and “0” is called additive identity.

* LITERAL : A primed or unprimed boolean variable is called literal. Each variable can have maximum of two literals.

Eg: X Is a variable which can have two literals x and x .

Proof for some properties ;

17. X + YZ = (X+Y) (X+Z)

R.H.S = X.X+X.Z+X.Y+Y.Z

=X + XZ +XY +YZ

=X(1+Z)+XY+YZ

=X+XY+YZ [ 1+ Z = 1 ]

= X (1+Y)+(Y+Z) [1+Y= 1]

= X + YZ = L.H.S



22. X+ XY = X+ Y

L.H.S = X + XY

=(X + X)(X+Y)

=X+Y = R.H.S

23. X(X + Y) = XY

LHS = XX + XY = 0 + XY = XY =RHS

9. logics circuits can be simplified by simplifying the boolean equation using any one of the following methods :

a) applying boolean properties.

b) karnaugh – map method of simplification

c) tabulation method

10. The properties of boolean algebra are useful for the simplification of boolean equation leading to minimum structure.

11. simplify the boolean equation Z = XY + X (X+Y)

XY + X (X+Y) = XY + XX + XY

= XY + XY

= (X+ X) Y = Y

DUALITY PRINCIPLE : The important property of boolean algebra is the duality principle.

It states that every algebraic expression deducible from theorems of boolean algebra remains valid if the operators and identify elements are interchanged.

EXAMPLES :-

X + X = X X.X= X BY duality

X + 1 = 1 x.0= 0 by duality

X + x y= x x(x +y)=x by duality

X + y= y + x xy=yx by duality



X +(Y + Z)=(X+Y)+Z X (YZ)= (XY) Z

By duality

• The dual of the exclusive – OR is equal to its complement

• A simple procedure to find the complement of a function is to take the dual of the function and complement of each literal.

12. Standard product or minterm (M): consider two binary variables x and y combined with an AND operation. Since each variable appears in direct form or in its complement form there are four possible combinations X Y, X Y, X Y and XY. Each of these four AND terms is called a minterm or a standard product.

X Y MINTERM m

0

0

XY

m0

0

1

XY

m1

1

0

XY

m2

1 1 XY m3

Standard sum or Maxterm (M): Two binary variables X and Y combined with an OR operation we will an OR operation we will get four possible combinations X+Y, X+ӯ, Ẋ+Y and Ẋ+ӯ. Each of these four OR terms is called a Maxterm or a standard sum term.

X Y Maxterm (M) 0 0 M0

X+Y 0 1 M1

X+Ẏ 1 0 M2

Ẋ+Y 1 1 M3

Ẋ+Ẏ

Each Maxterm is the compliment of its corresponding minters and vice versa.

Eg: - XY = Minterm

The compliment of minterm = (XY) = Ẋ + Ẏ = Maxterm



13. CANONICAL FORM: Expressing the Boolean function in standard sum of product form (SSPO) or standard product of sums form (SPOS) is called canonical form.

1. A Boolean function may be expressed algebraically from given truth table by forming a minterm for each combination of variables which produces 1 in the function, and then taking the OR of all those terms.

X Y F 0 0 0 0 1 1 1 O 1 1 1 1

F(X, Y) = X Ẏ + Ẋ Y = Ʃ m (1, 2)

This representation is called SSOP form. minterm or product of maxterm are said to be canonical form.

3. Sum of products form can be implemented by using NAND – NAND realization.

4. NAND-NAND realization is same as AND – OR.

5. Product of sums form can be implemented by using NOR- NOR realization.

6. NOR – NOR realization is same as OR - AND.

7. If the signals are propagating through two stages of gates, then it is called two level gate network.

DEGENERATIVE FORM: A two level gate network is said to be degenerative if it degenerates to a single operation. The following two level gate networks are degenerative.

Forms:

AND-AND AND

OR-OR OR

OR -NOR NOR

NOR -NAND OR

NAND -NOR AND

AND -NAND NAND



Realizing the minimal sum of products form of a function form truth table using Boolean

algebra

We are not sure that the given function or logical circuit is in its simplest form. It is possible to design a circuit having less number of gates and inputs to realize the same function , then it saves hard ware. Reduction at gate level is important.

*Characteristic table of given function;

IN PUTS

A B C

OUTPUT

F(A,B,C)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0

0

1

0

1

1

1

1

*Here three input variables (A,B,C) are present. The possible minterms are 8.

They are:-



)111(),110(,)101(,)100(

,)011(),010(),001(),000(

7654

3210

ABCmCABmCBAmCBAm

BCAmCBAmCBAmCBAm

====

====−−−−

−−−−−−−−

Each row in the truth table is a minterm . Output is true i.e ’1’ for 5 minterms. Output is false i.e 0

for 3 minterms. Function is expressed as a sum of minterms for which output is true i.e’’1’’

∑=++++=

−−−−−−

)7,6,5,4,2(

),,(

m

ABCCABCBACBACBACBAF(SOP)

NOTE; Reduction means reducing the number of terms and number of variables in each term. Our

goal is to make it as minimum sum of products beyond which we can not reduce further

ACB

ACB

ACBAA

ACBA

ACBA

BBACBA

ABBACBA

CCABBACBA

CCABCCBACBACBAF

+=

+=

++=

+=

+=

++=

++=

+++=

++++=

−

−

−−

−−

−−

−−−

−−−

−−−−

−−−−−

))(1(

))((

)1(

)(

)()1(

)()(),,(

Alternative:-

−

−

−−

−−−

−−−−−−

+=

+=

++=

++=

++++=

CBA

ACB

ACBAA

ACABCBA

ABCCABCBACBACBACBAF

)(

),,(



This is the minimal sum of products form.

By using De Morgans Theorem ; we can use the minterms for which the output is false i.e ’’0’’. To

realise the function instead of using minterms for which the output is true i.e ’’1’’. Complement of the

function (−F ) is the sum of minterms for which the output is false i.e ’’0’’.

From this we can realize that the given function is the product of max terms for which output is false i.e ’0’. For max terms 0-variable ; 1- complement of variable.

3

1

0

)011(

)001(

)000(

MCBA

MCBA

MCBA

−++

−++

−++

−−

−

Module-6

Simplification of Boolean functions

• Map method of Boolean simplification

• KARNAUGH maps( K-maps):



Here we are using concepts of Boolean algebra in a systematic way. In it we are

mapping the truth table on a graph. Combining the outputs that are having logical

values has true that is ‘1’ to get the minimum possible solutions.

1. A map is a diagram made up of squares. Each square represents one minterm.

The number of squares in the karnaugh map is given by 2n. Where n= no. of

variables.

2. Two variable K-map consists of 4 cells or squares.

3. Three variable K-map consists of 8 squares or 8 cells

4. 4 variable K-map consists of 16 squares or 16 cells.

5. To maintain adjacency property gray code sequence is used in K-map(any 2

adjacent cell will differ by only one bit)

• Three variable K-map:

A,B,C are three input variables so we have 8 minterms so this graph contains 8

cells or squares.

A BC 00 01 11 10

[�̅ = 0][A=1] 0

1

• ‘A’ varies vertically, ‘B,C’ varies horizontally

• Adjacency Rule:

Allowing only one of the variable to vary from one cell to neighbor cell in

horizontal and in vertical direction, but not diagonally

• In the map we are denoting “11” after “01” because of adjacency rule.

�̅��̅ �̅�� ̅�� ̅��̅

��̅ �� ̅



For ex: Assume output is true for minterms �̅��C and �̅BC then we can combine these

minterms. = �̅ ��C + �̅ BC

= �̅C(��+B)

= �̅C [Here one variable is removed that is “B”]

So we removed the variable which is varying from one cell to its neighbor cell.

Denoting “11” after “01” give a way to remove only one variable which is varying.

Consider a function F= A+B�̅

• Combine the cells that are having “1”, side to side or top to bottom and find which variable has

compliment in one cell and true in adjacent cell that variable can be eliminated.

(I) It is the sum of minterms 2 and 6

�̅ B�̅ + AB�̅ = B�̅(�̅+A) =B�̅ [here ‘A’ only varies vertically]

• “A” variable is eliminated.

A B C

F

First min term – m0 ------ 0 0 0

Second min term- m1----- 0 0 1

Third min term- m2----- 0 1 0

Fourth min term –m3----- 0 1 1

Fifth min term—m4---- 1 0 0

Sixth min term ---m5----- 1 0 1

Seventh min term ----m6--- 1 1 0

Eighth min term ----m7 --- 1 1 1

0

0

1

0

1

1

1

1

1

1 1 1 1

BC A

00 01 11 10

0

1



[II] it is the sum of min terms 4,5,7 and 6 . here A remains constant and B and C varies with in these four

cells horizontally.

So II = A

Now F is the sum of these two equations (I) + (II)

Therefore, F = A+B�̅

This is the simplified Boolean equation using K-map method.

• Four variable map :

Ex: simplify the Boolean function

F (P,Q,R,S) = ∑ m(0,2,3,7,11,13,14,15)

The given function is the sum of min terms 0,2,3,7,11,13,14,15 these are min terms for which output is

true i.e. “1” . in the map, map the cells corresponding to these min terms as “1” .

RS

PQ 00 01 11 10

00

01

11

10

NOTE: here 8th

min term comes in last because we followed the denoting order 00, 01, 11, 10

1) Try to combine as many ones as possible in a given group, but they should all be adjacent.

2) Always start with a highest possible group of one’s because sometimes the smaller group may

submerge with in the larger group.

3) We can combine a cell with “1” more than once.

4) Every one (1) should be included without leaving any one.

I-this is the maximum block of ones. Here PQ varies vertically and RS remains same. This is the combination of 3,

7, 15, 11. So we can eliminate variables PQ and RS remain in the final solution.

I= RS

II- this is the combination 13, 15. In it R only varies horizontally and PQS remains constant. So

II= PQS

III- this is the combination of 14,15. Here S varies horizontally. So III= PQR

1 1 1

1

1 1 1

1



IV- this is the combination 0,2. Here the logical adjacency exists between the cells 0 and 2 as IV= ��̅��

Since R only varies from 2 to 0.

Final expression can be written as

F= (I) + (II) +(III) +(IV)

F= RS + PQS + PQR + ��̅��

Each of the product term (I, II, III, IV) which are combined to form sum of products is called an implicant.

Implicant:- Any possible group ones.

Example:- 1) {0,2} 2) {3,2} 3) {3,7} 4) {7,5} 5) {13,15} 6) {14, 15}

7) {11, 15} 8) {3,7,15,11}

Prime Implicant:- largest possible group ones. Implicants may be submerged into a prime implicants.

Eg: {0,2}, {3,7,5,11}, {13,15}, {14,15}

Essential Prime Implicant:- A group with at least one cell with truth value “1” has not been covered in any

prime implicant.

Eg: {0,2}, {3,7,5,11}, {13,15}, {14,15}

Those are the four essential prime implicants because they have at least one truth value “1” which is not

covered.

Note1:- To eliminate n variables there should be a combination of 2n adjacent cells having output as true i.e. “1”

Note2:- An essential prime implicant covering all min terms having unique minimal form

Eg:- F= ∑ m(12,15,13,7,15,6,11)

Note3:- For the given function in K-map every min term is covered exactly by two prime implicants such a K-map

is called cyclic.



Module-7

VARIABLE MAPS

INTRODUCTION:

In the last lecture we introduce the map method of boolean simplification. we use a karnaugh map which is a graphical representation of a truth table, filled this graph with 1's corresponding to the cells whose minterms had a output true. The object is to identify groups of 1's as large as possible with satisfying the adjacency rule.



FOUR VARIABLE K-MAP:

Four variable k-map consists of 24=16 squares or 16 cells. The rows and columns are numbered in a gray code sequence, with only one digit changing value between two adjacent rows or columns.

RULES TO SIMPLIFY K-MAPS:

1. At the time of grouping the adjacent cells containing 1's always use maximum

possible group.

2. All the 1's must be covered atleast once in any group.

3. At the time of grouping don't care(x) values can be taken as 1's.

4. All don't care values need not be covered.

fig: Four variable map

The combination of adjacent squares that is useful during the simplification process is easily determined from the inspection of four variable map.

• One square represents one minterm, giving a term of four literals.

• Grouping two adjacent squares containing 1's represents a term of three literals.

• Grouping four adjacent squares containing 1's represents a term of two literals.

• Grouping eight adjacent squares containing 1's represents a term of one literal.

m0 m1 m3 m2

m4 m5 m7 m6

m12 m13 m15 m14

m8 m9 m11 m10



• Grouping sixteen adjacent squares containing 1's represents the function=1(a term of zero literals).

No other combination of squares can simplify the function.

PRIME IMPLICANTS:

In choosing adjacent squares in a map, we must ensure that

1. All the minterms of the function are covered when we combine the squares.

2. The number of terms in the expression is minimized, and

3. There are no reduntant terms. some times there may be two or more expressions that satisfy the simplification criteria.

Any group of 1's is an implicant. A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map. If a minterm in a square is covered by only one prime implicant, that prime implicant is said to be essential.

FIVE VARIABLE MAP:

A five variable map needs 32 squares and a six variable map needs 64 squares. The five variable map shown in below fig. It consists of 2 four variable maps with variables A,B,C,D and E. Variable A distinguishes between the two maps, as indicated at the top of the diagram. The left hand four variable map represents 16 squares in which A=0, and the other four variable map represents the squares in which A=1. Minterms 0 through 15 belong with A=0 and minterms 16 through 31 with A=1. Each four variable map retains the previously defined adjacency when taken separately. In addition each square in the A=0 map is adjacent to the corresponding square in the A=1 map. For example, minterm 12 is adjacent to minterm 10to21.The best way to visualize this new rule for adjacent squares is to consider the two half maps as being one on top of the other. Any two squares that fall one over the other are considered adjacent.

SIX VARIABLE MAP:



By following the procedure used for the five variable map ,it is possible to construct a six variable map with 4 four variable maps to obtain the required 64 squares. Maps with six or more variables need too many squares and are impractical to use. the alternative is to employ computer functions with large number of variables.

Module-8

CODE CONVERTERS

INTRODUCTION:

We have seen the techniques for reduction of boolean functions by using boolean algebra as well as kmaps. The object is to design circuits as per the given specifications by using these techniques.

There are two types of the digital circuits i.e., combinational and sequential



circuits. Combinational circuits are the circuits whose output is based on the inputs and the sequential circuits are the circuits whose output is depends on the input and as well as the previous behaviour of the circuit.

DESIGN OF COMBINATIONAL CIRCUITS:

Code converters are one class of circuits in combinational logic. Code converters, more specifically encoders and decoders, have been used by security agencies to protect private information. Indeed code converters have proven to be so effective that the National Security Agency (NSA) has made a career out of creating and breaking codes.

Example:

When we speak into cellular phone, an encoder converts the sound of our voice into electrical signals. which can travel very fast over very long distances. When the electrical signal get to another cellular phone, a decoder converts the electrical signal back to the sound of our voice.

So code converters are used for more than protecting private information from spies.

The class of codes which are used for simplification of hardware one is called excess-3 code and other is called gray code.

DECIMAL TO EXCESS-3 CODE CONVERTER:

Excess-3 code is used to convert a set of numbers to another set of numbers. By this code arithmetic complementing operation is easier. This is the reason why we go for excess-3 code. The excess-3 system simply adds 3 to each number to make the codes look different. The excess-3 BCD system has some properties that made it useful in early computers.

BCD EXCESS-3

b3 b2 b1 b0 E3 E2 E1 E0



Table: Truth table BCD to excess-3

Now we will have to take each of the values E0,E1,E2,E3 and find out the logic

function which can represent E0,E1,E2,E3 in terms of b0,b1,b2,b3.

E0,E1,E2,E3 = f(b0,b1,b2,b3)

BINARY TO GRAY CODE CONVERTER:

The gray code is often used in digital systems that because it has the advantage that only one bit in the numerical representation changes between successive numbers.

Binary Code Gray Code

Decimal number

D C B A G3 G2 G1 G0

0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 . . . . . . . . . . . . . . . . 1 1 1 1

0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 X X X X . . . . . . . . . . . . . . . . X X X X



0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 2 0 0 1 0 0 0 1 1 3 0 0 1 1 0 0 1 0 4 0 1 0 0 0 1 1 0 5 0 1 0 1 0 1 1 1 6 0 1 1 0 0 1 0 1 7 0 1 1 1 0 1 0 0 8 1 0 0 0 1 1 0 0 9 1 0 0 1 1 1 0 1 10 1 0 1 0 1 1 1 1 11 1 0 1 1 1 1 1 0 12 1 1 0 0 1 0 1 0 13 1 1 0 1 1 0 1 1 14 1 1 1 0 1 0 0 1 15 1 1 1 1 1 0 0 0

Table: Truth table for binary to gray code conversion

GRAY CODE:

The gray code belongs to a class of codes called minimum change codes, in which only one bit in the code changes when moving from one code to the next. The gray code is non weighted code, as the position of bit does not contain any weight. The gray code is a reflective digital code which has the special property that any two subsequent numbers codes differ only by one bit. This is also called a unit distance code. In digital gray code it has got a special place.

CONVERSION FROM BINARY NUMBER TO GRAY NUMBER:

It is easy to convert the binary number to gray number. For example take a binary number i.e., 101101

Step 1: 101101 first write the MSB as it is i.e., 1

Step 2: add and bit next to the MSB i.e., 1+0=1



Step 3: again add 0 and 1 we get i.e., 0+1=1

Step 4: again add 1 and 1 we get 1+1=0

Step 5: in previous step carry is occured so neglect that carry. Note that don’t add

carry to next add numbers then again add 1+0=1

Step 6: add 0+1=1

Answer : Gray code is 111011

Module-9

PARITY GENERAROR

Parity Generator:

A parity bit is used for the purpose of detecting errors during transmission of binary

information .A parity bit is an extra bit included with a binary message to make the

number of is either odd or even. The message including the parity bit is transmitted and



then checked at the receiving end for the errors. An error is detected if the checked

parity does not correspond with the one transmitted

The circuit the generates the parity bit in the transmitter is called a parity generator and

the circuit that checks the parity in the receiver is called parity checker.

In even parity the added parity will make the total number of 1s

an even number of

amount and odd parity the added parity bit will make the total number of 1s an odd

amount it is not necessary that should odd parity has one and even parity as zero as

long as there is a complete understanding between sender and receiver these called

protocol they no what is the number of bits we sending they should also know whether

you send parity bit or not at the end of group. And also know odd parity or even parity.

In a three bit odd parity generator the three bits in the message to ether with the parity

bit are transmitted to their destination, where they are applied to parity checker circuit

.the parity checker circuit checks for errors in the transmission.

Since the information was transmitted with odd parity the four bits received must have

an odd number of 1s an error occurs during transmission if the four bits received have n

even number of 1s,indicating that one bit has changed during transmittion.The output of

parity of the parity checker is denoted by PEC(parity

Error checker) and it will be equal to 1 it an error occurs it the four, bits received has an

even number of is.



3-bit odd parity generator

Input output

A B C P

0 0 0 1

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

From the truth table the expression for output parity

P (A,B,C)= € (0,3,5,6)

From k.map

P= A¹B¹C¹+A¹BC+ABC¹+AB¹C



= A¹ (B¹C¹+BC) + A (BC¹+B¹C)

P

= A¹P¹+AP

= PA ⊕

= CBA ⊕⊕

Circuit Diagram:

4-Bit odd parity generator:

B3 b2 b1 b0 p

0 0 0 0 0

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 1

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 1

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 1

1 1 1 1 0



4-bit odd Generator:

BCD to 7-segment display decoder:

Every where we are using decimal numbers.In this circuit the inputs are

decimal to we have to use decimal to binary converter.A display is made up of an LED

independent on other leds.We need 7-outputs from circuit for 7 segments.



INPUTS OUTPUTS

A B C D a B c D e f G

0 0 0 0 0 1 1 1 1 1 1 0

1 0 0 0 1 0 1 1 0 0 0 0

2 0 0 1 0 1 1 0 1 1 0 1

3 0 0 1 1 1 1 1 1 0 0 1

4 0 1 0 0 0 1 1 0 0 1 1

5 0 1 0 1 1 0 1 1 0 1 1

6 0 1 1 0 0 0 1 1 1 1 1

7 0 1 1 1 1 1 1 0 0 0 0

8 1 0 0 0 1 1 1 1 1 1 1

9 1 0 0 0 1 1 1 0 0 1 1



−−+++= DBCDBDAa CDDCBb ++=

−−−

DCBc ++=−

DCBCBDCDBd−−−−−

+++=

−−−

+= DCDBe −−−−

+++= DBCBDCAf



−−−

+++= DCCBCBAg

There are so many gates common for some segments.So make as many as common

terms and rest of them are can’t be accommodated with them.Make that common

terms unique and reduce design effort.

Module-10



ARITHMETIC CIRCUITS

Arithmetic circuits:

Simplest arithmetic operation is adder

1. Half adder

2. Full adder

1. Half adder:

Half adder is one which can only take two digits and add the sum and

get the carry and not taking carry of previous position of addition.

A logic circuit for the addition of two one bit numbers is referred to as

an half adder.

A and B are the two inputs and s(sum) and carry(c) are the outputs

S=A+B

A B S C

0 1 1 0

1 0 1 0

1 1 0 1

Carry is when we have a digit over flowing that over flow has to accomdated

else where in the next time computation stak.you have to take into account

this over flow.



Circuit Diagram:

From truth table:

S=A B⊕

C=AB

The half adder is used for 1 bit addition.No practical use except for every

first bit position.It not used for multibit number.To over come this we need

another circuit known as full adder.Half adder has only two inputs and there

is no provision to add a carry coming from the lower order bits when multibit

addition is performed.



For this purpose a 3rd

input terminal is added and this circuit is used to add

An,Bn and Cn-1 where An and Bn are nth order bits of numbers A and B

respectively and Cn-1 is the carry generated from addition of (n-1)th order

bits.this circuit is refered to as full order.

Sum=A CiB ⊕⊕

Carry C0=AB+BC+CA

=AB+Ci(A+B)

This carry we can represent in XOR gates also.

C0=AB+Ci(A BA ⊕ )

But we will use this occasionally for to know next carry to reduce time delay



In this the adders we have time delay i.e propagation delay.carry

propagation and sum propagation there is no difference between these two

propagations.

Circuit Diagram:



In this circuit carry in is the carry out of previous addition such a adder

which take carry from previous addition is called full order.

This is used for practical purpose and for multibit

Truth table:

A B Cin S C0

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Output is represtion of number of 1s in input



But we mainly consider carry propagation delay because the carry has

to propagate through are the gates but no need of sum propagation.The sum

has to leave in every stage.

4-bit full adder:

The very first carry of total circuit we will take as ‘0’ and to calculate

sum in every stage we need carry out of previous stage so there is a delay of

carry propagation.



� Gate delay depends on number of inputs and type of gate.

� Full order is unit of propragation delay Tp.

� For 16 bit and 32 bit adders we need to cascade 4bit or 8bit full

adders.

Module-11

CARRY LOOK A HEAD ADDERS



Propagation delay is the average transition delay time for a signal to propagate from input to output.It is the

time delay between the application of a level change at the input and the change of state at the output of a

circuit. This propagation delay depends on the lenth of signal path or the length that the signal has to traverse

from input to the output.

When we would like to design faster system or faster circuits, the propagation delay has to be taken into

consideration where the length of the paths that the signal is going to traverse has to be reduced.

A carry look ahead adder is a type of adder used in digital logic that imp roves speed by reducing the amount

of time required to determine carry bits. consider for example a four fit adder where a carry bit is calculated

along the sum bit, and each bit must wait until the previous carry has been caluclated.

Here in this adder each bit will not wait for previous carry but looks carry ahead and thus reduces the wait time

to calculate the result. For example consider,

A = A3 A2 A1 A0

B = B3 B2 B1 B0

C3 S3 S2 S1 S0

For a full adder circuit the truth looks like

A B Ci C0

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0 A B = 1 is Ci = 1

1 0 1 1

Both A & B are ‘1 ’ , AB = 1

Here the carry output is ‘1’ if A & B are ‘1’ irrespective of the previous carry and the carry output is ‘1’. If

A B is ‘1’ an carry input is ‘1’. So we can conclude carry output as

1 1 0 1

1 1 1 1



Co = AB + (A B) Ci = G + PCi

Carry generate Carry propagate

If A and B are 1 then irrespective of the carry input the output carry is generated . so , we refer to it as carry

generate.

If A B I is 1 and ci=1 then output is generated that means the carry is generated based on the previous

carry that is propagrated. So, we refer to it as carry propagate.

Let us consider a 4-bit adder

B3 A3 B2 A2 B1 A1 B0 A0

CI Cin C-1

C3

Ci = Gi + Pi Ci-1

C0 = G0 + P0C-1

C1 = G1 + P1C0 = G1 + P1G0 + P1P0C-1

C2 = G2 + P2C1 = G2 + P2(G1+P1G0+P1P0C-1)

C3 = G3 + P3C2 = G3 + P3G2+P3 P2 (G1 + P1G0 + P1 P0 C-1)

Now from each Pi , Gi and C-1 we can generate each Ci from the set of equations that we have derived earlier .

so now the 4-bit adder can be remolded as.

+

C2

C1

C0



So, carry look ahead adder is one of basic techniques to improve speed of addition. In the basic adder

We have to wait for previous carries which is in contrast with this technique as it just the matter of extra

combinational logic.

Fan – in : no. of inputs can give to a gate without any degradation in the performance.

Fan – out : no.of outputs you can take from a gate to feed similar gates without degradation in the

performance of output.

Though CLA adder is quite advantareous regarding speed or the performance it has two

disadvantares.

1) Non uniformity or non modularity of CLA adder and

2) There is limit on no.of bits we have to do

So here in CLA adder each bit in a binary sequence to be added, the CLA logic will determine

whether the bit pair will generate a carry or propagate a carry.

Module-12

12. SUBSTRACTORS



COMPLEMENTS :

In digital systems complements are used for simplifying the subtraction operation and for

logical manipulation. There are two types of complements for each base-r system. The first is referred

to as the r’s complement and the second as the (r-1)’s complement.

For binary numbers of radix 2 the two types are referred to as 2’s complement and for decimal

numbers the two types are referred to as 10’s complement and 9’s complement.

r’s complement -------------- radix complement

(r-1)’s complement -------------- diminished radix complement

RADIX COMPLEMENT :

The r’s complement of an n-digital number N in base r is defined as rn-N , for N ≠0 and 0 for N=0

.

EG: the 10’s complement of decimal (1725)10 is 104 – 1725 = (8275)10

The 2’s complement of binary (101)2 is 23

-101 = 1000-101 = (011)2.

DIMINISHED RAIDX COMPLEMENT :

Given a number N in base r having n digits, the (r-1)’s complement of N is defined as (rn-1)-N.

Eg: for a decimal number 729 of base 10 the (10-1)’s complement

Or

9’s complement = (103-1)-729=999-729=27010

For a binary number 1101 of base 2 the (2-1)’s complement or

1’s complement = (24-1) – 1101 = (10000-1)-1101 =1111-1101 = (0010)2.

We can obtain r’s complement from (r-1)’s complement by adding 1 to it.

SUBSTRACTION USING COMPLEMENTS :



In the direct method of subtractions we use the barrow concept which is less efficient than

method that uses complements so, now we turn our attention towards indirect method of subtraction

that uses complements.

Let us consider the substraction of two signed numbers M,N in base r. there 2 cases will occur. They

are if 1) M>N 2) M<N

CASE – 1 :

Here inorder to perform M-N we compute M + (r’s complement of N ) this performs

M+(rn – N ) = M – N + r

n

The above sum will produce an end carry , rn, which can be discarded

= M – N + rn

--------- discarded [ rn = M-N]

e.g. Let M =0110 ---------------6

N = 0011 -----------------3

2 ‘s compliment of N= 1100+1=1101

M-N= 0110 – 1101=*0011 = 0011 --------3 (*is discarded carry)

Without discarding carry the sum will be M+(rn-N) which rearranged as M-N+r

n. so, inorder to obtain M-N, r

n

should be removed.

M-N = M+(rn-N)-r

n

In the previous example the sum is 10011 and rn

=10000

=>M-N = 1001 – 10000 = 00011 ---------- 3

END AROUND CARRY (EAC):

EG : let M = 0101, N = 0010

1’s complement of N =1101

M + 1’s complement of N --------- 0101 + 1101 = *0010 + 1 = 0011

Here we added 1’s complement of N to M. but subtraction of N from M is equal to addition of



M and 2’s complement of N. so we need to add 1 to 2’s complement the number inorder to do so we utilize the

discarded overfilow that means in the sense we bring the carry around and add this to the sum that is obtained

in the previous step. After adding the carry to the list significant digit of the sum we obtained desired result.

Remember that if the discarded bit is 1 , the result is positive . if the discarded bit is 0, the result is

negative.

CASE – 2 :

Here M<N and the sum doesn’t produce an end carry and is equal to M+(rn-N) which can be rearranged

as rn

– (N-M) that means the sum is rth

complement of (N-M).

Therefore M-N = -(N-M)

= -(rn

– (rn-(N-M)) ) = -(r

n - SUM)

= -( 2’S COMPLEMENT OF SUM ) where SUM = rn-(N-M).

Here sum is not the actual result . as the discarded bit is 0 in this case the result is a negative with

magnitude equal to 2’s complement of sum . actually the sum is signed representation of the negative result as

most significant bit is 1.

To demonstrate this above hypothesis let us consider an example.

E.g.: M = 0011 , N = 0101

2’s complement of N = 1010 + 1 = 1011

Therefore M ----------- 0 0 1 1

2’s complement of N ------------ 1 0 1 1

Sum------------- 1 1 1 0

MSB

Therefore M-N = -(2’s complement of sum )

= -(0010) = -2

Here the discarded bit is ‘0’ indicates that the result negative and MSB as 1 indicates that the result is signed

representation of -2.

MODULE-13



2'S COMPLEMENT SUBTRACTOR AND BCD ADDER

1'S COMPLEMENT: The invertor of the given number. Ex: Q: 101001 Ans : 010110 2'S COMPLEMENT: 1's complement of given number plus one.

Ex: Q: 1001 1's complement of number - 0110 Adding one to the number - 1 2's complement of number - 0111 Let A, B are two binary numbers If both are positive then add those numbers If A or B or both are negative, then to add these numbers we have to use 2's complement method. Ex: (1) A 0101 B 1001 A+B 1110 (2 A 0101 1's complement of B 0110 B 1001 2's complement of B 0111 (-B) A-B 1100 A 0101 (-B) 0111 A+ (-B) 1100 -4 Since 1 100 indicates - 4 If MSB is 1 then the number is negative. If MSB is 0 then the number is addition of complement numbers. In case of binary numbers, it is 2's complement. 4 - BIT REPRESENTATION OF NUMBERS:

• Here Most Significant Bit is singed bit and remaining three are magnitude bits. • If MSB is Zero then number is greater than or equal to zero (>=) that is positive. • If MSB is one then number is less than Zero (<) that is negative.

Ex: (1) b3 b2 b1 b0 if b3 is '0' then it is "positive". if b3 is '1' then it is "negative". (2) Q: 0 0 0 1 A: + 1 (3) Q: 0 1 0 1 A: + 5

(4) Q: 1 0 1 1 A: - 6 Here MSB is '1", it is negative. So we have to do 2's complement. Q: 1 0 1 0 1's complement of number 1 0 1 2's complement of number 1 1 0 (101+1) Therefore 1010 is -6 In 4- bit representation, we have only three magnitude bits. So, The maximum "+ve" number is +7 "0111"



The minimum "+ve" number is 0 "0000" Similarly, The maximum "-ve" number is -1 "1111"

The minimum "-ve" number is -8 "1000" Therefore, The positive numbers are from 0 to7.

The negative numbers are from 0 to 8.

Truth table for 4-bit representation of numbers

Signed numbers 4 – bit binary number 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 -8 1000 -7 1001 -6 1010 -5 1011 -4 1100 -3 1101 -2 1110 -1 1111

Ex: (1) + 5 : 0 1 0 1 (2) + 7 : 0 1 1 1 (3) - 5 : 1 0 1 1 1 0 0 ( 1's complement of magnitude bits ) + 1 (adding one to get 2's complement) 1 1 0 1 (-5) (4) - 8 : 1 0 0 0 1 1 1 (1's complement of magnitude bits ) + 1 (adding one to get 2's complement) 1 0 0 0 (-8)

GENERAL 4-BIT ADDER/ SUBTRACTOR (A+B) OR (A-B)



• If we want to add A,B then it takes ADD = 0 and Cin =0 next 0 B = B then B Cin(0) = B. Therefore, the adder directly adds the A,B.

• If we want subtraction of A, B then it takes SUB = 1 and Cin =1. When SUB = 1, then SUB B = B * (complement of B) and Cin=1. So, when we add 1 to B' we get 2' s complement of B, that is "B", then the adder will adds the A and -B, so we get A-B.

• The circuit will gives adder as well as subtraction. • Since it is a 4- bit adder , it adds upto 15 only. If sum is greater than fifteen then it will not give and

appropriate answer. • Up to "BOX1" it gives only magnitude that is unsigned bit (i.e. it gives sum upto15). • If we consider the whole circuit then it gives the signed output. • If output is signed bit then it gives sum upto +7 only. • If sum is greater than '7' then it won't give exact answer.

BCD ADDER: • Consider the arithmetic addition of two decimal digits in BCD, together with a possible carry from a

previous stage. Since each input digit does not exceed '9', the output sum cannot be greater than 9 + 9 + 1 = 19, where '1' is the input carry.

• That is, if we apply to BCD digits to a four bit binary adder, the adder will from the sum in binary and produce a result that may range from 0 to 19.

TRUTH TABLE FOR DERIVATION OF A BCD ADDER



Decimal Binary sum BCD sum

Number C* S3* S2

* S1* S0

* C* S3* S2

* S1* S0

*

0 0 0 0 0 0 0 0 0 0 0

1 0 0 0 0 1 0 0 0 0 1

2 0 0 0 1 0 0 0 0 1 0

3 0 0 0 1 1 0 0 0 1 1

4 0 0 1 0 0 0 0 1 0 0

5 0 0 1 0 1 0 0 1 0 1

6 0 0 1 1 0 0 0 1 1 0

7 0 0 1 1 1 0 0 1 1 1

8 0 1 0 0 0 0 1 0 0 0

9 0 1 0 0 1 0 1 0 0 1

10 0 1 0 1 0 1 0 0 0 0

11 0 1 0 1 1 1 0 0 0 1

12 0 1 1 0 0 1 0 0 1 0

13 0 1 1 0 1 1 0 0 1 1

14 0 1 1 1 0 1 0 1 0 0

15 0 1 1 1 1 1 0 1 0 1

16 1 0 0 0 0 1 0 1 1 0

17 1 0 0 0 1 1 0 1 1 1

18 1 0 0 1 0 1 1 0 0 0

19 1 0 0 1 1 1 1 0 0 1

• Above table represents conversion binary sum to BCD sum.



• In this conversion, upto '9' the BCD number is same as the binary number.

• When the sum is greater than '9', we obtain non - valid BCD representation. so, the addition of binary 6 (0110) to the binary sum, converts it to the correct BCD representation and also produces an out put carry as required.

• The logic circuit that detects the necessary correction can be derived from the table entires.

The correction is needed when C* = 1 (or)

S*3 S

*2 =1 (or)

S*3 S

*1 = 1

Therefore, the Boolean function C = C*+ S*3 S

*2 + S*

3 S*1

• When C = 1, it is necessary to add 0110 to the binary sum and provide an output carry for the next stage.

DESCRIPTION ABOUT BCD ADDER

• BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD.

• BCD adder must include the correction logic in its internal construction.

• To add 0110 to the binary sum, we use a second 4 - bit adder.

• The two decimal digits, together with the input carry are first added in the top 4 - bit binary adder to produce the binary sum.

• When the output carry is equal to zero, nothing is added to the binary sum. When it is equal to one, binary 0110 is added binary sum through the bottom 4 - bit binary adder.

• The output carry generated from the bottom binary adder can be ignored, since it supplies information already available at the output carry terminal.

• The BCD adder can be constructed with three IC packages. Each of the 4- bit adder is an MSI function and the three gates for the correction, logic need one SSI package. However, the BCD adder is available in one MSI circuit. To achieve shorter propagation delays, an MSI BCD adder includes the necessary circuits for look - ahead carries.

• The adder circuit for the correction does not need all four full - adders, and this circuit can be optimized within IC packages.

THE CIRCUIT DIAGRAM OF BCD ADDER



NOTE : A decimal parallel adder that adds 'n' decimal digits need ' n' BCD adder stages. SUMMARY :

• Explanation about two's complement with examples.

• A 4 -bit representation of numbers.

• Design of 4 - bit adder / subtraction.

• Design of BCD adder.

MODULE – 14



ARRAY MULTIPLIER

ARRAY MULTIPLIER:

• It is a digital combinational circuit.

• It is used for the multiplication of two binary numbers by employing an array of full adders and half adders.

• This array is used for the nearly simultaneous addition of the various product terms involved. To form the various product terms, an array of ' AND' gates is used before the adder array.

• The main advantage of array multiplier over traditional bit serial multipliers is, it improves the speed.

BASIC THINGS TO SPEED UP ARE :

• Repeated addition - it is inefficient.

• Shift and add with a set of adders - we repeatedly do it.

• Shift and add several times - working all with same times.

DEFINITION OF ARRAY MULTIPLIER :

The circuit within do the "shift and add" all at ones is called as an array multiplier.

• It also called parallel multiplier.

• It takes array of adders.

EXAMPLES

(1) 2 - Bit array multiplier :



a1 a0 ------- multiplicand

b1 b0 ------- multiplier

a1 b0 a0 b0

a1 b1 a0 b1

p3 p2 p1 p0 ------- product

p0 = a0 b0

p1 = a1 b0 + a0 b1

p2 = a1 b1 + c1, where c1 = carry generator during the addition for p1 term.

p3 = c2 , where c2 = carry generator during the addition of p2 term.

LOGICAL DIAGRAM :

HA = half adder

pi = product terms ( i = 0,1,2,3 )



c = carry

s = sum

Ts = sum bit propagation time

Tc = carry bit propagation time

(2) 3 * 3 array multiplier

a2 a1 a0 ------- multiplicand

b2 b1 b0 ------- multiplier

a2 b0 a1 b0 a0 b0

a2 b1 a1b1 a0 b1

a2b2 a1b2 a0b2

p5 p4 p3 p2 p1 p0 product terms

p0 = a0 b0

p1 = a1 b0 + a0 b1

p2 = a2 b0 + a1 b1 + a0b2 + c1

p3 = a2 b1 + a1b2 + c2

p4 = a2b2 + c3

p5 = c4

where c1, c2, c3, c4 are carry generators during the addition for p1, p2, p3, p4 respectively.

LOGIC DIAGRAM :



Where

HA = half adder

FA = full adder

pi = product terms ( i = 0,1,2,3,4,5 )

c = carry

s = sum

Ts = sum bit propagation time

Tc = carry bit propagation time



(3) 4 * 4 array multiplier

a3 a2 a1 a0

b3 b2 b1 b0

a3b0 a2 b0 a1 b0 a0 b0

a3b1 a2 b1 a1b1 a0 b1

a3b2 a2b2 a1b2 a0 b2

a3b3 a2b3 a0b3 a0b3

p7 p6 p5 p4 p3 p2 p1 p0

Logic Diagram



For 2 * 2 multiplier (see ex :1)

Number of AND gates required are 2*2 = 4

Total number of adders required are (2-1) * 2 = 1 * 2 = 2

Numbers of 'HA' required are '2'

Numbers of 'FA' required are ' ( 2 - 2 ) * 2 ' = 0 * 2 = 2

Number of product terms = number of bits in multiplier * bit width of each partialproduct

= 2 * 2= 4

For 3 * 3 multiplier ( see ex 2)



Number of AND gates required are 3*3 = 9

Total number of adders required are (3-1) * 3 = 2 * 3 = 6

Numbers of 'HA' required are ' 3 '

Numbers of 'FA' required are ' ( 3 - 2 ) * 3 ' = 1 * 3 = 3

Number of product terms = number of bits in multiplier * bit width of each partial product

= 3 * 2

= 6

Similarly for m * n multiplier :

Number of AND gates = m * n

Total number of adders = ( m - 1 ) * n

Numbers of 'HA' = n

Numbers of 'FA' = ( m - 2 ) * n

Number of product terms = number of bits in multiplier * bit width of each partial product

Even through it improves the speed, still there is a level of delay invovled in an array multiplier before the final product is achieved. That is

For an " m * n" bit multiplier

Let Ta = AND gate propagation delay

Ts = sum bit propagation delay



Tc = carry bit propagation delay

Final product delay is

T ={Ta + [ (m-1) + (n -1) ] Tc , if Tc > Ts

Ta + ( m-1) Tc + ( n - 1 ) Ts, if Tc <Ts }

Ex : For 4 * 4 multiplier ( see ex 3)

The final product delay (T) = { Ta + 6 Tc , if Tc > Ts

Ta+ 3 Tc + 3 Ts, if Tc < Ts }

CONCLUSION :

Array multiplier is an electronic circuit used in digital electronics to multiply two binary numbers.

ADVANTAGE :

It improves the speed.

DISADVANTAGE :

Even though it improves the speed it has some propagation delay.

SUMMARY :

• Array multiplier definition

• Advantages and disadvantages of array multiplier.

• Examples of Array Multiplier.

• Knowledge about m * n array multiplier.

Module-15



INTRODUCTION TO SEQUENTIAL CIRCUITS

The digital circuits considered so far have been combinational, where the outputs are

entirely depends up on the current inputs. Although every digital system likely to have

combinational circuits, most systems encountered in practice also include storage

elements, which require that the system be described in terms of sequential logic.

In sequential circuits present output depends on present outputs and past outputs of

the system where as in combinational circuits output is influenced only by present

inputs. This is the difference between combinational circuits and sequential circuits.

There are two main types of sequential circuits and their classification depends on the

timing of their signals. A synchronous sequential circuit is a system whose behavior can

be defined from the knowledge of its signal at discrete instant of time. The behavior of

an asynchronous sequential circuit depends upon the input signals at any instant of time

and the order in which the inputs change. The storage elements commonly used in

asynchronous sequential circuits are time delay devices. Thus, an asynchronous

sequential circuit may be regarded as a combinational circuit with feedback. Because of

the feedback among logic gates, an asynchronous sequential circuit may become

unstable at times.

A synchronous sequential circuit employs the signal that affects the storage elements

only at discrete instant of time. Synchronization is achieved by a timing device called a



clock generator. That provides a periodic train of clock pulses. The clock pulses are

distributed throughout the system in such way that storage elements are affected only

with arrival of each pulse.

LATCHES

The basic storage (memory) elements are latches. The latches introduced here basic

circuits from which all flip-flops are constructed. Although latches are useful for storing

binary information and for the design of asynchronous sequential circuits, they are not

practical for used in synchronous sequential circuits.

SR LATCH

The SR latch is a circuit with two cross-coupled NOR gates or two cross coupled NAND

gates. It has two inputs labeled S for SET and R for RESET. In digital language SET

means output is ‘1’ and RESET means output is ‘0’. This latch has two useful states.

When the output ‘Q=1’ and ’QI=0’, is said to be SET. When the output ‘Q=0’ and ’Q

I=1’,

is said to be RESET. The each outputs Q and QI are normally the complement of each

other. How-ever when both inputs are equal to 1 at same time, an undefined state with

both outputs equal to ‘0’ occurs.

When S=0 and R=0 the outputs are depends upon previous output of Q and QI. it is

called memory state.



When S=1 and R=0 the outputs Q=1 and QI=0 respectively it is called SET state.

When S=0 and R=1 the outputs Q=0 and QI=1 respectively it is called RESET state.

When S=1 and R=1 the outputs are ‘0’. it is called invalid state. Because of Q and QI

should be complement to each other.

THE NAND GATE VERSION OF SR LATCH

FLIP-FLOPS

A flip flop circuit can maintain a binary state indefinitely (as long as power is delivered to

the circuit) until directed by an input signal to switch states. The major differences

among various types of flip-flops are in the number of inputs they posses and the

manner in which the inputs effect the binary state.

SR FLIP-FLOP

The operation of the basic flip flop can be modified by providing additional control input

that determines when the state of the circuit is to be changed. An RS flip-flop with a

clock pulse (cp) input is shown.


Rajiv Gandhi University of Knowledge Technologies

The pulse input acts as an enable signal for the other two inputs.

Let us assume previous output is zero for starting time. At t

until t2 and now cp=0 means it

get output as 1 we have to supply two inputs S and

we have another flip-flop called D



The pulse input acts as an enable signal for the other two inputs.

Let us assume previous output is zero for starting time. At t1 cp and S=0 and R=1 so Q=0

and now cp=0 means it assigns its previous state i.e. Q as 0. In this SR flip

supply two inputs S and R as 1,0 respectively. To avoid this

flop called D-flip-flop.


Sk.Riyaz Hussain

cp and S=0 and R=1 so Q=0

Q as 0. In this SR flip-flop to

R as 1,0 respectively. To avoid this



When clk =1

If S=1 and R=0 the outputs Q=1 and QI=0 respectively.

If S=0 and R=1 the outputs Q=0 and QI=1 respectively.

When clk =0, it gives the previous output and it is known as memory state.

The D-flip-flop can be shown as

Generally flip-flops can perform following operations:

1. SET operation

2. RESET operation

3. MEMORY operation

4. TOGGLE operation

All these operations can be performed by JK-flip-flop. Before going to JK-flip-flop, let us

look at this special or modified SR-flip-flop.



Toggle means complement of previous outputs. Here one disadvantage that is while S, R

and clk are at logic level 1 , it gives output Q ,QI, Q ,Q

I, Q ,Q

I............ and this

phenomenon is called RACING.

In previous case this logic condition(S=R=1) is unpredictable and now it is predictable,

but not useful.

Changing states from Qn to Qn

I or Qn

I to Qn is known as toggling and when this happens

continuously it is called Racing.

• Race is uncontrollable

• Toggle is controllable

If we can control racing phenomenon then it is useful. It can be done by restricting the

output to clock periods means the output is effected by inputs only once at a clock

period.

If clock on time < propagation delay of flip-flop then racing can be avoided.

Digital Electronics Concepts

Engineering

Transcript of Digital Electronics Concepts