Digital Electronics and Computer Organization Digital Design … Materils for Digital... ·...
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CKV Digital Electronics and Computer Organization Lecture 16 : D-Latches and D-Flipflops Digital Design 10/1/2020 1
Transcript of Digital Electronics and Computer Organization Digital Design … Materils for Digital... ·...
CKV
Digital Electronics and Computer Organization
Lecture 16 : D-Latches and D-Flipflops
Digital Design
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CKV
Latches
SR Latch with Enable
S’R’ Latch
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CKV
Latches
D Flip-flop circuit
S’R’ Latch
SR Latch with Enable
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CKV
Latches
D Latch with Enable
En D Q Q’
X Q Q’
0 0 1
1 1 0
Reset
No change0
1
1 Set
D = 0 makes S = 0 and R = 1
D = 1 makes S = 1 and R = 0
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CKV
Latches
D Latch with Asynchronous PRESET and CLEAR
Activating PRESET’ (i.e. 0) makes Q=1. This in turn maintains Q’=0
Activating CLEAR’ (i.e. 0) makes Q’=1. This in turn maintains Q=0
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CKV
Latches
SR Latch S’R’ Latch D Latch
Graphic Symbols
S
R
Q
Q’
S
R
Q
Q’
D
En
Q
Q’
Pr’
Cr’
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Latch – Responds to change in level of clock pulse
Sequential Circuits
The key to the proper operation of a flip flop is to trigger itonly during signal transition.
CKV
Race around in Latches
D Latch
D
En
Q
Q’
Pr’
Cr’
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XnYn = Xn . Xn-1
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Flip-Flops
Two ways to build a flip flop
Special configuration of two latches to isolate the output of flip-flop
Gate based design which triggers only during signal transition ofclock and is disabled during rest of clock pulse
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CKV
Master Slave Flip-flop
Edge Triggered D Flip-Flops
If D changes
Y will be affected and not Q
If D changes
Y remains unaffected and Q stable
1
1 2
2
Y passed to Q
-ve Edge Triggered
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CKV
Master Slave Flip-flop
Edge Triggered D Flip-Flops
1 2
CLK
D
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CKV
Master Slave Flip-flop
Edge Triggered D Flip-Flops
CLK
D
Y
Q Negative Edge Triggered
S’R’ Latch
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CKV
D-type positive edge triggered
Edge Triggered D Flip-Flops
B
ACase I:
CLK = 0
S = 1, R = 1 for S’R’ latch
Hence Previous state of Q and Q’ is maintained
CLK = 0 => S=1, R=1
D = 0 ->1 -> 0
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D-type positive edge triggered
Edge Triggered D Flip-Flops
B
A
S’R’ Latch
Case 2:
CLK = 1 , D=0, S=1, R=0B=1, A=0
D -> 0 -> 1 -> 0 B =1 Since R=0
0
0
Hence Initial state of Q and Q’ is maintained
Case 3:
CLK = 1 , D=1, S=0, R=1B=0, A=1 D -> 1 -> 0-> 0 B -> 0-> 1> 0 R=1 Since S=0A=1 Since S=0
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D-type positive edge triggered
Edge Triggered D Flip-Flops
B
A
S’R’ Latch
Case 4:
CLK = 0 , D=0, S=1, R=0B=1, A=1, Q=0
D ->1B=0
0
0
CLK->1R=1A=1S=0Q=1
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D-type positive edge triggered
Edge Triggered D Flip-Flops
Thank You
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