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IP CoresIP CoresIP CoresIP Cores

ASIC DESIGN USING FPGA

BEIT VII

KICSIT

2012 Lecture 26-27

2012 Lecture 26-27 2

Intellectual Property (IP)Intellectual Property (IP)

• It would be waste of time, if a digital engineer were to code an adder or create a cosine lookup table each time.

• it would be reinventing the wheel and a waste of their time

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Intellectual Property (IP)Intellectual Property (IP)

• Similarly, continually re-code commonly used complex digital circuits in large projects is just wasting more time and money.

• Because of this, a digital design engineer may just use an IP core.

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Intellectual Property (IP)Intellectual Property (IP)

• An IP (Intellectual Property) core is a block of HDL code that other designers have already written to perform a specific function.

• IP cores can be used in a complex design where a designer wants to save time.

• Examples of IP cores may be RS232 Serial Port, Graphic LCD controller, PCI Interface, I2C controller, Microprocessor core etc.

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Intellectual Property (IP)Intellectual Property (IP)

• IP cores in the electronic design industry have had a profound impact on the design of systems on a chip.

• IP cores for standard processors, interfaces, and internal functions have enabled chip makers to put more of their resources into developing the differentiating features of their chips.

• As a result, chip makers have developed innovations more quickly.

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Intellectual Property (IP)Intellectual Property (IP)• The licensing and use of IP cores in chip design came

into common practice in the 1990s.

• There were many licensors and also many foundries competing on the market.

• Today, the most widely licensed IP cores are from MIPS Technologies and ARM Holdings.

• A number of organizations, such as the Free IP Project and Open Cores, have formed to promote open sharing of IP cores

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Advantages and Disadvantages of IP CORESAdvantages and Disadvantages of IP CORES

• As with any other engineering tool, IP cores have their advantages and disadvantages.

• Although they may simplify a given design, the engineer has to design the interfaces to send and receive data from this “black box”.

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Advantages and Disadvantages of IP CORESAdvantages and Disadvantages of IP CORES

• So many IPs are designed for particular parts and some come free but other cores may cost you thousands of dollars.

• While an IP core may reduce design time, the engineer frequently has to pay for the right to use the core.

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Types of IP CORESTypes of IP CORES

• IP cores fall into one of three categories: hard cores , firm cores , or soft cores

• Hard cores are physical implementation of the IP design.

• These are best for plug-and-play applications, and are less portable and flexible than the other two types of cores

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Types of IP CORESTypes of IP CORES

• Firm (sometimes called semi-hard ) cores, like Hard cores, also carry placement data but are configurable to various applications.

• Soft cores, the most flexible of the three, exist either as a netlist (list of the logic gates and associated interconnections making up an integrated circuit) or hardware description language ( HDL ) code.

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Xilinx Core Generator Xilinx Core Generator

• The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx® FPGAs.

• It provides you with a catalog of ready-made functions ranging in complexity from simple arithmetic operators such as adders, accumulators and multipliers, to system-level building blocks such as filters, transforms, FIFOs and memories.

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Xilinx Core GeneratorXilinx Core Generator

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Starting the CORE Generator from Xilinx ISEStarting the CORE Generator from Xilinx ISE

• Start by creating a project.

• Launch the Xilinx ISE software.

• Once the Project Navigator window opens, create a new project by clicking on the File drop-down menu, and selecting New Project.

• Finish creating your project and proceed to double click on Create New Source in the Processes window.

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Starting the CORE Generator from Xilinx ISEStarting the CORE Generator from Xilinx ISE

• Choose IP and name the file ‘add_sub’.

• In the next screen open the tree to Math Functions => Adders & Subtracters => Adder Subtracter v7.0 as shown in the image below. Click Next and Finish.

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Starting the CORE Generator from Xilinx ISEStarting the CORE Generator from Xilinx ISE

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Starting the CORE Generator from Xilinx ISEStarting the CORE Generator from Xilinx ISE

• After a few seconds a new window (LogiCore) should pop up.

• Select the options to match those in Fig. 2 and Fig. 3. Select Next on Fig. 2, and Generate on Fig. 3.

• The window will disappear and will have created an Adder/Subtracter that operates on two four-bit numbers.

172012 Lecture 26-27

•Fig. 2. First page of the LogiCore Window

•Fig. 3. Second page of the LogiCore Window

Starting the CORE Generator from Xilinx ISEStarting the CORE Generator from Xilinx ISE

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Starting the CORE Generator from Xilinx ISEStarting the CORE Generator from Xilinx ISE

• It will take a few moments to generate all of the files.

• Progress made can be seen by looking at the messages in the Transcript window.

• When it is finished, add_sub will be shown in the sources window inside the Project Navigator.

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Starting the CORE Generator from Xilinx ISEStarting the CORE Generator from Xilinx ISE

• Now Go to File, click on Open, and browse to “add_sub.v”.

• This will bring up one of the files created by the CORE Generator System.

• There is some information in it that needs to be copied from the file.

• Now, click on the New icon to create a new Verilog file. Enter the code in the file. Copy it and Save it into the Verilog Source.

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Starting the CORE Generator from Xilinx ISEStarting the CORE Generator from Xilinx ISE

• After Saving the file as “adder_subtracter.v” add it to your project as an existing source.

• Now Synthesize the file.

• If everything was done correctly, it should synthesize without errors.

• If there are any warnings, ignore them for now, and in the case that there are errors review the code.