Digital DCDC control with sliding mode controlBruno Andre Marcal Jacinto

Instituto Superior TecnicoLisbon, Portugal

bruno.jacinto@ist.utl.pt

Abstract—This work proposes a digital implementation ofthe Sliding Mode Control law in a DC-DC buck converter.The control law is implemented monitoring only the DC-DC output voltage, and is capable of producing a maximumovershoot/undershoot of 50 mV for load transients from 0A to 1,5 A and vice versa, for reference voltages of 1 and1,5 A. For line transients the DC-DC converter produces noovershoot/undershoot. Several results are present in Matlab withthe continuous control law and in HSim with the digital controllaw implementation.

The ADC is implemented using a current controlled delay linethat generates the error voltage for any input voltage from 1 Vto 1,5 V.

The ADC and the control law where designed using CMOStechnology AMS C35B4 (0.35µm) .

I. I NTRODUCTION

There are several DC-DC converters topologies, they canbe linear, like an LDO, or non-linear, for example an Buckconverter. The topologies used will vary depending of therequirements, application and current that need to be deliveredby the converter to the load.

The current required by the load isn’t constant and that willhave influence on the output voltage. In order to maintain aconstant supply voltage at the output the converter needs acontrol law. There are several control laws that can be used tointroduce negative feedback and maintain the output voltageconstant, like PD, PI, PID[1],V 2 [2], Sliding Mode Control[3] and they can be applied as an analog circuit or digitalcircuit. For this work will be used the buck converter presentin Figure 1.

Fig. 1. DC-DC buck converter

The buck converter is controlled with Sliding Mode Controland works at CCM and DCM depending on the values.

The use of the Sliding Mode Control to control the buckconverter has the advantage of being a Variable StructureControl that produces a discontinuous signal to control the

system. The control signal produced have two possible statesrequired by DC-DC converter and is advised to discontinuouscontrolled systems. Sliding Mode control is also a robustcontrol approach. This property allow it to deal with theinaccuracies of the system and achieve the desired state init’s presence.

II. A NALOG SLIDING MODE CONTROL

It is possible to obtain the SMC law based on the transferfunction of the system or on the state space equations. In thiswork the state space method will be used to achieve the SMClaw.

Let us consider the following control system of equation(1) where x∈ ℜ is the system state vector,µ is the inputsignal applied to the system where A and B are the systemand control matrices and the pair (A,B) is assumed to be fullcontrollable.

x = Ax(t) +Bµ (1)

The objective of any control law is to achieve a definedequilibrium point and remain there for any initial conditions.Usually, the equilibrium point is defined as the differencebetwen the output of the system and a reference signal (xREF ),the value for which we want the system to converge to. Whenthe system achieves the equilibrium pointxREF , the differencebetween the reference signal and the system state space outputwill be zero and it is given by:

x = x− xREF (2)

If we manage to control the desired state space variable, sothat the control can achieve a well known value and remainin that value, the expression which allows this to happen iscalled sliding surface. The system will start from any pointand when it reaches the sliding surface it will remains thereuntil the equilibrium point is achieved.

Let’s define the sliding surface as:

S(t) = x|s(x, t) = 0 (3)

The expression of s(x,t) must be chosen in order to beexponentially stable[4].

There are several ways to obtain this expression, one is touse a PID controller as sliding surface s(x,t), on alternative isthe following equation. The equation must be choose in orderto lead the error value to zero.

S(x, t) = (d

dt+ δ)n−1x(t), δ > 0 (4)

In eq. (4) the constantδ is the bandwidth of the system. Withthis control law the error will converge to zero exponentially.

Applying (4) to the DC-DC converter the control law isgiven by:

S(x, t) = (d

dt+ δ)x(t) =

dx(t)

dt+ δx(t) (5)

Eq. (5) is equivalent to an Proportional Derivative (PD)controller.

The objective of the control law is achieve the desiredstate only monitoring the output voltage, then lets define thefollowing state space variables:

x =

[x1

x2

]=

[vovo

](6)

In eq.(6)vo is the output voltage andvo is it’s derivative.Writing the system equations to obtain the system matricesfrom equation 1 for the buck converter, it can be writen as:

vo = vovo = vin

LC− vo

LC− 1

RCvo

(7)

Eq. (7) in matricial form are presented in eq. (8).[vovo

]=

[0 1

− 1LC

− 1RC

] [vovo

]+

[01

LC

]VINµ (8)

The Sliding Mode Control law from equation (5) applied tothe DC-DC converter is given by:

S(x, t) =dvodt

+ δ(vo(t)− VREF ) (9)

Since δ represents the bandwidth of the system and theobjective is to obtain the output voltagevo switched by thecontrol at a frequency of 2 MHz. The value ofδ will be δ =2 · 106.

With equation (9) it is possible to manage the switchingstates provided by the Sliding Mode Control law. The slidingsurface is represented in Figure 2 and for any initial conditionthe system will converge to the desired equilibrium state. Theswitching states are given by:

µ =

1 , s(x, t) = dvo

dt+ δ(vo(t)− VREF ) < 0

0 , s(x, t) = dvo

dt+ δ(vo(t)− VREF ) ≥ 0

(10)

However, if considering the control law behaviour as ideal,when the control reaches the sliding surface, theµ signalswitches theoretically at infinite frequency. This phenomenonis called chattering. For example, in DC-DC converters, thesystem supplies a load. This load, if the inductor and capacitorare ideal components, will impose variations in the outputvoltagevo as the LC filter charges/discharges. To compensatethis changes the control needs to switch between states sothat it can converge to the desired solution. Another cause forchattering are the non-idealities of the system. For example,discontinuities invo generate infinite derivative terms on the

Fig. 2. Sliding Surface for equation (9)

sliding surface leading to infinite frequency switching. Thisinfinite frequency switching also leads to high losses becausethe power switches of the DC-DC converter are not ideal,producing losses at a rate ofP ∝ V ·f2 W due to the requiredcharge and discharge of the MOS gates.

The solution to limit the frequency is to introduce hysteresisin the sliding surface. The hysteresis will limit the switchingfrequency since the control will not switch in the sliding plane,but near it. Figure 3 shows the sliding mode control behaviourwith hysteresis control from the following equation:

µ =

1 , s(x, t) = dvo

dt+ δ(vo(t)− VREF ) < BMinus

0 , s(x, t) = dvo

dt+ δ(vo(t)− VREF ) > BPlus

µ , others(11)

Fig. 3. Sliding Surface for equation (9) with hysteresis

However, there is still the problem caused by the disconti-nuities of the output voltagevo. To solve this issue, an analogfilter is needed to reconstruct the ideal signal from the circuitwith non-idealities. Since the system is a second order system,the filter order must be a second order filter with bandwidth, atleast, of the switching frequency of the DC-DC converter. Theuse of a 1st order filter can also be possible. However, the wavereconstructed is a linear wave and doesn’t correspond to the“ideal” second order behaviour of the system. The maximumbandwidth required for the filter depends significantly fromthe influence of the non-idealities. Figure 4 shows the blockdiagram of the analog system with the low pass filter.

The use of the filter is mandatory if considering the imple-mentation of the control in an ideal system. However, when

Fig. 4. System block diagram with the low-pass filter

we implement the control law with electronic circuits, the useof this filter can be avoided. This happens because electroniccircuits that perform the control law have a filter associatedto its function because they are not ideal and consequentlythey are limited in frequency response to the discontinuitiesgenerated on the signal. This would allow the effect of thefilter without implement it directly on the design.

Using equation (11) the values forBMinus and BPlus

for L=1µH and C=25µF (values obtained by simulationthat perform a load transient with less than 50 mV under-shoot/overshoot) for an load of 1.5 A are:

TABLE IVALUES OFBMinus AND BPlus FOR THE REFERENCE VOLTAGES OF1 V

AND 1.5 V AND SWITCHING FREQUENCIES OF2 MHZ AND 3.3 MHZ

f=2 MHz f=3,3 MHzVREF (V) BMinus BPlus BMinus BPlus

1 4, 53.106 −6, 30.106 −1, 33.103 −1, 961, 5 2, 53 2, 01.103 2, 53 1, 20.103

As it can be seen in table I, at switching frequency of 2MHz the system is not realisable for a reference voltage ofVREF = 1 V, becauseBMinus > BPlus. For a switchingfrequency of 3.3 MHz the system is realisable for both refer-ence voltages. However, the values differ from one to another.Since forVREF = 1 V the reference voltage requires a smallerduty cycle and generates an higher overshoot/undershoot. Thevalues used by the control law will be:

BMinus = −1, 33.103

BPlus = −1, 96(12)

III. I MPLEMENTATION

A. LC Filter Values

The values for the L C filter where previous indicated insection II. However this values are ideal and don’t have thenon-idealities associated.

Then in table II are present the values for the LC filter withthe non-idealities.

TABLE IIDC-DC LC FILTER VALUES

Element Value UnitCapacitor

C 25 µFLC 2,5 nHRC 12,5 mΩ

InductorL 1 µHRL 4,5 mΩ

IV. D IGITAL SMC LAW

The implementation of the digital Sliding Mode Controlshould preserve the behaviour of the analog Sliding ModeControl law. However, since the digital control law is ansampled system, the error either due to A/D converter preci-sion errors nor to the delay introduced between 2 consecutivesamples, will have influence in the circuit. This happensbecause the control law will not switch in the real value, butwill switch in the nearby value influencing the output voltageand circuit response. Figure 5 shows the analog response anddigital response if the switching values are influenced by thesampled period and error quantization.

Fig. 5. Comparasion betwen the analog and Digital Sliding Mode ControlLaw with the error introduced by digitalization of the signal

There is also the problem of the A/D converter will notcover all the DC-DC output voltage. Then to cover the majorpart of the output voltage values the Sliding Mode Controllaw will be separated in transient and steady-state regions.

A. Steady-state Sliding Mode Control law

The steady-state SMC is implemented by reformulating theanalog control law into it’s digital equivalent. The reformulatedcontrol law for steady state region obtained from equation 11is given by:

Bn = (Von − VREF ) · δ +∆V

∆t(13)

In eq. (13)∆V and∆t represent:

∆V = Von − Vo(n−α)

∆t = tn − tn−α

∆t = α · TS

(14)

In (14) TS represents the sampling frequency andα thenumber of clock cycles between the actual sample and theprevious sample that is used to implement the derivativepart. Since∆t is a constant value, andδ is also a constant

and represents an higher value thenBPlus andBMinus, theequation (13) can be rewritten as:

Bn

δ= (Von − VREF ) +

∆V

δ ·∆t(15)

orBn ·∆t = (Von − VREF ) · (δ ·∆t) + ∆V (16)

Both equations are quite similar. The difference is thatthe proportionality constant will multiplies the difference ofthe output voltages of the derivative term in (15), increas-ing/decreasing the quantization error at the proportionaltermif δ ·∆t is less/greater than 1. In (16), ifδ ·∆t is less/greaterthan 1, the quantization error will decrease/increase. Thenin order to maintain an similar precision in the derivativeand proportional term (not given too much importance toone term), the value ofα that represents the amount ofclock cycles from the actual sample and previous sample toemulate the derivative term can take several values. The typicalimplementation of the derivative term is usually done withα = 1 [5]. However this is not possible in this circuit.

The value ofα = 1 will not be used because with thisvalue, due to the nature of the system it will only give theinformation if von is increasing/decreasing and the system willnot converge becauseδ ·∆t = 1

16 . This value introduces allotof error in equation (15) and the system wouldn’t converge tothe required equilibrium point

The values ofα where obtained by experimentation. Severalvalues ofα where experimented in order to achieve a goodconvergence the valueα = 8 produced a balanced solutionbetween delay and error.

Therefore using the values of 12 withα = 8, the values ofBPlus andBMinus are given by:

BMinus = −665.10−3 ≈ 0BPlus = −980.10−9 ≈ 0

(17)

The values are almost zero because the ADC will only allowto distinguish from error voltages greather than 1 mV. As aconsequence, when the control law produces a zero value, theoutput will be equal to the last value.

B. Transient Sliding Mode Control law

The transient region is implemented for output voltagesbetween 0 andVREF − ∆VErrorADC

2 , where∆VErrorADC isthe voltage bandwidth for the steady ADC. For this region itis expected that the output voltage increases to reachVREF .However, the voltage increase needs to be controlled in orderto produce an small overshoot and reduce the current requiredduring transient state to achieve the desired output voltage.

The control for this region looks for the change in the outputvoltage each 16 clock cycles. If the difference between theactual value and the previous value is less than 3, the controlwill turn the DC-DC in the ON-State. If the difference is equalto 3, the actual state is maintained. Otherwise the control willturn into OFF-State. To help with the convergence, if duringthe 16 clock cycles the difference voltage drops bellow 0,

Fig. 6. Digital Sliding Mode Control Law

the control law will put the DC-DC automatically at the ON-State. After 16 clock cycles, the output voltage could dropsignificantly, and would take more time or even could not beable to converge to the desired value.

For output voltages greater thenVREF + ∆VErrorADC

2 thecontrol law will always be at Cut-OFF state, and there is noneed to treat this region.

However this block isn’t fully functional due to the lackof precision of the ADC in the transient regime. There whereobtained good transient results (Overshoot less than 200 mV),however they depend on the load and dont’t accomplish themaximum overshoot that is 50 mV. The block has been left inthe circuit because it helps to achieve the steady state regimeand for power analysis, the digital gates used will influencethecircuit. The delay line for this A/D conversion is shut-downwhen the control achieves the steady-state regime in order toreduce power consumption.

The block diagram that implements the digital Sliding ModeControl law in both regions is present in figure 6.

Figure 7 shows the block diagram for the implementationof the digital Sliding Mode Control Law.

Fig. 7. Digital control law

However even using an higher value ofα it is still possibleto occur high frequency transitions, so in order to limit thefrequency of the signalµ is proposed an circuit to limitthe switching frequency of the control. Figure 8 shows the

Fig. 8. Digital control law

implementation of the circuit.The circuit is based on the actual value and the previous

two last samples. If the signalµ switches and in the nextclock cicle receives the order to switch to the older value, thisblock will maintain the actual control output. If theµ have thesame value for at least two clock cycles, the circuit will allowthe output to be switched. The maximum switching frequencywith this block will befcontrol/4, since when a change occurs,unless the control is constant for at least two consecutive clockcycles, the output will not switch.

V. A/D CONVERSION USING ANDELAY LINE

The use of A/D converters is crucial when we implementan digital control in order to interact between the analog anddigital world. Since the signal that is being processed is analog,the ADC will convert the analog value into an digital value.

In this work the A/D conversion will be implemented usingan delay line. The delay will be controled with a voltagecontrolled current source to achieve the precision and powerrequirements.

A. Proposed A/D Conversion

The proposed A/D converter uses an delay line that receivesa certain signal and generate the same signal delayed for acertain amount of time. The value of delay produced will beused to make the Analog to Digital conversion and has differ-ent values for different input currents using the approximatedequation (18) [6]. The different delay values will be detectedusing Flip-Flop D in each inverter working as a phase detector.The digital word produced will correspond to a certain inputcurrent. In this work is used the current to control the delayof equation (18).

tpINVLH,HL= C

VPlus

iDN |av

(18)

In eq.(18) the variableCtot is the total capacitanceof the inverter including the the input and output loadcapacitances.iDN (0) andiDN (tpLH,HL) are the saturation andtriode current of the inverter at the specified time instants. Formore extensive analysis of the delay can be consulted [7].

Using the current (eq. (18)) to control the delay of the ADCinverters, the ADC schematic with current control is present inFigure 9 for the steady-state region. In Figure 10 is presentedthe schematic for the transient region. This separation happensbecause, at steady state we are interested in the error voltage

Fig. 9. A/D Converter with automatic voltage control for steady state region

for a defined reference voltage and in transient region the ADCmust cover all the values from 0 V toVREF .

The left side of figure 9 will be responsible for generatingthe gate voltageVPOLAR to be applied to the right side of thecircuit responsible for the conversion of the input voltagevalimto the digital value corresponding to the difference betweenVREF −Valim. The current mirror ratios allow the gain controlof the delay. If the ratio increases, the precision of the ADCalso increases. Another way to control the precision is changethe reference frequency. Increasing/decreasing the referenceswitching frequency will decrease/increase the precisionof theADC, but will increase/decrease the number of samples persecond and would require less/more inverters in the delay line.

Fig. 10. A/D Converter for transient region

For the transient region the circuit will be implemented withthe resistor current source (Figure 10)to cover the maximumvalue of input voltage ranges. In a future work the ADC forthis region will be improved.

In both circuits there will exist a coder circuit that willconvert the digital word into a known value. The values needto be coded with the value that corresponds to output voltage.

TABLE IIIPARAMETERS FOR THEA/D CONVERTERS

DimensionsElement W(µm) L(µm) Others

Delay lineInverters

NMOS 0,4 0,35 -PMOS 0,4 0,35 -

Level ShifterMP0 0,4 0,35 -MP1 0,4 0,35 -MP2 1 0,35 -MP3 1 0,35 -MN0 2 0,35 -MN1 2 0,35 -

A/D converter for transientCurrent Source

MP0 1,5 1 -MP1 1,5 1 -R0 - - 1 MΩ

M - - 2A/D converter for steady-state

Current SourceMP0 1,5 1 -MP1 1,5 1 -MN0 0,5 1 -

M - - 40Transistor Remove

MN0 0,35 10 -VREF Control

R0 15 MΩ

R2 15 MΩ

C4 10 pF

The values used by the ADC will have a certain delay. Ifwe neglect the response time of the current source for changesin the input voltage, the delay of the circuit will be dominatedby the propagation of the reference signal from the delay lineto the digital word after codded. This delay will be a multipleof the reference clock frequency. To propagate the signal willbe need:

• 1 clock cycle to propagate the reference signal from thedelay line to the entrance D of the FF.

• 1 clock cycle to generate the digital word at the FF-D.• 1 clock cycle to convert the digital word into the respec-

tive value

The delay from the current source has not been parametrizedbecause it would require complex analysis such as slew rateand time response for small and large input signal changes,but unless the input voltage suffers an big change (at least 500mV) the converter will track the analog value to the digitalvalue.

For simulation purposes the dimensions for the elements ofthe A/D converters are present in table III.

VI. A NALYSIS & RESULTS

A. A/D Converter

The A/D conversion is an important element when it comesto digital circuits. The use of the ADC is mandatory tointeract the digital world with the analog world, howeverit’s functionality consumes energy. To an efficient energy

management is required that the ADC should consume theminimum possible energy to perform it’s operation so it can’tdegrade allot the efficiency of the circuit.

The ADC designed at the steady-state region from figure 9have an average precision of∆VS = 1, 08 mv and it allowsan error voltage band of∆VErrorADC = 108 mV. The ADCuses 100 inverters in the delay line and works at a frequencyof 33 MHz. Figure 11 shows which inverter corresponds toa defined input error voltage, assuming no influence from thelevel shifter.

Fig. 11. Input error voltage and inverters required for an frequency of 33MHz

The current and power requirements for the A/D conversionby the relevant elements (level shifter, current mirror andcurrent remove)is present in table IV . As can be seen the

TABLE IVADC POWER CONSUMPTION AND INFLUENCE OF EACH BLOCK ON THE

CIRCUIT

Input Cur-rent (mA)

Power (mW) Sub-Influence(%)

Influence (%)

MN0(CurrentRemove)

0,01 0,03 1,19 0,41

CurrentSources

0,13 0,44 16,41 5,74

LevelShifters

0,68 2,23 82,40 28,82

SubTotal 0,82 2,70 100 34,97

FF-D andSmall coder

1,53 5,04 100 65,03

SubTotal 1,53 5,04 100 65,03

Total 2,35 7,74 - 100

elements responsible for the major power consumption arethe Flip Flops and the small coder responsible for generatingthe equilibrium point with 65,03%, and the level shifter with28,82% from the total power consumption of the ADC.

B. Line transient

In this were where considered the line transient from 2,5 Vto 3,3 V and 2,5 V to 3,6 V and vice versa, for an load of

1,5 A that are present in Figure 12 and 13 for the referencevoltages of 1 V and 1,5 V.

Fig. 12. HSim Line transient simulations forVREF = 1 V, ILOAD = 1, 5A for load transients from 2,5 V to 3,3 V and 2,5 V to 3,6 V

As can be seen the output voltage produced don’t have anyrelevant overshoot/undershoot value. The only change is intheaverage value of the output voltage like in line regulation (aswill be explained in VI-D). This is an direct effect from thecontrol law. Since the output produced is the signal that willbe applied to both switches and not a PWM signal, when aline transient occurs, the output produced will respond almostinstantaneously to the line transient, changing the “duty cycle”of the wave produced.

C. Load transient

In this section where made load transients for the referencevoltages of 1 and 1,5 V and input voltages of 2,5 and 3,3.There where made the load transient from 0,15 A to 1,5 A andvice versa present in Figures 14 and 15 using HSim simulator.In table V are present the relevant results for Load Transientusing HSim and Matlab/Simulink, including the load transientfrom No Load (0 A) to full load (1,5 A).

As can be seen in the table the maximum load transientrequirement for 1 V and 1,5 V from maximum load to noload is achieved with an ripple less then 50 mV for anyreference voltage. In the load transient from 0,15 A to 1,5 Athe undershoot for 1,5 V reference voltage and supply voltageequal to 2,5 V is 51,8 mV. This is slightly larger then the

Fig. 13. HSim Line transient simulations forVREF = 1, 5 V, ILOAD =

1, 5 A for load transients from 2,5 V to 3,3 V and 2,5 V to 3,6 V

Fig. 14. HSim simulations forVREF = 1 V with load transitions from 0,15A to 1,5 A (and vice versa) for DC-DC supply voltages ofVIN = 2, 5 andVIN = 3, 3

Fig. 15. HSim simulations forVREF = 1, 5 V with load transitions from 0A to 1,5 A (and vice versa) for DC-DC supply voltages ofVIN = 2, 5 andVIN = 3, 3

requirement and is a direct effect from an Off-State that isgenerated during 90 ns while the output voltage drops. Thisdecision is an error from the ADC, because when the loadtransient happens, the spike generated is reflected in the ADC,generating a wrong value. However due to it’s small difference(1,8 mV) from the desired value of 50 mV, this value can benegleted.

The settling time of the circuit is also significant. For a Loadreduction by 1/10 the circuit responds in5, 51 µs.

D. Line Regulation

The results analysis for the DC-DC converter when chang-ing the input voltage to produce the same output voltage iscalled line regulation. In this thesis the main objective istoproduce an DC-DC converter that can receive input voltagesfrom 2,5 V to 3,6 V and produce the required output voltage(1 V to 1,5 V) for loads from 0 A to 1,5 A. In this thesiswent further and found its operation, wherever possible, forinput voltages from 1,8 V. Figures 16 and 17 show the averageoutput voltage obtained for the reference voltages of 1 V and1.5 V to the line regulation range.

TABLE VLOAD TRANSIENT RESULTS

VREF =1VParameter VIN Iload Mathlab/

Simulink R©Hsim

Overshoot/Undershoot Peak(VREF −vout)time

2,5

0 to 1,5 1,2 1,5441,5 to 0 1 1,307

0,15 to 1,5 1,3 1,051,5 to 0,15 0,9 1,169

3,3

0 to 1,5 1,4 1,6171,5 to 0 1,4 1,362

0,15 to 1,5 1 1,3521,5 to 0,15 1,2 1,788

Overshoot/Undershoot(VREF − vout)

2,5

0 to 1,5 19,6 29,781,5 to 0 43 47,18

0,15 to 1,5 26,6 29,841,5 to 0,15 32 37,19

3,3

0 to 1,5 20,8 23,861,5 to 0 39 49,78

0,15 to 1,5 17 32,861,5 to 0,15 41 37,58

Establishmenttime (1,5%)

2,5

0 to 1,5 0,5 2,1491,5 to 0 N/A N/A

0,15 to 1,5 2 2,1151,5 to 0,15 3,7 5,51

3,3

0 to 1,5 0,3 0,5481,5 to 0 N/A N/A

0,15 to 1,5 1,4 21,5 to 0,15 7 4,833

VREF =1,5VParameter VIN Iload Matlab/

Simulink R©Hsim

Overshoot/UndershootPeak(µs)

2,5

0 to 1,5 1,4 1,91,5 to 0 1 1,088

0,15 to 1,5 1,8 1,6151,5 to 0,15 0,6 0,806

3,3

0 to 1,5 1,3 1,4651,5 to 0 1,4 1,009

0,15 to 1,5 1,2 1,0441,5 to 0,15 0,8 0,959

Overshoot/Undershoot(VREF − vout)

2,5

0 to 1,5 33 41,111,5 to 0 32 39,6

0,15 to 1,5 40 51,81,5 to 0,15 25 27,1

3,3

0 to 1,5 23 36,881,5 to 0 40 34,76

0,15 to 1,5 26 19,341,5 to 0,15 33 32,04

Establishmenttime (1,5%) (µs)

2,5

0 to 1,5 0,5 2,7611,5 to 0 N/A N/A

0,15 to 1,5 2,2 3,1161,5 to 0,15 2,9 1,156

3,3

0 to 1,5 1,9 0,2241,5 to 0 N/A N/A

0,15 to 1,5 1,7 1,0441,5 to 0,15 4,1 2,451

As can be seen the circuit produces a maximum change of3 mV/V for a reference voltage of 1 V. For a reference voltageof 1,5 V the change produced is 3,8 mV/V. For the referencevoltage of 1,5 V and a current of 1,5 A the values where onlyconsidered from 2,0 V. This happens because the duty cyclerequired by the circuit will be too small and the control lawwould not be capable of generating a near constant outputvoltage.

The output voltage ripple for the line regulation valuesproposed are present in figure 18 for both reference voltages

Fig. 16. Line Regulation for 1 V Reference Voltage

Fig. 17. Line Regulation for 1,5 V Reference Voltage

Fig. 18. Voltage ripple for an line regulation from 1,8 V to 3,6 V

E. Load Regulation

The results analysis for the DC-DC converter when chang-ing the load of the circuit to produce the same output voltageis called load regulation. To know the influence of the changein load value to the required output voltage is necessary toanalyse it’s influence in the circuit. Figures 19 and 20 showthe average output voltage obtained for the reference voltagesof 1 V and 1,5 V to a load regulation from 1,5µA to 1,5 A.

As can be seen the circuit produces a maximum loadregulation of 3,5 mV/A for a reference voltage of 1 V. Fora reference voltage of 1,5 V the load regulation has a valueof 5,2 mV/A.

The ripple produced by a load regulation from 15µA to1,5 A is present in figure 21.

Fig. 19. LoadRegulation for 1,5 V Reference Voltage and supply voltagesof 2,5 V and 3,3 V

Fig. 20. LoadRegulation for 1,5 V Reference Voltage and supply voltagesof 2,5 V and 3,3 V

Fig. 21. Voltage ripple for an load regulation from 15µA to 1,5 A

The ripple of the load decreases when the load also de-creases. This happens because the current converter for lowloads varies less, causing less variation in output voltageandconsequently reduces the ripple.

The average switching frequency of the DC-DC converterfor a load regulation from 15µA to 1,5 A is present in figure22.

The switching frequency remains constant and around 3MHz for any supply and reference voltage until the DCM isachieved. At this mode the control will only turn the DC-DCat the ON-State during the time interval required to maintainoutput voltage at the desired value.

Finally table VI shows the converter achievements in this

Fig. 22. Voltage ripple for an load regulation from 15µA to 1,5 A

work. As can be seen all the values are accomplished and inthe load and line transients the results exceed the requirements.

TABLE VIDC-DC CONVERTER ACHIEVEMENTS

Symbol Parameter min typ max unitVIn Input Voltage 2,5 3,3 3,6 VVOut Output Voltage 1 1 1,5 V

VORiple Output VoltageRiple

21 mV

∆VOIO−PK Load TransientVoltage Peak

50 mV

∆VOIO−PK Line TransientVoltage Peak

≈ 0 V

∆VORiple

∆VINLine Regulation 3,8 mV/V

∆VORiple

∆ILoadLoad Regulation 5,2 mV/A

VII. C ONCLUSION

This Master Thesis work concludes that it is possibleto implement directly the sliding mode control law usingdigital circuits. The circuit was implemented in AMS@0.35µtechnology and validated using the HSim simulator.

It is possible to achieve an overshoot/undershoot with amaximum value of 50 mV for load transitions from No Load(0 A) to Full Load (1,5 A) and vice versa. When the loadbecomes from full load (1,5 A) to a 0,15 A load, and viceversa, the settling time is less than 5,1µs. For a line transientthe system responds immediately to this change producingno overshoot/undershoot. However, the average value driftstowards the line regulation.

The current controlled delay line controls the precision ofthe ADC. This is an advantage because the precision of theADC with a delay line can be adjusted as a function of the sys-tem specifications. The ADC is insensitive to layout parasitics,temperature, supply voltage and process parameters changes.This is a direct consequence from using an equal delay lineto obtain the reference voltage for the A/D conversion. If thelayout is designed to be symmetrical, a change in the ADCoperating conditions also afects the reference voltage generatorin a way that the digital word that corresponds toVREF isalways the same and the DC-DC is self adjusted to continueto obtain the same result.

This continuous self calibration capability of the DC-DC isconsidered a major original contribution of this thesis work.

FUTURE WORK

In the future it is possible to improve the circuit responseand efficiency. This can be done in several blocks such as:

• ADC delay line - The delay line can be substitutedby a ring oscillator [8] that can reduce significantly thearea and power consumption of the circuit reducing thecurrent mirror ratios and the number of inverters and levelshifters.

• Level Converter - With the reduction of the number ofinverters and consequently the number of level convert-ers, the implemented level converter could be replacedby more efficient structures even if they require moreelements.

• Control - Identify the elements that require more currentand replace them for more efficient digital circuits likehas happen with OAI212.

• ADC convergence - At this stage the ADC requiressignificant time to converge to the required referencevoltage. The fast achievement can be done by increasingthe current delivered to the reference voltage capacitorwhile the required voltage is away from the requiredvalue. This current increase can be done by introducingmore switches in the reference voltage control withsmaller resistances.

• Improve the ADC response to load transients -Whena load transient occurs, the spikes generated at the outputvoltage are reflected in the ADC generating wrong valuesduring a certain amount of time. The correction of thisworng feedback would improve the DC-DC response forload transients because the control would not generatethe opposite from the value required.

The ADC can work at smaller supply voltages, however due tothe limits imposed by the NMOS transistor, that limits the gatevoltage from the current mirror, the input voltage is limited toan upper value. Actually the circuit works fine for 2,5 V supplyvoltage, however it can only coversvfbinput voltages from 0to 1,33 V. To correct this issue and possibility implement anADC converter from rail to rail, it will be discussed also theimplementation in parallel on a PMOS transistor to cover thehigher values of the input voltage.

Stability analysis should be done in order to prove thestability of the digital control. It should also be done a moredetailed analysis of the sliding mode control, such as theinfluence of the non-idealities, switching frequency and delay.

The main future work consist in implementing the opti-mized system in to an integrated circuit to prove the systemfunctionality.

REFERENCES

[1] S. Chae, B. Hyun, W. Kim, and B. Cho, “Digital load current feed-forwardcontrol method for a dc-dc converter,” feb. 2008, pp. 498 –502.

[2] H. Wei and M. T. Tan, “A control algorithm to reduce steadystateoscillation in digital v2 dc-dc converters,” jan. 2009, pp.1 –6.

[3] S.-C. Tan, Y. Lai, C. Tse, and M. Cheung, “An adaptive sliding modecontroller for buck converter in continuous conduction mode,” vol. 3,2004, pp. 1395 – 1400 Vol.3.

[4] Q. Ming, “Sliding mode controller design for abssystem,” Master’s thesis, aprill 1997. [Online]. Available:http://scholar.lib.vt.edu/theses/available/etd-5440202339731121/

[5] S. W. Smith,The scientist and engineer’s guide to digital signal process-ing. San Diego, CA, USA: California Technical Publishing, 1997.

[6] A. S. Sedra and K. C. Smith,Microelectronic Circuits Revised Edition.New York, NY, USA: Oxford University Press, Inc., 2007.

[7] J. Ayers,Digital integrated circuits: analysis and design. CRC Press,2004.

[8] J. Kim and M. Horowitz, “An efficient digital sliding controller foradaptive power-supply regulation,”Solid-State Circuits, IEEE Journal of,vol. 37, no. 5, pp. 639 –647, may. 2002.