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Digital Data Communications Techniques
Ir. Hary Nugroho MT.
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Data Transmission
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The Successful transmission of data depends principally on two factor :The quality of the signal being
transmittedThe characteristics of transmission
medium
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Quality of the signal
Timing Problem controlling Dealing with errors
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Timing Problem Controlling
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Asynchronous and Synchronous Transmission
Timing problems(rate, duration, spacing) require a mechanism to synchronize the transmitter and receiver
Two solutionsAsynchronousSynchronous
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Asynchronous
Data transmitted one character at a time5 to 8 bits
Timing only needs maintaining within each character
Resynchronize with each character
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Asynchronous (diagram)
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Asynchronous - Behavior
In a steady stream, interval between characters is uniform (length of stop element)
In idle state, receiver looks for transition 1 to 0 Then samples next seven intervals (char length) Then looks for next 1 to 0 for next char
Simple Cheap Overhead of 2 or 3 bits per char (~20%) Good for data with large gaps (keyboard)
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Synchronous - Bit Level
Block of data transmitted without start or stop bits
Clocks must be synchronized Can use separate clock line
Good over short distancesSubject to impairments
Embed clock signal in dataManchester encodingCarrier frequency (analog)
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Synchronous - Block Level
Need to indicate start and end of block Use preamble and postamble
e.g. series of SYN (hex 16) characterse.g. block of 11111111 patterns
ending in 11111110
More efficient (lower overhead) than async
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Synchronous (diagram)
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Dealing with Error
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Types of Error
An error occurs when a bit is altered between transmission and reception
Single bit errors One bit altered Adjacent bits not affected White noise
Burst errors Length B Contiguous sequence of B bits in which first last and
any number of intermediate bits in error Impulse noise Fading in wireless Effect greater at higher data rates
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Error Detection Process
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Error Detection
Additional bits added by transmitter for error detection code
ParityValue of parity bit is such that
character has even (even parity) or odd (odd parity) number of ones
Even number of bit errors goes undetected
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Cyclic Redundancy Check
For a block of k bits transmitter generates n bit sequence
Transmit k+n bits which is exactly divisible by some number
Receive divides frame by that numberIf no remainder, assume no errorFor math, see Stallings chapter 6
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Error Correction
Correction of detected errors usually requires data block to be retransmitted (see chapter 7)
Not appropriate for wireless applications Bit error rate is high
• Lots of retransmissions
Propagation delay can be long (satellite) compared with frame transmission time
• Would result in retransmission of frame in error plus many subsequent frames
Need to correct errors on basis of bits received
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Error Correction Process Diagram
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Error Correction Process Each k bit block mapped to an n bit block (n>k)
Codeword Forward error correction (FEC) encoder
Codeword sent Received bit string similar to transmitted but may
contain errors Received code word passed to FEC decoder
If no errors, original data block output Some error patterns can be detected and corrected Some error patterns can be detected but not corrected Some (rare) error patterns are not detected
• Results in incorrect data output from FEC
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Working of Error Correction
Add redundancy to transmitted message Can deduce original in face of certain level
of error rate E.g. block error correction code
In general, add (n – k ) bits to end of block• Gives n bit block (codeword)• All of original k bits included in codeword
Some FEC map k bit input onto n bit codeword such that original k bits do not appear
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Device
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Line Configuration
Topology Physical arrangement of stations on medium Point to point Multi point
• Computer and terminals, local area network
Half duplex Only one station may transmit at a time Requires one data path
Full duplex Simultaneous transmission and reception between two
stations Requires two data paths (or echo canceling)
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Traditional Configurations
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Interfacing
Data processing devices (or data terminal equipment, DTE) do not (usually) include data transmission facilities
Need an interface called data circuit terminating equipment (DCE) e.g. modem, NIC
DCE transmits bits on medium DCE communicates data and control info with
DTE Done over interchange circuits Clear interface standards required
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Data Communications Interfacing
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Characteristics of Interface
MechanicalConnection plugs
ElectricalVoltage, timing, encoding
FunctionalData, control, timing, grounding
ProceduralSequence of events
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V.24/EIA-232-F
ITU-T v.24 Only specifies functional and procedural
References other standards for electrical and mechanical
EIA-232-F (USA) RS-232 Mechanical ISO 2110 Electrical v.28 Functional v.24 Procedural v.24
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Mechanical Specification
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Electrical Specification
Digital signals Values interpreted as data or control,
depending on circuit More than -3v is binary 1, more than +3v
is binary 0 (NRZ-L) Signal rate < 20kbps Distance <15m For control, more than-3v is off, +3v is on
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Functional Specification
Circuits grouped in categories Data Control Timing Ground
One circuit in each direction Full duplex
Two secondary data circuits Allow halt or flow control in half duplex
operation
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Local and Remote Loopback
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Procedural Specification
E.g. Asynchronous private line modem When turned on and ready, modem (DCE) asserts
DCE ready When DTE ready to send data, it asserts Request to
Send Also inhibits receive mode in half duplex
Modem responds when ready by asserting Clear to send
DTE sends data When data arrives, local modem asserts Receive
Line Signal Detector and delivers data
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Dial Up Operation (1)
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Dial Up Operation (2)
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Dial Up Operation (3)
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Null Modem
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ISDN Physical Interface Diagram
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ISDN Physical Interface
Connection between terminal equipment (c.f. DTE) and network terminating equipment (c.f. DCE)
ISO 8877 Cables terminate in matching
connectors with 8 contacts Transmit/receive carry both data and
control
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ISDN Electrical Specification
Balanced transmission Carried on two lines, e.g. twisted pair Signals as currents down one conductor and up the other Differential signaling Value depends on direction of voltage Tolerates more noise and generates less (Unbalanced, e.g. RS-232 uses single signal line and
ground) Data encoding depends on data rate Basic rate 192kbps uses pseudoternary Primary rate uses alternative mark inversion (AMI) and
B8ZS or HDB3
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Foreground Reading
Stallings chapter 6 Web pages from ITU-T on v.
specification Web pages on ISDN
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Data Link Control
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Flow Control
Ensuring the sending entity does not overwhelm the receiving entityPreventing buffer overflow
Transmission timeTime taken to emit all bits into medium
Propagation timeTime for a bit to traverse the link
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Model of Frame Transmission
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Stop and Wait
Source transmits frame Destination receives frame and replies
with acknowledgement Source waits for ACK before sending
next frame Destination can stop flow by not send
ACK Works well for a few large frames
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Fragmentation
Large block of data may be split into small framesLimited buffer sizeErrors detected sooner (when whole frame
received)On error, retransmission of smaller frames is
neededPrevents one station occupying medium for
long periods Stop and wait becomes inadequate
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Stop and Wait Link Utilization
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Sliding Windows Flow Control Allow multiple frames to be in transit Receiver has buffer W long Transmitter can send up to W frames without
ACK Each frame is numbered ACK includes number of next frame expected Sequence number bounded by size of field (k)
Frames are numbered modulo 2k
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Sliding Window Diagram
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Example Sliding Window
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Sliding Window Enhancements Receiver can acknowledge frames without
permitting further transmission (Receive Not Ready)
Must send a normal acknowledge to resume If duplex, use piggybacking
If no data to send, use acknowledgement frame If data but no acknowledgement to send, send
last acknowledgement number again, or have ACK valid flag (TCP)
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Error Detection
Additional bits added by transmitter for error detection code
ParityValue of parity bit is such that
character has even (even parity) or odd (odd parity) number of ones
Even number of bit errors goes undetected
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Cyclic Redundancy Check
For a block of k bits transmitter generates n bit sequence
Transmit k+n bits which is exactly divisible by some number
Receive divides frame by that numberIf no remainder, assume no errorFor math, see Stallings chapter 7
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Error Control
Detection and correction of errors Lost frames Damaged frames Automatic repeat request
Error detectionPositive acknowledgmentRetransmission after timeoutNegative acknowledgement and
retransmission
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Automatic Repeat Request (ARQ)
Stop and wait Go back N Selective reject (selective
retransmission)
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Stop and Wait
Source transmits single frame Wait for ACK If received frame damaged, discard it
Transmitter has timeout If no ACK within timeout, retransmit
If ACK damaged,transmitter will not recognize it Transmitter will retransmit Receive gets two copies of frame Use ACK0 and ACK1
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Stop and Wait -Diagram
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Stop and Wait - Pros and Cons
Simple Inefficient
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Go Back N (1)
Based on sliding window If no error, ACK as usual with next frame
expected Use window to control number of outstanding
frames If error, reply with rejection
Discard that frame and all future frames until error frame received correctly
Transmitter must go back and retransmit that frame and all subsequent frames
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Go Back N - Damaged Frame
Receiver detects error in frame i Receiver sends rejection-i Transmitter gets rejection-i Transmitter retransmits frame i and all
subsequent
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Go Back N - Lost Frame (1)
Frame i lost Transmitter sends i+1 Receiver gets frame i+1 out of
sequence Receiver send reject i Transmitter goes back to frame i and
retransmits
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Go Back N - Lost Frame (2)
Frame i lost and no additional frame sent Receiver gets nothing and returns neither
acknowledgement nor rejection Transmitter times out and sends
acknowledgement frame with P bit set to 1 Receiver interprets this as command which
it acknowledges with the number of the next frame it expects (frame i )
Transmitter then retransmits frame i
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Go Back N - Damaged Acknowledgement Receiver gets frame i and send
acknowledgement (i+1) which is lost Acknowledgements are cumulative, so next
acknowledgement (i+n) may arrive before transmitter times out on frame i
If transmitter times out, it sends acknowledgement with P bit set as before
This can be repeated a number of times before a reset procedure is initiated
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Go Back N - Damaged Rejection
As for lost frame (2)
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Go Back N - Diagram
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Selective Reject
Also called selective retransmission Only rejected frames are retransmitted Subsequent frames are accepted by
the receiver and buffered Minimizes retransmission Receiver must maintain large enough
buffer More complex login in transmitter
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Selective Reject -Diagram
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High Level Data Link Control
HDLC ISO 33009, ISO 4335
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HDLC Station Types
Primary station Controls operation of link Frames issued are called commands Maintains separate logical link to each
secondary station Secondary station
Under control of primary station Frames issued called responses
Combined station May issue commands and responses
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HDLC Link Configurations
UnbalancedOne primary and one or more
secondary stationsSupports full duplex and half duplex
BalancedTwo combined stationsSupports full duplex and half duplex
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HDLC Transfer Modes (1)
Normal Response Mode (NRM)Unbalanced configurationPrimary initiates transfer to secondarySecondary may only transmit data in
response to command from primaryUsed on multi-drop linesHost computer as primaryTerminals as secondary
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HDLC Transfer Modes (2)
Asynchronous Balanced Mode (ABM)Balanced configurationEither station may initiate transmission
without receiving permissionMost widely usedNo polling overhead
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HDLC Transfer Modes (3)
Asynchronous Response Mode (ARM)Unbalanced configurationSecondary may initiate transmission
without permission form primaryPrimary responsible for linerarely used
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Frame Structure
Synchronous transmission All transmissions in frames Single frame format for all data and
control exchanges
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Frame Structure
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Flag Fields
Delimit frame at both ends 01111110 May close one frame and open another Receiver hunts for flag sequence to synchronize Bit stuffing used to avoid confusion with data
containing 01111110 0 inserted after every sequence of five 1s If receiver detects five 1s it checks next bit If 0, it is deleted If 1 and seventh bit is 0, accept as flag If sixth and seventh bits 1, sender is indicating abort
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Bit Stuffing
Example with possible errors
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Address Field
Identifies secondary station that sent or will receive frame Usually 8 bits long May be extended to multiples of 7 bits
LSB of each octet indicates that it is the last octet (1) or not (0)
All ones (11111111) is broadcast
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Control Field
Different for different frame type Information - data to be transmitted to user
(next layer up)• Flow and error control piggybacked on information
frames
Supervisory - ARQ when piggyback not used Unnumbered - supplementary link control
First one or two bits of control filed identify frame type
Remaining bits explained later
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Control Field Diagram
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Poll/Final Bit
Use depends on context Command frame
P bit1 to solicit (poll) response from peer
Response frameF bit1 indicates response to soliciting
command
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Information Field
Only in information and some unnumbered frames
Must contain integral number of octets Variable length
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Frame Check Sequence Field
FCS Error detection 16 bit CRC Optional 32 bit CRC
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HDLC Operation
Exchange of information, supervisory and unnumbered frames
Three phasesInitializationData transferDisconnect
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Examples of Operation (1)
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Examples of Operation (2)
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Required Reading
Stallings chapter 7 Web sites on HDLC