Digital Control Technologies for Switching Power Converters

April 3, 2012 Dr. Yan-Fei Liu, Professor

Department of Electrical and Computer Engineering Queen’s University, Kingston, ON, Canada

yanfei.liu@queensu.ca www.QueensPowerGroup.com

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Outlines

1. Introduction 2. Steady State Performance Improvement 3. Auto Tuning with Digital Control 4. Dynamic Performance Improvement 5. Conclusion

Advantages of Digital Control

• Intelligence • Better system level performance • Better steady state performance • Better dynamic performance

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4

Challenges of Digital Control

• Output voltage resolution – Output voltage not continuously adjusted – Resolution of digital PWM generator not enough for

high switching frequency • Dynamic analysis of digital controller

– Digital design method is not suitable for power supply

• New control methods for digital control – To achieve better dynamic performance – NOT the digital implementation of analog method

5

Brief History of Digital Control

• Output voltage resolution – Catch even with analog control – No customer value

• New control technologies – Better performance – Customer value

• Smaller board area – PID implemented digitally – No need for Rs, Cs

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Evolution of Power Supply

Isolated converter Board Mount PS

7

Evolution of Power Supply

Point of Load (POL) Power Supply on Chip (PwrSoC)

No space for feedback R, C Digital control a must!

8

Digital PWM

DC-DC Converter

Digital PWM

Digital Compensator

Vin Vo

Vo Iind

Vcon

D

Block diagram of a DC-DC converter with digital control

9

Block Diagram of Digital Controlled Buck

Limit Cycle Oscillation: Should be avoided

LSB

ΔTon

ΔVo (ΔTon ) < LSB(ADC)

10

Basic Block Diagram of DPWM

Ton Counter PWM out

MSB bits

AND R

System Clock, 50M

Ts Counter

Coarse adjust

S

Digital Duty Cycle Bits

Delay Line

LSB bits Fine

adjust

Enable

MSB bits: coarse adjustment, based on system clock LSB bits: fine adjustment: based on gate delay

11

Fine DPWM: ASIC Tapped Delay Line

Use the input-output time delay of logic gate Increase the resolution of on time, or duty resolution

enable

LSB bits

12

Fine DPWM: FPGA Implementation

Shift Register

2 BitAdder 7

3 LSB Duty Cycle Input

(0 1 1)

Enable

2 BitAdder 6

2 BitAdder 5

2 BitAdder 4

2 BitAdder 0

2 BitAdder 3

2 BitAdder 2

2 BitAdder 1

0

0

0

0

1

0

0

0

Enable Signal

Output

Delayτ

1

1

1

1

1

1

1

1

C7=0

A7=1

A6=1

A5=1

A4=1

A3=0

A2=0

A1=0

A0=0

C6=0

C5=0

C4=0

C3=1

C2=1

C1=1

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

0

0

0

0

0

0

0

1

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Digital Pulse Width Modulator

• Bottom Line: – Achieve fine enough on time (Ton) resolution – Accurate control of output voltage

• Impact − Catch even with analog control

14

Introduction

• Value of Digital Control – Intelligence – Complicated calculation capability

• Mission − Explore the digital capability − Achieve better performance − Steady state, dynamic and system level

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Seminar Outlines

1. Introduction 2. Steady State Performance Improvement 3. Auto Tuning with Digital Control 4. Dynamic Performance Improvement 5. Conclusion

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2. Steady State Performance Improvement

• Light Load Efficiency Improvement – Phase shedding control – Logarithmic Current Sharing

• Heavy Load Efficiency Improvement – Automatic dead time adjustment

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Phase Shedding Control

• Reduce the activated phase number to improve efficiency

• Problems to be solved: – Current balance during load transient – Current sensing

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Light Load Efficiency Optimization

• Two Buck converters for 60A load current

65%

70%

75%

80%

85%

90%

95%

0 5 10 15 20 25 30

Eff

65%

70%

75%

80%

85%

90%

95%

0 10 20 30 40 50 60

Eff

Eff curve for one Buck converter Eff curve for two Buck converters

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Light Load Efficiency Optimization

• Efficiency curve for two Buck converters in parallel: – Io < 25A, one Buck operating, Io > 25A, two Buck converters operating

65%

70%

75%

80%

85%

90%

95%

0 10 20 30 40 50 60

Eff

Eff (shedding)

2 Buck in parallel 1 Buck operation

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2. Steady State Performance Improvement

• Light Load Efficiency Improvement – Phase shedding control – Logarithmic Current Sharing

• Heavy Load Efficiency Improvement – Automatic dead time adjustment

Block Diagram

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Current command No current

ADC Tight current

regulation

Phase enabler

4A

2A

1A

0 – 1 A

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Heavy Load Efficiency Optimization

• Buck converter – Dead time between Vgs1 and Vgs2 – Too long: body diode of Q2 conducts – Too short: shoot through between Q1 and Q2

Q1

Q2

Lo

Co

ESRDriver ic vo

+

-

iL

Io

Vin

A/D Converter

Digital Control Law S

Vref[n]

+

Digital PWM

RLoadA/D

Converter

-e[n] vo[n]iL[n]

d[n]......

vgs1

vgs2

td,on td,ontd,off td,off

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Heavy Load Efficiency Optimization

• How to determine optimal dead time – Highest efficiency = optimal dead time – Minimum input current = highest efficiency, Iin = D * Io – Minimum duty cycle = highest efficiency

24

Dead Time Optimization in SR Buck

• Strategy – Changing the dead time

and monitor the duty cycle

– Search algorithm to minimize the duty cycle with respect to Td,on, Td,off

Implementation Block Diagram

25

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Outlines

1. Introduction 2. Steady State Performance Improvement 3. Auto Tuning with Digital Control 4. Dynamic Performance Improvement 5. Conclusion

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3. Auto Tuning with Digital Control

• Auto Tuning – Change certain parameters in order to improve certain

performance – Unique to digital control, intelligence

• What can be achieved? – Power train circuit estimation – Compensating parameter design – Plug and play, no feedback design needed – Better dynamic performance

3. Auto Tuning Technology

• With Limit Cycle Oscillation – Oscillation caused by Limit Cycle Oscillation – Identify power circuit parameters – Design PID parameters

• With nonlinear relay oscillation • With Phase Margin measurement

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LCO Based Auto Tuning

• Limit Cycle Oscillation should be avoided − Caused by ΔVo (ΔTon ) > LSB(ADC)

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LCO Based Auto Tuning

• LCO frequency contains power circuit information • The relationship is:

Gain of DPWM Control to output

transfer function

ADC transfer function

Advantages

• Optimal dynamic performance with parameter tolerance

• Estimation of load current – For better current sharing

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3. Auto Tuning Technology

• With Limit Cycle Oscillation • With nonlinear relay oscillation

– Oscillation caused by relay – Design PID parameter directly

• With Phase Margin Measurement – Emulate human operation

32

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Auto Tuning Discussion

• Why Auto Tuning? – Get power train parameter – Design optimal PID parameters – Under different operating conditions, power parameters

• Benefits of Auto Tuning – Shorter design cycle (no or little loop design work) – Compensation for parameter changes over temperature, aging

• Value of Auto Tuning – Why customers want to pay for auto tuning – Compensation for parameter change – Good for shorter design cycle

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Seminar Outlines

1. Introduction 2. Steady State Performance Improvement 3. Auto Tuning with Digital Control 4. Dynamic Performance Improvement 5. Conclusion

Dynamic Performance Improvement

• Feature of Digital Control? – Intelligence – Complicated calculation capability – Adoption, changing control parameters based on

the changing conditions – Potential to achieve better performance – Steady state and dynamic

• What I would do if I were the controller?

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Dynamic Performance Improvement

• Charge Balance Control

– Minimum time control, Time optimal control, Optimal control, Continuous time control

• Basic idea – Force inductor current and capacitor voltage

recover at same time

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Conventional Control with Buck

L

Vin C

ESR

R L oiLi

CiRo

S 1

S 2

• Given circuit parameters: L, C, Vin, Vo, Fs, Io • Different dynamic response for different control methods

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Response of Conventional Controller

Point 0 Point 1 Point 2 Point 3 Point 4

iL_endio2

Vref

io1

iL3

iL0

AdischargeAcharge

t1t0

Load current

step

Transition time

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Charge Balance Control (CBC)

L

Vin C

ESR

R L oiLi

CiRo

S 1

S 2

• Given circuit parameters: L, C, Vin, Vo, Fs, Io • Different dynamic response for different control methods • One possible best dynamic response and find it

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Capacitor Charge Balance (over Ts)

• Used extensively in steady-state analysis of DC-DC converters

L

VinC

ESR

RL oiLi

Ci RoS 1

S 2Vc

Vo++

--

output voltage

Ts

inductor current

load current

reference voltage

+-

∫ =→=⋅=− sT

cs

avgcCcsc dttiT

ivTv0

1 0)(10)0()(

oLc iii −=

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Capacitor Charge Balance (Dynamic Period)

Extend principle to transient period

oad cu e t

reference voltage

output voltage

ta tb

∫ =−

=⋅=− b

a

t

t cab

avgcCacbc dttitt

oritvtv 0)(1,0)()( 1

Voltage recovers to original value when net charge balanced

Goal: Balance the charge in shortest

possible time

inductorcurrent

loadcurrent

t0 t1 t2 t3

referencevoltage

Adischarge

Acharge

outputvoltage

Tdis Tch

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Implementation of CBC

• Set PWM high immediately – Inductor current increases

at fastest slew rate – Minimizes Tdis – Minimizes Adischarge – Minimizes Δvo

• Set PWM low at t2 such that Acharge = Adischarge – Minimizes Tch – Minimizes settling time

How do we obtain t2?

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Discharge Area Calculation

A1

A3

A2

A1a

t0 t1 t2 t3

Adischarge = A1Acharge = A2 + A3

inductor current iL

load current io

IL0

Io1

Io2

T1T0 T2

Note:

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Charge Area Calculation

A1

A3

A2

A1a

t0 t1 t2 t3

Adischarge = A1Acharge = A2 + A3

inductor current iL

load current io

IL0

Io1

Io2

T1T0 T2

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Balancing the Charge Area

A1

A3

A2

A1a

t0 t1 t2 t3

Adischarge = A1Acharge = A2 + A3

inductor current iL

load current io

IL0

Io1

Io2

T1T0 T2

discharge Charge

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Physics of the Double Integration

Vo integrated two times from t0 to t1

-Vin integrated two times from t1 to t2

At t = t2 , these two terms added together is zero

∫ ∫ ∫ ∫

=1

0

1

0

1

0OO VV

t

t

t

t

t

tdtdtdtdt ( )∫ ∫ ∫ ∫

=2

1

2

1

2

1inin V-V-

t

t

t

t

t

tdtdtdtdt

Re-write the integrations as:

The second integrations can be combined.

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Double Integrator Implementation

∫∫

∫

t0

t

vint2

vint1

t1 t0 t1 t2

vint1

vint2

Vo

-Vin

Multiplexer

t

1a

1b

20

1Reset: t<t0 or t>t1

Reset: t<t1 or t>t2 t>t1

Reset: t<t0 or t>t2

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Block Diagram of CBC with Analog

Q1

Q2

Lo

Vin

Co

ESR

RL

LoadDriver

Conventional Controller

Linear Control Voltage Hold

Ic

Vo

+

-

PWM Multiplexer

IL

Io

Charge BalanceController

Steady-State /Transient

PWM Output

VinVout

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Other Considerations

• Equations for a positive load current step – For a negative load current step, the derivation is

similar

• Before completion, algorithm calculates the new steady state duty cycle d and inductor current iL to be passed to the PID current-mode controller – Allows for a smooth transition

Importance for Detection of t1 and t2

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• At t = t1: – I_load = I_ind – Icap = 0 – Vout = min

• Critical to detect t1: • t2 depends on t1

inductorcurrent

loadcurrent

t0 t1 t2 t3

referencevoltage

Adischarge

Acharge

outputvoltage

Tdis Tch

Technologies to Detect t1 and t2

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• Analog Icap sensing – Trans-impedance amplifier for t1 – Double integrator falls to zero – As discussed before

• Digital Icap information – Digital Icap rebuilding – Digital double integrator falls to zero – Suitable for AVP

Other Technologies to Detect t1 and t2

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• Time domain detection – Asynchronous ADC operation for t1 – Calculate t2 based on t1

• Continuous time DSP structure • Voltage domain detection

– Voltage value calculated to determine t1 – Voltage value calculated to determine t2 – AVP achieved

Other Technologies to Detect t1 and t2

• Time domain detection – Asynchronous ADC operation for t1

– Calculate t2 based on t1

• Continuous DSP structure • Voltage domain detection

– Extreme voltage detector for t1 – Parabolic Curve Fitting for t1 to determine t2 – AVP can be achieved

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Digital Parallel Current Mode Control

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Reference signal for inductor current )()()(1 tvtvktv controlgxref =

When vin(t) ↑ → vg(t) ↑, →vref1(t) ↑, →ig(t) ↑, pin(t) ↑, →VC(t)↑. This is not a desired situation. We need to wait the voltage loop to bring down the output voltage.

Digital Parallel Current Mode Control

Ro

L D

C Vo

+

-

Vin(t)

+

-

S

L

Vin(t) RoVo

+

-

C

+

-

L

+

-

RoC Vo

+

-

Vin(t)

Li Li

inL V

dtdiL = snnn Tdttt +<≤

oinL VV

dtdiL −= 1+<≤+ nsnn ttTdt

Basic idea of parallel current mode control:

Boost Converter On state Off state

Inductor current:

Digital Parallel Current Mode Control

LTndV

LTnVnini sosin

LL⋅−

−⋅

+=+))(1()()()1(

Inductor current in discrete form:

At duty cycle d, the inductor current at the end of switching cycle

Rewrite the above equation as:

o

ino

o

LL

s VnVV

Vnini

TLnd )()()1()( −

+−+

⋅=

Required duty cycle in order to drive inductor current from iL(n) at the beginning of switching cycle to iL(n+1) at the end of switching cycle.

Digital Parallel Current Mode Control

For a properly designed system, we want:

Proposed power factor correction algorithm:

o

ino

o

LL

s VnVV

Vnini

TLnd )()()1()( −

+−+

⋅=

refo VV = )1()1( +=+ nini refL

ref

inref

ref

Lref

s VnVV

Vnini

TLnd

)()()1()(

−+

−+=

Substitute the above two relations into duty cycle equation:

Digital Parallel Current Mode Control

Block diagram: parallel operation.

BoostConverterV in

Current TermCalculation

Voltage TermCalculation

V refi ref(n+1)

i L(n)V in(n)

d(n)

V ref

Vo

Digital Parallel Current Mode Control

Reference current for PFC implementation:

IPK is the peak inductor current, from voltage error amplifier sin (ω · t(n+1) ) is sine waveform, from lookup table Therefore, direct duty cycle control for PFC:

))1(sin()1( +⋅⋅=+ ntIni PKref ω

ref

inref

c

LPK

VnVV

KnintI

nd)()()1(sin(

)(−

+−+⋅⋅

=ω

where Kc=TsVref /L, is a constant

Digital Implementation

Load

L D

AC S C2

Vin iL

+

-

Vo

iL

Vin Vo

PWM A/DA/D

Duty CycleCalculation

Sine WaveLook up Table

Multiplierpidk PID

refVerror

Zero CrossDetection DSP

C1

R1

R2

R3

R4

GateDriver

A/D

)(niL

)(nVin

)(nd

Input Voltagefed-forward

)sin( 1+⋅ nline tϖ

)sin( 1+⋅= nlinepidref tki ϖ

Digital Implementation

OpAmp1I term

+

Vref

OpAmp2V term

OpAmp3Adder

Iref = K* Vac_pk*IPK*|sin(wline t)|

+

-

PWM

Gatedrive

-

L

Q

DiL(t)

CLoad

Vo

OpAmp4Voltage Loop

iL(t)

Vin

Currentsensor

Vo-

+

iL_avg(t)

Vin

Vac

D1 D3

D2D4

Iac

MultipierIPK

K*Vac_pk * |sin(wline t)|

Vref

ref

inref

c

LPK

VnVV

KnintI

nd)()()1(sin(

)(−

+−+⋅⋅

=ω

Kc=TsVref /L

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Outlines

1. Introduction 2. Steady State Performance Improvement 3. Auto Tuning with Digital Control 4. Dynamic Performance Improvement 5. Conclusion

63

Future Work for Digital Control

• Take advantage of digital circuits • Provide value to end customers

– Lower cost, better (same) performance at lower cost – Better performance at same cost

• Dynamic performance improvement – Reduced undershoot and overshoot – Smaller output capacitor value

– Digital only implementation – Analog circuit cannot make it

Conclusion

• Take advantage of digital circuits – Intelligence, calculation capability, lower cost

• Provide value to end customers – More cost effective product

• Auto tuning – Reduced design effort, better performance

• Charge Balance Control (or TOC) – Reduced output capacitor, faster response

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