Digital Control Options for Embedded DC-DC Converters...

Digital Control Options for Embedded DC-DC Converters in CMOS SoC

G. Maderbacher, S. Marsili, C. Sandner

Center of Competence Power Mgmt Systems

Design Center Villach

Infineon Technologies Austria AG

PowerSoC 2012, San Francisco

Copyright © Infineon Technologies 2009. All rights reserved.

Outline

n  Introduction

n Advantages of digital controllers

n Building blocks

o DPWM

o ADC

n  Limit cycle oscillation

n Efficiency comparison

n Conclusion

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Digitally Controlled Power Management in SoC

n  Digital and analog baseband and power management functions are monolithically integrated in 65nm CMOS

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2 x digitally controlled DCDC converter same DCDC already ported in 28nm CMOS [1]


Analog and Digitally Controlled DC-DC Buck Converters

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VSS

VIN

L

C load

DRV, LS,

DTCU

PWM comparator

ramp generator

VoutVref

compensator

VSS

VIN

L

C load

DRV, LS,

DTCU

VoutADC DPWM

Vref

digitalcompensator

n  Analog control:

o  compensator compares a the scaled converter output voltage with a reference voltage

o  the error signal goes to a PWM which generates control pulses for the power stage

o  fine resolution of the output voltage

n  Digital control

o  ADC converts output voltage into digital representation

o  digital compensator calculates actuating variable for the DPWM

o  DPWM generates control pulses for the power stage

o  only finite resolution of the output voltage

Digital control

Analog control


Comparison of Transient Performance for Different Controllers

n All the controllers have same bandwidths

n Analog controller structures generally are able to deliver a better transient performance than digital controllers in a certain operating point [4]

n Why do we often prefer digital implementations ? 11/29/12


Why do we often Prefer Digital Controller?

n Can be easily ported to different technologies

n They are stable over process and temperature

n We can implement a lot of different features:

o  advanced control methods (e.g. non linear control) o  provide different operating modes (PWM-CCM, PWM-DCM, Feed-

Forward) o  calibration algorithm o  monitor functions o  different controlled startup scenarios o  frequency spreading o  dynamic voltage scaling o  digital dead time optimization o  …

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General Macro of Digitally Controlled DC-DC converter

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PID

CORE

Adaptation DCM

Adaptation Feed Forward

Digital PWM

Scheduler

ADC

error precondition

ΣΔ modulator

Voltage Monitoring

Over Current Handling

Pulse Shaping

Buck/Boost

Startup

Vo

iL Vi

Frequency Spreading

Pulse Skipping

Transient Frequency Control


Product A

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PID

CORE

Adaptation DCM


Digital PWM ADC

error precondition

ΣΔ modulator

Voltage Monitoring


Pulse Shaping

Buck/Boost

Startup Frequency Spreading

Pulse Skipping

Scheduler Transient Frequency Control


Product B

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PID

CORE

Adaptation DCM


Digital PWM ADC

error precondition

ΣΔ modulator

Voltage Monitoring


Pulse Shaping

Buck/Boost

Startup Frequency Spreading

Pulse Skipping

Scheduler Transient Frequency Control


Automatic Controller Parameter Adaption for Different Operating Modes

n  optimized set of controller parameters in CCM à not an optimum in DCM

n  Adapt the coefficients according to the time interval where iL=0

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iL

P

I

D


Published DC-DC Buck Converters: Analog Control vs. Digital Control

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1e

2e

3e

4e

5e6e8e

9e

10e

11e

12e

13e

14e

15e

16e

17e

18e

19e20e

21e

22e

23e

24e

25e

26e

27e

40

50

60

70

80

90

100

1 10 100 1000

Converter P

eak Efficiency (%

)

Operating Frequency (MHz)

analog controldigital control


DPWM

n Counter based DPWM

¬  linear/monotonic ¬  can be implemented in HDL ¬  requires a high system clock: 2n*fs

(e.g. fs=5MHz, 7bit à clk ~640MHz; fs=80MHz, 7bit à ~10GHz!!)

n Delay line based DPWM

¬  high resolution ¬ monotonic ¬  large multiplexer (thermometer code)

n Hybrid DPWM

¬  counter based DPWM (coarse) & delay line based DPWM (fine) ¬  resolution: n+m bit ¬  required system clock: 2n*fs

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n-bit down counter

2n*fs

init

zero detectorS

Rout

ton toff

fs τd τd τd τd τd τd

MUX set

SR

out

ton toff

n-bit counter based DPWM

2n*fs

init

m-bit delay line based

DPWM

SR

out

ton toff


ADC Performance: Power vs. Bandwidth

[5] Data: B. Murmann, "ADC Performance Survey 1997-2012," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.

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1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

1E-01

1E+00

1E+01

1E+02

1E+04 1E+05 1E+06 1E+07 1E+08 1E+09 1E+10 1E+11

Pow

er [W

]

fsnyq [Hz]

ISSCC SNDR<50dBVLSI SNDR<50dBISSCC SNDR>50dBVLSI SNDR>50dB


Limit Cycle Oscillation

n  Limit cycle oscillation is only a problem in digitally controlled DC-DC converter

n  It occurs due to quantization effects in the feedback loop

n output voltage oscillates around the nominal voltage

n  It can occur if the resolution of the DPWM is lower than the resolution of the ADC

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0

+1

+2

-1

-2

D

+1

-1

ADCDPWM Vout target

time

volta

ge le

vels +2


Ways to Avoid Limit Cycle Oscillations

n  increase DPWM resolution [2]: ∆Vo_DWPM < ∆VADC with ∆Vo_DWPM = VIN*∆D

o can be done by:

¬  increasing system clock ¬  change the DPWM topology ¬  dithering ¬ ∑∆-modulation

n  shift the target value to a comparator threshold by adding 0.5 to the ADC output [1]:

o high static accuracy

o only one comparator has to be designed with low offset

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0

+1

-1

D

+1

-1

ADCDPWM Vout target

+2

-2

time

volta

ge le

vels +3

0

+1

-1

-2D

+1

ADCDPWM Vout

targetvalue

timevo

ltage

leve

ls

- 0.5 +0.5 - 0.5 +0.5 - 0.5 +0.5

sample points

ADC+0.5

Vout

0

-1


Pdig0,5%

PDPWM1,1% PADC

0,7%

PR11,9%

PM15,1%

PON,P15,9%

PCOM,P21,1%

PDRV,P4,4%

PON,N18,0%

PCOM,N6,9%

PDRV,N4,4%

Pdig6,7%

PDPWM16,0%

PADC10,7%

PR1,1%

PM0,5%PON,P

8,2%

PCOM,P28,5%

PDRV,P8,6%

PON,N11,7%

PCOM,N7,1%

PDRV,N0,9%

Power Losses: fs=1.6MHz vs. 80MHz (50x)

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Fig.1: 1.6MHz, Efficiency=90%

Fig.2: 80MHz, Efficiency=73%

Conditions: n  65nm CMOS, 100mA load n  3.3uH vs. 200nH n  switches optimized for peak eff. around 100mA

ßController+DPWM+ADC: 2,3%

Here: 33%


Conclusion

n Digital power control allows very flexible power conversion

n Going to high switching frequency (àPowerSoC applications):

o No blocking point in using digital power control

o We can implement

¬  high resolution DPWMs,

¬  fast ADCs

o We know techniques to avoid limit cycle oscillation

o BUT: efficiency!!!

o Analog control: much simpler (eg. COOT, hysteretic controller), therefore better efficiency

n  Future will show more and more digital control also at higher frequencies, since technology scaling will help digital control

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Bibliography

n  [1] A digitally controlled DC-DC converter for SoC in 28nm CMOS-F.; Habibovic, H.; Hartig, T.; Fulde, M.; Babin, G.; Santner, A.; Bogner, P.; Kropf, C.; Riesslegger, H.; Hodel, U.; - Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International

n  [2] Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters; Peterchev, A.V.; Sanders S.R., IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO.1 JANUARY 2003

n  [3] A Digitally Controlled Linear Voltage Regulator in a 65nm CMOS Process; Jackum, T.; Riederer, R.; Maderbacher, G.; Pribyl, W., Proceedings of ICECS , 2010

n  [4] Comparative study of linear and non-linear integrated control schemes applied to a Buck converter for mobile applications - Priewasser R., Agostinelli M., Marsili S., Straeussnig D., Huemer M. - Austrochip 2009 Tagungsband - pp. 51-56

n  [5] Data: B. Murmann, "ADC Performance Survey 1997-2012," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.

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Digital Control Options for Embedded DC-DC Converters...

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