Digital Control of Switching Mode Power Supply Simone Buso 1

8/13/2019 Digital Control of Switching Mode Power Supply Simone Buso 1

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Simone Buso - UNICAMP - August 2011 1/74

Digital control of switching mode power supplies

Digital control of switching modepower supplies

Simone Buso

University of Padova ITALY

Dept. of Information Engineering DEI


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About the instructor

Simone Buso

Associate Professor of Electronics

University of PadovaDept. of Information Engineering DEI

Via G. Gradenigo, 6/a35131 PadovaITALY

phone: +39 049 8277525fax: +39 049 8277699

E-mail: [email protected]


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Lesson 1

Control of power converters by PWM modulationAnalog PWM: naturally sampled implementationDigital PWM: uniformly sampled implementationSingle update and double update modesMinimization of the modulator delay

Digital current mode control of power converters

Space Vector Modulation

Modulation in three phase systems

Transformation

Space Vector Modulation


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Basic motivations

Digital control offers the possibility to implement sophisticated control laws,taking care of system non linearities, parameter variations or constructiontolerances by means of self-analysis and auto tuning strategies, very difficult orimpossible to implement analogically.

Software based digital controllers are inherently flexible, which allows thedesigner to modify the control strategy, or even to totally re-program it, withoutthe need for significant hardware modifications. Also very important are thehigher tolerance to signal noise and the complete absence of ageing effects or

thermal drifts.

A large variety of electronic devices, from home appliances to industrialinstrumentation, require the presence of some form of man to machine interface(MMI). Its implementation is almost impossible without having some kind of

embedded microprocessor. The utilization of the computational power, that thusbecomes available, also for lower level control tasks is often very convenient.


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+

-

+-

+

RS

VDCD1

VDC D2

S1

S2

LSES

G1

G2

E2

E1

C O

IO

Case study: a Voltage Source Inverter

Half bridge voltage source inverter


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The VSI represented can be described in the state space by the followingequations:

Case study: a Voltage Source Inverter

+=

+=

DuCxy

BuAxx&

where x = [IO] is the state vector, u = [VOC, ES]T is the input vector and y = [IO]

is the output variable.

Direct circuit inspection yields:

A = [-RS/LS], B = [1/LS, -1/LS], C = [1], D = [0, 0]

Based on this model and using Laplace transformation, the transfer functionbetween the inverter voltage VOC and the output current IO, GI

OV

OC

can befound to be:

( ) ( )

S

SS

11

1

OC

O

VI

R

Ls1

1

R

1BAsIC

V~I~

sGOCO

+

===


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The VSI controller is organized hierarchically. In the lowest level a controllerdetermines the state of each of the two switches, and in doing this, the averageload voltage. This level is called the modulator level.

The strategy according to which the state of the switches is changed along timeis called the modulation law. The input to the modulator is the set point for theload average voltage, normally provided by a higher level control loop.

A direct control of the average load voltage is possible: in this case the VSI is

said to operate in open loop conditions. However, this is not a commonlyadopted mode of operation, since no control of load current is provided in thepresence of load parameter variations.

Case study


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Because of that, in the large majority of cases, a current controller can be foundimmediately above the modulator level. This is responsible for providing the set-point to the modulator.

Similarly, the current controller set-point can be provided by a further externalcontrol loop or directly by the user.

In the latter case, the VSI is said to operate in current mode, meaning that the

control circuit has turned a voltage source topology into a controlled currentsource.

Case study


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t

TS

c(t), m(t)cpk

t

t

t

dTS

VOC(t) +VDC

-VDC

+

-

m(t)

c(t)

VGE1(t)*

VGE2(t)*

VGE1(t)*

VGE2(t)*

m(t)c(t)

DRIVER

VMO(t)

COMPARATOR

PWM modulator: analog implementation

Naturally sampled implementation of a PWM modulator.


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A square wave voltage VOC is applied to the load, with constant frequency fS=1/TS, TSbeing the period of the carrier signal c(t), and variable duty cycle d. Thisis implicitly defined as the ratio between the time duration of the +VDCvoltageapplication period and the duration of the whole modulation period, TS.

We can explicitly relate signal m(t) to the resulting PWM duty-cycle. Simplecalculations show that, in each modulation period, where a constant misassumed, the following equation holds:

pkS

pk

Scmd

Tc

dTm ==

PWM modulator: principles of operation

( ) ( ) ( )( )( ) ( )( )1td2VTtd1VtdVTT

1d)(V

T

1tV

DCSDCDCS

S

t

TtOC

S

OCS

===

In addition, we can compute the relationship between the duty-cycle and theaverage inverter voltage. This turns out to be:


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If we assume that the modulating signal changes slowly along time, with respectto the carrier signal, i.e. the upper limit of m(t) bandwidth is well below 1/TS, wecan still consider the above result correct.

This means that, in the hypothesis of a limited bandwidth m(t), the informationcarried by this signal is transferred, by the PWM process, to the duty-cycle, thatwill change slowly along time following the m(t) evolution. Based on the previousrelation, this means that

The duty-cycle, in turn, is transferred to the load voltage waveform by the powerconverter. The slow variations of the load voltage average value will therefore

copy those of signal m(t). Therefore, the modulator transfer function, including theinverter gain will be given by:

pk

DCOC

c

V2

m

d

d

V=

pkc1

md =


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A more mathematically sound approach, would basically show that thefrequency content, i.e. the spectrum, of the modulating signal m(t) is shiftedalong frequency by the PWM process, and is replicated around all integermultiples of the carrier frequency.

This implies that, as long as the spectrum of signal m(t) has a limited bandwidthwith a upper limit well below the carrier frequency, signal demodulation, i.e. thereconstruction of signal m(t) spectrum from the signal VOC(t), with associated

power amplification, can be easily achieved by low pass filtering VOC(t).

In the case of power converters, like the one we are considering here, the lowpass filter is actually represented by the load itself.

Again, this implies that the previously found transfer function is, in a firstapproximation (i.e. neglecting the residual ripple), correct. Please note that,from now on, the modulating signal m(t) will always be assumed to be limited inbandwidth.



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VOC(t)

ES(t)

t

t

IO(t)

IO(t)

VOC(t)


Example of PWM operation

+

-

+

-

+

RS

VDCD1

VDC D2

S1

S2

LSES

G1

G2

E2

E1

C O

IO


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PWM modulator: dynamic response

The previous analysis assumes the following relationship exists between smallvariations of the duty-cycle, , and the corresponding variations of themodulating signal, .

d~

m~

pkc1

md =

The purely proportional relationship implies an instantaneous response (i.e.

exhibiting no delay whatsoever) of the modulator to changes in the modulatingsignal. A fundamental question arises:

is the assumption correct?

The answer to this question has been found 30 years ago by R.D. Middlebrook,and it is absolutely affirmative.


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Indeed, it is possible to see that any change in the modulating signals amplitude,provided that its bandwidth limitationis maintained, implies an immediate, i.e. inphase, adjustment of the resulting duty-cycle.

This means that the analog implementation of PWM guarantees the minimumdelay between modulating signal and duty-cycle. Therefore, the intuitiverepresentation of the modulator operation can be actually corroborated by a moreformal, mathematical analysis.

The formal derivation of an equivalent modulator transfer function, in magnitudeand phase, has been studied and obtained since the early 80s. The modulatortransfer function has been determined using small signal approximations [1],where the modulating signal m(t) is decomposed in a dccomponent Mand a

small signal perturbation (i.e. m(t) = M + ). The corresponding duty-cyclehas been found, whose small signal component is called .

[1] R.D. Middlebrook; Predicting modulator phase lag in PWM converter feedback loops,

Advances in switched-mode power conversion, vol I, pp. 245-250, 1981.

m~ m~d~


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m(t)

VOC(t)

t t

tt

m(t)

M

m~

D

d~

m~

d~ DTS

c(t)

d~


TSTS

TS

TS

d(t)


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Under these assumptions, in [1], the author demonstrates that the phase lag ofthe naturally sampled modulator is actually zero, i.e. and are in phase,concluding that the analog PWM modulator delay can always be considerednegligible. Therefore, the transfer function we already computed can be

considered as well a reasonable model of the inverter dynamic behaviour.

Quite differently, we will see in the following how the discrete time or digitalimplementations of the pulse width modulator, that necessarily imply the

introduction of sample-and-hold effects, often determine a significant responsedelay [2].


[2] D.M. Van de Sype, K. De Gusseme, A.P. Van den Bossche, J.A. Melkebeek, Small-signal Laplace-domain analysis of uniformly-sampled pulse-width modulators; 2004 Power

Electronics Specialists Conference (PESC), 20-25 June, pp. 4292 - 4298

m~ d~

Di it l t l f it hi d li


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PWM modulator: dead times

+

-

+

-

+

RS

VDCD1

VDC D2

S1

S2

LSES

G1

G2

E2

E1

C O

IO

Dead times effectfor IO > 0

t

t

t

t

t

tdead*

GEV 1

VGE1

VGE2

*

GEV 2

VOC

TS

TS

TS

TS

TS

tON1

tON2

Logicgatesignals

Appliedgatesignals

Loadvoltage

+VDC

-VDC

tdead

Digital control of s itching mode po er s pplies


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To avoid cross conduction, the modulator delays S1 turn-on by a time tdead,applying the VGE1 and VGE2command signals to the switches. The duration oftdead is long enough to allow the safe turn off of switch S2before switch S1 iscommanded to turn on, considering propagation delays through the driving

circuitry, inherent switch turn off delays and suitable safety margins.

The typically required dead time duration for 600 V, 40 A IGBT is currently well

below 1 s. Of course, the dead time required duration is a direct function of theswitch power rating.

It is important to notice that the effect of the dead time application is the creationof a time interval where both switches are in the off state and the load currentflows through the free-wheeling diodes.

Because of that, an undesired difference is created between the duration of theS1 switch on-time and the actual one, that turns into an error in the voltageapplied to the load.




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It is important to notice that the opposite commutation, i.e. where S1 is turned offand S2 is turned on, does not determine any voltage error. However, we mustpoint out that, if the load current polarity were reversed, the dead time inducedload voltage error would take place exactly during this commutation.

The above discussion reveals that, because of dead times, no matter what themodulator implementation, an error on the load voltage will always be

generated. This error, VOC, whose entity is a direct function of dead timeduration and whose polarity depends on the load current sign, according to the

following relation

will have to be compensated by the current controller. Failure to do so willunavoidably determine a tracking error on the trajectory the load current has tofollow (i.e. current waveform distortion).


)(2O

S

dead

DCOC IsignT

tVV =



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Clock Binary Counter

Duty-Cycle

n bits

n bits

Binary Comparator

Timer Interrupt

Match Interrupt

PWM modulator: digital implementation

Digital PWM modulator typical structure



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The counter is incremented at every clock pulse; any time the binary countervalue is equal to the programmed duty-cycle (match condition), the binarycomparator triggers an interrupt to the microprocessor and, at the same time,sets the gate signal low.

The gate signal is set high at the beginning of each counting (i.e. modulation)period, where another interrupt is typically generated for synchronizationpurposes.

The counter and comparator have a given number of bits, n, which is often 16,but can be as low as 8, in the case a very simple microcontroller is used.

Depending on the ratio between the durations of the modulation period and thecounter clock period, a lower number of effectivebits, Ne, could be available torepresent the duty-cycle. The Neparameter is important to determine the duty-cycle quantization step.




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The number Neof effective bits, used to represent the duty-cycle, is given by thefollowing relation

where fclock is the modulator clock frequency, fS=1/TS is the desired modulationfrequency and the floor function calculates the integer part of its argument.Typical values for fclockare in the few tens of MHz range, while modulationfrequencies can be as high as a few hundreds of kHz.

When the desired modulation period is short, the number of effective bits, Ne,will be much lower than the number of hardware bits, n, available in thecomparator and counter circuits, unless a very high clock frequency is possible.


12log

log

10

10

+

= S

clock

e f

f

floorN



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Timer count

t

Timer interrupt request

t

t

Gate signal

Programmed duty-cycle

TS


Digital PWM operation principle



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g g p pp

Digital PWM modulator: dynamic response

It is immediate to see that the modulating signal update is performed only at thebeginning of each modulation period.

We can model this mode of operation using a sample and hold equivalent.

Indeed, we can observe that, neglecting the digital counter and binarycomparator effects (i.e. assuming infinite resolution for both), the digitalmodulator works exactly as an analog one, where the modulating signal m(t) issampled at the beginning of each modulation period and the sampled valueheld constant for the whole period.

m(t)+

-

ms(t)

c(t)

VMO(t)ZOHTS



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g g p pp

It is now evident that, because of the sample and hold effect, the response of themodulator to any disturbance, e.g. to one requiring a rapid change in theprogrammed duty-cycle value, can take place only during the modulation periodfollowing the one where the disturbance actually takes place.

This delay amounts to a dramatic difference with respect to the analogmodulator implementation, where the response could take place already duringthe current modulation period, i.e. with negligible delay.

Even if our signal processing were fully analog, without any calculation orsampling delay, passing from an analog to a digital PWM implementation wouldimply, by itself, an increase in the systems response delay.

We can now mathematically analyze the simplest implementation of the digitalmodulator, so as to determine its exact dynamic model.




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t

c(t), m(t)

cpk

t

VMO(t)

c(t) m(t)

ms(t)

TS


pk

sDT

MO

ce

)s(M)s(V)s(PWM

S

==

Digital PWM: trailing edge implementation

Objective: we will now prove that

: sampling instants


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Digital PWM: small signal analysis

t

t

t

cpk

MSmS~

mS~

nTS (n+1)TS

VMO

vMO~

DTS DTS

pk

S

c

T

pk

S

c

T

Unity area Diracimpulse

perturbations

Correction pulses

Dirac impulseapproximation ofcorrection pulses



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Considering small signal perturbations, , of the steady state output of thesampler, MS, we can see how these are turned into small correction pulses,appearing at the modulator output, .

The correction pulses can be approximated as ideal, zero duration impulses,with equal area, and located at the steady state pulses edge.

The input perturbations can be, in particular, unity area Dirac impulsesappliedat the modulator input. Considering one of these impulses to be applied at timezero, we can immediately find that, in the above approximation, it generates atime translated impulse at the output:

whose area is equal to the modulator small signal gain (i.e. the inverse of thesaw-tooth slope).

Sm~

MOv~

)(1~S

pk

S

MO DTt

c

Tv

=



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Any generic discrete time sampled signal can be expressed as a sum ofweighted Dirac pulses, such as:

therefore, it is now possible to express the Laplace transform of the genericmodulator output as a function of the sampled input signals one. Since any inputpulse is translated into a time shifted, scaled area, correction impulse we canwrite:

We can now compute the Laplace transform of both sides of the aboveexpression, exploiting the rule for time translation and the basic property of theDirac pulse to have a unity Laplace transform.

( ) ( )+

=

=n

SSS nTtnTmtm ~)(~

( ) ( )+

=

=n

SS

pk

S

SMO DTnTtc

TnTmtv ~)(~


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If we assume, as usual, that the input signal spectrum is limited in bandwidthbelow the Nyquist frequency, and if we neglect the output signal frequencycontent above the same frequency, then we can say:

And, consequently,

that represents the transfer function between the modulator input and output

signals. A similar procedure can be applied to other, more complex, modulatororganizations. Another useful relation, that we will use later on, is the following:

( )sMT1

sMS

S )(

pk

sDT

MO

c

e

sM

sVsPWM

S

== )(

)()(

)(

)()(

sM

sVsPWMT

S

MOS =



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t

c(t), m(t)

cpk

t

VMO(t)

c(t) m(t)

ms(t)

TS

Digital PWM: leading edge implementation


pk

T)D1(s

MO

ce

)s(M)s(V)s(PWM

S

==



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t

cpk

t

VMO(t)

c(t)

m(t)

ms(t)

TS

c(t), m(t)

+==

+2

T)D1(s

2

T)D1(s

pk

MOSS

eec2

1

)s(M

)s(V)s(PWM


Digital PWM: symmetric pulseimplementation



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The transfer functions we just found correspond to a non instantaneous behaviorof the digital modulator. As can be seen by computing arg(PWM(j)) there willalways be a phase shift between the input and output signal, whose entity is, ingeneral, a function of the steady state duty-cycle value. For example, in the case

of the single update, trailing edge implementation we can find:

Similarly, for the symmetric pulse implementation we find:

which is a remarkable result, as it does not depend on the particular steady-state

value of the duty-cycle, D.

S

pk

DTj

DTc

ejPWM

S

=

=

arg))(arg(

( ) ( )

2

T

c2

ee

jPWM

S

pk

2

TD1j

2

TD1j SS

=

+

=

+

arg))(arg(



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To partially compensate for the increased delay of the uniformly sampledPWM, the double update mode of operation is often available in severalmicrocontrollers and DSPs.

In this mode, the duty-cycle update is allowed at the beginning and at the halfof the modulation period. Consequently, in each modulation period, the matchcondition between counter and duty-cycle registers is checked twice, at firstduring the run up phase, then during the run down phase. In the occurrence ofa match, the state of the gate signal is toggled.

The result of this mode of operation is a stream of gate pulses that aresymmetrically allocated within the modulation period, at least in the absence ofany perturbation.

Interrupt requests are generated by the timer at the beginning and at the half ofthe modulation period, to allow proper synchronization with other controlfunctions, e.g. with the sampling process.



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t

t

t

TS

Timer interrupt request

Gate signal

Timer count

Programmed duty-cycle


Digital PWM: double update implementation



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t

cpk

t

VMO(t)

c(t) m(t)

ms(t)

TS

c(t), m(t)

TS/2

m(t)+

-

ms(t)

c(t)

VMO(t)ZOH

+==

2

)1(2

2

1

)(

)()(

ss TDsT

sD

pk

MO eecsM

sVsPWM


Digital PWM: double update implementation



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This modulator implementation can be analyzed as well using a sample andhold equivalent. In this case, the sampling frequency is set to the double of themodulation frequency. The analysis proceeds following the same approach wehave used for the basic modulator implementation.

Interestingly, the transfer function we can derive in this case presents a similarstructure with respect to the symmetric pulse modulators one. However, themodulators phase lag in this case turns out to be equal to:

which is exactly of the previously obtained one. This suggests thegeneralization of the technique, leading to the so-called multi-sampling PWMimplementations.

( )

4

T

c2

eejPWM S

pk

2TD1j

2TDj SS

=

+=

arg))(arg(



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Digital PWM: multi-sampled implementation

t

c(t), m(t)

cpk

t

VMO(t)

c(t)

m(t)

ms(t)

Tsample

m(t)+

-

ms(t)

c(t)

VMO(t)ZOH

TS/N

dst

pk

ec1)s(PWM = SSd T

N)ND(floorDTt =where

Trailing edge delay Multi-sampling effect



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The equivalent delay is equal to the one found for the conventional trailingedge implementation, reduced by the so-called multi-sampling effect.

It is interesting to observe that, as N tends to infinity, the equivalent delaytends to zero, which is consistent with a continuous time, naturally sampledimplementation of the modulator, where the sample and hold effect is notpresent.

Multi-sampling presents some limitations as well, namely:

- need for proper filtering of the switching noise;- need for non conventional hardware;- generation of dead bands.

Research investigates possible means to overcome the limitations and fullyexploit the advantages of multi-sampling.



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m(t), c(t)

tTS

Generation of dead bands.

Vertical intersection: themodulator gain is zero.

Horizontal intersection: themodulator gain is 1/cpk.

1

2



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[3] L. Corradini, P.Mattavelli, Modeling of Multisampled Pulse Width Modulators forDigitally Controlled DCDC Converters, IEEE Trans. on Power Electronics, Vol. 23, No.4, July 2008, page(s) 1839-1847.

The presence of zero gain regions in the multi-sampled modulator trans-characteristic increases the settling time during transients and generates sub-harmonic oscillations in the steady state.

One possible way to compensate for these undesired effects consists insuitably synchronizing the sampling process and the modulator (i.e. the carrier

wave) so that only horizontal intersections are allowed to take place [3].




Th h


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Three phase systems

What we have just seen for single phase converters can be almost identicallyapplied to three phase systems. When the three phase converter ischaracterized by four wires, i.e. three phases plus neutral, the application isstraightforward, since a four wire three phase system is totally equivalent tothree independent single phase systems. Of course, this particular situation

does not deserve any further discussion. On the contrary, we need to apply alittle more caution when we are dealing with a three phase system withinsulated neutral, i.e. with a three-wire, three-phase system.

The transformationrepresents a very useful tool for the analysis and themodelling of three phase electrical systems. In general, a three phase linearelectric system can be properly described in mathematical terms only bywriting a set of tri-dimensional dynamic equations (integral and/or differential),providing a self consistent mathematical model for each phase. In some casesthough, the existence of physical constraints makes the three models notindependent from each other. In these circumstances the order of themathematical model can be reduced without any loss of information. We willsee a remarkable example of this in the following.


Th h t


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Three phase systems

Supposing that it is physically meaningful to reduce the order of themathematical model from three to two dimensions, transformationrepresents the most commonly used relation to perform the reduction of order.

To explain how it works we can consider a tri-dimensional vector [xa, xb, xc]

that can represent any triplet of systems electrical variables (voltages orcurrents). We can now consider the following linear transformation, ,

that, in geometrical terms, represents a change from the set of reference axes

denoted as abcto the equivalent one indicated as .

=

=

c

b

a

c

b

a

x

x

x

212121

23230

21211

32

x

x

x

x

x

x


Transformation


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[ ] [ ] [ ] }100,010,001{ TTTabc=

[ ] [ ] [ ] }212121,23230,21211{32TT

T

=

This change of reference axes takes place because the standard R3 orthonormal baseBabc

Transformation

is replaced by the new base B

The Bbase is once again orthonormal, i.e. its vectors have unity norm and areorthogonal to one another, thanks to the presence of the coefficient . Orthonormality

implies that: i) the inverse of the transformation is equal to the matrix transposed and ii)the computation of electrical powers is independent from the transformation ofcoordinates.

32


Transformation


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a

b

c

xa+ xb+xc= 0

a

b

c

The transformation has an additional, interesting property, that becomes clear whenwe take into account the following condition

whose meaning is to operate the restriction of the tri-dimensional space to aplane (Fig. 4.1.1.a).

0x0xxx cba ==++

Transformation


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Transformation


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Transformation

)32t(sinUe

)32t(sinUe

)t(sinUe

Mc

Mb

Ma

+=

=

=

Considering the following example :

We get:

)t(cosU2

3e

)t(sinU

2

3e

M

M

=

=


Space Vector Modulation - SVM


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LSa RSaESa

+

LSb RSb ESb+

LSc RSc

ESc

+

+-

VDC

Va

N

G

Vb

Vc

Ia

Ib

Ic


We can consider a typical three phase voltage source inverter and represent the possibleoutput voltage configurations as vectorson the plane .




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+

-

VDC

Va

G

Vb

Vc

Vector 100: Va= VDCVb=0 Vc=0

V100

Space Vector Modulation SVM




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+- VDC

Va

G

Vb

Vc

Vector 110: Va= VDCVb = VDCVc = 0

V110

Space Vector Modulation SVM




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+- VDC

Va

G

Vb

Vc

Vector 010: Va= 0 Vb= VDCVc=0

V010

Space ecto odu at o S




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+- VDC

Va

G

Vb

Vc

Vector 011: Va= 0 Vb = VDCVc = VDC

V011

p




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+- VDC

Va

G

Vb

Vc

Vector 001: Va= 0 Vb= 0 Vc= VDC

V001

p


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+- VDC

Va

G

Vb

Vc

Vector 111: Va= VDC Vb = VDCVc = VDC

V111




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+- VDC

Va

G

Vb

Vc

Vector 000: Va= 0 Vb = 0 Vc = 0

V000




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V110

V100

V1

V2

V110

V100

V1=1V110

V2=2V100V3=3V000

V*

V*

The procedure of Space Vector Modulation can be explained referring to the followingfigure:




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110

2

2

100

1

1

V

V

V

Vrr ==

1321

=++

*

21111311021001oVVVVVVV =+=++=r

The basic relations, used to compute the vector duty-cycles are the following:

Considering that the sum of the three duty-cycles has to be 1, i.e. the whole modulationperiod must be occupied, we can derive the third of them, referred to the zero vector:

The average voltage vector generated by the inverter is therefore:




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2

V15.1

2

V

3

2U

2

3V

3

2U

2

3 DCDCMMAXDCMMAX ==

It can be interesting to identify the locus of the constant amplitude rotating referencevectors that can be generated by the inverter without distortion.

This is represented by the circle inscribedin the vector hexagon. It is easy to verify that

every vector that lays inside the circle generates a valid 1, 2, 3, triplet. Instead, a vector

that lays partially outside the circle cannot be generated by the inverter, because the sumof the corresponding 1, 2, 3becomes greater than unity.

This situation is called inverter saturation and generally causes output voltage distortion.

It is easy to calculate the amplitude UMMAX of the voltage triplet that corresponds to arotating vector having an amplitude equal to the radius of the inscribed circle. We find:




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V110

V100

DCV2

1

DCV2

1

V111

V000

V010V011

V001

V101

Performing SVM, what is used to synthesize the desired output voltage vector is notthesuperposition of vectors laying on plane . A more realistic representation of the inverteroutput vectors, that puts into evidence their component, is shown here:




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The above observation means that SVM implies a particular modulation of the voltagebetween nodes N and G, V

NG. This is due to the common mode component of the

inverter output voltage vectors. Indeed, it is easy to demonstrate that, in case of asymmetrical load structure, almost always encountered in practice, V

NGis

instantaneously and exactly equal to the component of the inverter output voltage.

The most important implication of this fact is that the phase to neutral voltage of theload will always be insensitive to any common mode component of the inverter outputvoltage, i.e. one can freely add common mode components to the vector, withoutperturbing the load voltage.

This is exactly what SVM implicitly does. Its effect, from the inverters standpoint, canbe proved to be very similar to that of third harmonic injection, sometimes employed inanalog three phase PWM implementations.

An increase by 15% of the voltage amplitude range that corresponds to a linearconverter operation, i.e. to the absence of any saturation phenomenon, is obtained, asclearly demonstrates.




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Z1x

Z1y

12

3

4 5 6

Z2y

Z2x

Z3y

Z3x

We consider now a possible implementation algorithm for space vector modulation, thatcan be directly programmed into a microcontroller or digital signal processor. The firstissue in SVM implementation is the identification of the hexagon sector where thereference vector is laying.

This can be done by implementing once again a base change from the referenceframe to a new set of three different reference frames.




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=

3

20

3

11

M1

=

3

11

3

11

M2

=

3

11

3

20

M3

As can be seen, each frame refers to a particular couple of hexagon sectors. The methodwe propose simply requires the projection of the inverter output voltage reference vectoronto each one of the three hexagon reference frames. This is easily implemented with thefollowing set of reference base change matrixes:

that map the orthogonal set of axes and onto the three, non-orthogonal sets Z. It isinteresting to notice that the algorithm required to implement the three projections is quitesimple.




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Z1xZ

1y< 0Yes No

Z2xZ

2y< 0

Yes

Z3x

> 0

Z1x

> 0Yes

1st

No

No

Z2x

> 0Yes No

NoYes

4th

2nd

5th

6th3

rd


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2T

V100 V110 V111 100V110 V

Va

Vb

Vc

3T1T2T

T T

1T000V

3T /2

000

T /2

VDC

VDC

VDC

s s

sssss

V

3 s s

While the following one minimizes the current ripple amplitude and, therefore, currentdistortion:



The typical organization of a three-phase VSI controller based on SVM is shown here


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LS RS

ES

++-

VDCIabc N

abc

V1

V2

SVM

I

I_ref+

-

-

+

I

I_ref

-controller

-controller

V*V*

DSP

The typical organization of a three-phase VSI controller based on SVM is shown here.

As can be seen, the controller takes advantage of the application of transformations tooperate on two sampled variables instead of three.

Digital Control of Switching Mode Power Supply Simone Buso 1

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