DIGITAL COMMUNICATIONS LAB MANUAL TDM system and recover back the original message signals through a...

DIGITAL COMMUNICATIONS LAB MANUAL

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BLOCK DIAGRAM OF TIME DIVISION MULTIPLEXING AND DEMULTIPLEXING


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EXPT. NO: DATE:

TIME DIVISION MULTIPLEXING AND DEMULTIPLEXING

AIM:

To transmit a multiplexed output of different message signals through a single channel

using TDM system and recover back the original message signals through a demultiplexer at

receiver end.

APPARATUS:

1. Time Division Multiplexing & Demultiplexing Trainer Kit

2. CRO

3. CRO Probes

4. Connecting wires (or) Patch cards

THEORY:

The Sampling Theorem provides the basis for transmitting the information contained in a

band limited message signal m (t) as a sequence of samples of m (t) taken uniformly at a rate that

is usually slighter higher than the nyquist rate. An important feature of the sampling process is a

conservation of time. That is, the transmission the message samples engages the communication

channel s for only a fraction of the sampling interval on a periodic basis, and in this way some of

the time interval between adjacent samples is cleared for use by other independent message

sources on a time shared basis. We there by obtain a time division multiplexing (TDM) system,

which enables the joint utilization of a common communication channel by a plurality of

independent message sources without mutual interference among them.

The TDM system is highly sensitive to dispersion in the common channel, that is, to variations of

amplitude with frequency or lack of proportionality of phase with frequency. Unlike FDM, TDM

is immune to non linearities in the channel as a source of cross talk. The reason for this is, the

different message signals are not simultaneously applied to the channel. The primary advantage

of TDM is that several channels of information can be transmitted simultaneously over a single

cable.


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BLOCK DIAGRAM:

CH 1 CH 1

CH 2 CH 2

CH 3 CH 3

: :

: :

CH 8

CH 8

OBSERAVATION TABLE:

AT TRANSMITTER SIDE (MUX):

S.NO CHANNEL TYPE OF

WAVE AMPLITUDE TIME PERIOD FREQUENCY

1

2

3

AT RECEIVER SIDE (DEMUX):

S.NO CHANNEL TYPE OF

WAVE AMPLITUDE TIME PERIOD FREQUENCY

1

2

3

8X1

TIME DIVISION

MULTIPLEXER

COMMON

CHANNEL

1X8

TIME DIVISION

DE

MULTIPLEXER


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In the circuit diagram the 555 timer is used as a clock generator. This timer is a highly

stable device for generating accurate time delays. In this circuit this timer generates clock signal,

which is of 100 KHz frequency (approximately). This clock signal is connected to the 74163 IC;

it is synchronous presentable binary counter. It divides the clock signal frequency into three parts

and those are used as selection lines for multiplexer and de-multiplexer. Inbuilt signal generator

is provided with sine, square and triangle outputs with variable frequency. These three signals

can be used as inputs to the multiplexer. IC 4051 is an 8 to 1 Analog Multiplexer. Again IC 4051

is wired as one to eight de-multiplexers. Demux input receives the data source and transmits the

data signals on different channels.

PROCEDURE:

1. Switch on Time division multiplexing and demultiplexing trainer kit.

2. Connect the sine wave to channel 1, square wave to channel 2 and triangle wave form to

Channel 3 terminals of n to 1 multiplexer.

3. Observe the Multiplexer output on channel 1 of a CRO.

4. Connect Mux output to Demux input.

5. Observe corresponding signal outputs at channel 2 of CRO.

PRECAUTIONS:

1 .Avoid loose Connections.

2. Switch off the power supply during connections

3. Waveforms must be noted carefully.

RESULT:

Three different message signals (square, sine & triangular waves) are transmitted at a

time through a single communication channel using TDM system and hence the TDM waveform

is observed and the amplitude and time periods of the three message signals are measured. The

Demultiplexed message signals at the receiver are observed and hence the time period and

amplitude of the waveforms are measured. From the measurements we can observe that the

amplitude and frequency values are the same at the receiver also.


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MODEL WAVEFORMS:

1. INPUT WAVEFORMS:-

2. OUTPUT WAVEFORMS:-


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VIVA QUESTIONS:

1. What is meant by multiplexing technique and what are the different types of

Multiplexers?

2. Briefly explain about TDM&FDM?

3. What is the transmission band width of a PAM/TDM signal?

4. Define crosstalk effect in PAM/TDM system?

5. What are the advantages of TDM system?

6. What are major differences between TDM&FDM?

7. Give the value of Ts in TDM system?

8. What are the applications of TDM system?

9. What is meant by signal overlapping?

10. Which type of modulation technique will be used in TDM?


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CIRCUIT DIAGRAM OF PULSE CODE MODULATION AND DEMODULATION


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EXPT. NO: DATE:

PULSE CODE MODULATION & DEMODULATION

AIM:

To convert an analog signal into a pulse digital signal using PCM system and to

convert the digital signal into analog signal using PCM demodulation system.

APPARATUS:

1. Pulse Code Modulation & Demodulation trainer kit

2. CRO

3. CRO Probes


THEORY:

In pulse code modulation (PCM) a message signal is represented by a sequence of coded

pulses, which is accomplished by representing the signal in discrete form in both time and

amplitude. The basic elements of a PCM system are shown below.

(a)Transmitter (MODULATION)

(b) Transmission Path (CHANNEL)


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MODEL WAVEFORMS:

FOR SINE INPUT


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(c) Receiver (DEMODULATION)

The basic operations performed in the transmitter of a PCM system are sampling,

quantizing and encoding. The low pass filter prior to sampling is included to prevent aliasing of

the message signal. The incoming message signal is sampled with a train of narrow rectangular

pulses so as to closely approximate the instantaneous sampling process. To ensure perfect

reconstruction of the message signal at the receiver, the sampling rate must be greater than twice

the highest frequency component W of the message signal in accordance with the sampling

theorem.

The quantizing and encoding operations are usually performed in the same circuit, which is

called an analog-to-digital converter. The same circuit, which is called and analog-to-digital

converter. The sampled version of the message signal is then quantized, thereby providing a new

representation of the signal that is discrete in both time and amplitude. In combining the process

of sampling and quantization, the specification of a continuous message (baseband) signal

becomes limited to a discrete set of values, but not in the form best suited to transmission. To

exploit the advantages of sampling and quantizing for the purpose of making the transmitted

signal more robust to noise, interference and other channel impairments, we require the use of an

encoding process to translate the discrete set of sample values to a more appropriate form of

signal.

Regeneration:

The most important feature of PCM system lies in the ability to control the effects of

distortion and noise produced by transmitting a PCM signal through a channel. This capability is

accomplished by reconstructing the PCM signal by means of a chain of regenerative repeaters

located at sufficiently closed spacing along the transmission route. As illustrated in figure below

three basic functions are performed by a regenerative repeater: equalization timing and decision

making.

REGENRATION

CIRCUIT

DECODER RECONSTRUCTION

FILTER

DESTINATION


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MODEL WAVEFORMS:

FOR DC WAVE


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Regeneration Repeater

The equalizer shapes the received pulses so as to compensate for the effects of amplitude

and phase distortion produced by the non ideal transmission characteristics of the channel.

The timing circuit provides a periodic pulse trainer, derived from the received pulses, for

sampling the equalized pulses at the instants of time where the signal to noise ratio is maximum.

Each sample so extracted is compared to predetermined threshold in the decision making device.

In each bit interval, a decision is then made whether the symbol is 1 or 0 on the basis of whether

the threshold is exceeded or not. If the threshold is exceeded, a pulse representing symbol ‘1’ is

transmitted. In the way, the accumulation of distortion and noise in a repeater span is completely

removed.

The basic operations in the receiver are regeneration of impaired signals, decoding and

reconstruction of the train of quantized samples. The first operation in the receiver is to

regenerate (i.e., reshape and cleanup) the received pulses one last time. These clean pulses are

then regrouped in to code words and decoded into a quantized PAM signal. The decoding

process involves generating a pulse, the amplitude of which is the linear sum of all the pulses in

the code word. The final operation in the receiver is to recover the message signal by passing the

decoder output through a low pass reconstruction filter whose cut-off frequency is equal to the

message band width W. Assuming that the transmission path is error free, the recovered signal

includes no noise with the exception of the initial distortion introduced by the quantization

process.

PROCEDURE:

1. Switch on Pulse code modulation and demodulation.

2. Connect the variable DC output to the Analog I/P of modulation section.

3. Connect the clock O/P of bit clock generator to the clock I/P of modulation Section.

4. By varying the variable DC O/P observe the PCM O/P on CRO.

5. Connect the AF output to Analog I/P of modulation section by removing variable DC O/P

6. Connect the PCM O/P to PCM I/P of demodulation section.

7. Observe the DAC O/P at channel 1 of CRO and observe the demodulated O/P at channel 2 of

CRO.


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OBSERVATIONS TABLE:

AC INPUT (SINE WAVE)

Name of the signal Amplitude Time period Frequency

Modulating (AF) Signal

Carrier Signal(Pulse)

PCM Signal

Digital data

Demodulated Signal

DC INPUT


Modulating (DC) Signal


PCM Signal

Digital data

Demodulated Signal


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PRECAUTIONS:




RESULT:

Hence the continuous time signal is converted into digital signal in transmitter side and in

the receiver side the original continuous signal is recovered back from the received PCM signal

are observed and plotted the appropriate waveforms

Thus PCM modulation and demodulation systems are act as A/D and D/A converters.

From the measurements we can observe that the amplitude and frequency values are the same at

the receiver also.


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VIVA QUESTIONS:

1. What is the expression for transmission bandwidth in a PCM system?

2. What is the expression for quantization noise/error in PCM system?

3. What are the applications of PCM?

4. What are the advantages of the PCM?

5. What are the disadvantages of PCM?

6. What is the statement of sampling theorem?

7. What is meant by Quantizing?

8. What is meant by Encoding?

9. What is the purpose of Regenerative Repeater in PCM?

10. What is the purpose of Reconstruction filter in Demodulator?


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CIRCUIT DIAGRAM OF DPCM

BLOCK DIAGRAM OF DPCM

MODULATION:

DEMODULATION:


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EXPT. NO: DATE:

DIFFERENTIAL PULSE CODE MODULATION & DEMODULATION

AIM:

To study the differential PCM modulation and demodulation by sending variable

frequency sine wave and variable DC signal input and plot the appropriate waveforms.

APPARATUS:

1. DPCM trainer kit

2. CRO

3. CRO Probes


THEORY:

If we know the past behavior of a signal up to a certain point in time, we may use

prediction to make an estimate of a future value of the signal. Suppose, a base band signal m (t)

is sampled at the rate fs =1/Ts to produce the sequence m (n) whose samples are Ts seconds

apart. It is possible to predict future values of the signal m (t), provides motivation for the

differential quantization scheme shown in fig. below.

MODULATION BLOCK

In this scheme, the input signal to the quantizer is the difference between the unquantized input

sample m (n) and a prediction of it, denoted by m^(n). This predicted value is produced by using

a linear prediction filter whose input, consists of a quantized version of the input sample m (n).


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MODEL WAVEFORMS:

FOR SINE WAVE

OBSERVATION TABLE:




DPCM Signal

Digital data

Demodulated Signal


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The difference signal e (n) is the prediction error, since it is the amount by which the prediction

filter fails to predict the input exactly. By encoding the quantizer output, we obtain a variant of

PCM known as DPCM. Irrespective of the properties of the prediction filter, the quantized

sample m q (n) at the prediction filter input differs from the original input sample m (n) by the

quantization error q (n). Accordingly if the prediction is good, the variance of the prediction

error e (n) will be smaller than the variance of m (n), so that a quantizer with a given number of

levels can be adjusted to produce a quantization error with a smaller variance than would be

possible if the input sample m (n) were quantized directly as in a standard PCM system.

The receiver for reconstructing the quantized version of the input is shown in fig. below.

DEMODULATION BLOCK

It consists of a decoder to reconstruct the quantized error signal. The quantized version of the

original input is reconstructed from the decoder output using the same prediction filter used in

transmitter. In the absence of channel noise, we find that the encoded signal at the receiver input

is identical to the encoded signal at the transmitter output. Accordingly, the corresponding

receiver output is equal to m q (n), which differs from the original input m(n) only by the

quantization error q(n) incurred as a result of quantizing the prediction error e(n).

From these analyses, we observe that, in a noise-free environment, the prediction filter in the

transmitter and receiver operates on the same sequence of samples m q (n). It is with the purpose

that a feedback path is added to the quantizer in the transmitter.

DPCM includes Delta Modulation as a special case. By comparing the DPCM system

with DM system, they are basically similar, except for two important differences: The use of a

one-bit (two-level) quantizer in the delta modulator and the replacement of the prediction filter

by a single delay element (i.e., zero prediction order).


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MODEL WAVEFORMS:

FOR DC INPUT

OBSERVATION TABLE:


Modulating (DC) Signal


DPCM Signal

Digital data

Demodulated Signal


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PROCEDURE:

1. Switch on Differential Pulse code modulation and demodulation trainer kit.

2. Connect the variable DC output to the Analog I/P of modulation section.

3. Measure the clock O/P present in the modulation Section.

4. By varying the variable DC O/P observe the DPCM O/P on CRO.

5. Connect the AF output to Analog I/P of modulation section by removing variable DC O/P

6. Connect the DPCM O/P to DPCM I/P of demodulation section.

7. Observe the DAC O/P at channel 1 of CRO and observe the demodulated O/P at channel 2 of

CRO.

PRECAUTIONS:




RESULT:

Hence differential PCM modulation and demodulation are observed by sending variable

frequency sine wave and variable DC signal input and plotted the appropriate waveforms. From

the measurements we can observe that the amplitude and frequency values are the same at the

receiver also.


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VIVA QUESTIONS

1 .What is the differences between PCM and DPCM?

2 .What is the bandwidth of DPCM?

3 .What is the use prediction filter in DPCM?

4. What are the applications of PCM?

5. What are the advantages of the DPCM?

6. What are the disadvantages of DPCM?


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CIRCUIT DIAGRAM OF DELTA MODULATOR:

CIRCUIT DIAGRAM OF DELTA DE-MODULATOR:


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EXPT. NO: DATE:

DELTA MODULATION AND DEMODULATION

AIM:

To transmit an analog message signal in its digital form and again reconstruct back the

Original analog message signal at receiver by using Delta modulator.

APPARATUS:

1. Delta modulation and demodulation trainer kit

2. CRO

3. CRO Probes


THEORY:

Delta modulator is an advanced version of PCM system, so it is also known as ‘Single bit

PCM system’. It generates the output signal by comparing the input signal with its quantized

approximated output i.e. if the step size increases to+ it gives binary value ‘1’ and if step

downs to -it gives binary value ‘o’. In this way it reduces the transmission channel band width.

Rather than quantizing the absolute value of the input analog waveform, delta modulation

quantizes the difference between the current and the previous step, as shown in the block

diagram

Block diagram of a Δ-modulator/demodulator

The modulator is made by a quantizer which converts the difference between the input signal and

the average of the previous steps. In its simplest form, the quantizer can be realized with a

comparator referenced to 0 (two levels quantizer), whose output is 1 or 0 if the input signal is


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BLOCK DIAGRAM OF DELTA MODULATION:

BLOCK DIAGRAM OF DELTA DEMODULATION:


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Positive or negative. It is also a bit-quantizer as it quantizes only a bit at a time. The demodulator

is simply an integrator (like the one in the feedback loop) whose output rises or falls with each 1

or 0 received. The integrator itself constitutes a low-pass filter.

In delta modulation, the transmitted data is reduced to a 1-bit data stream. Its main features are:

the analog signal is approximated with a series of segments

each segment of the approximated signal is compared to the original analog wave to

determine the increase or decrease in relative amplitude

the decision process for establishing the state of successive bits is determined by this

comparison

Only the change of information is sent, that is, only an increase or decrease of the signal

amplitude from the previous sample is sent whereas a no-change condition causes the

modulated signal to remain at the same 0 or 1 state of the previous sample.

PROCEDURE:

1. Switch on the experimental board.

2. Connect the clock signal of Bit clock generator to the bit clock input of Delta

Modulator circuit.

3. Connect modulating signal of the modulating signal generator to the modulating

Signal input of the Delta modulator.

4. Observe the modulating signal on Channel 1 of CRO

5. Observe the Delta modulator output on channel 2 of CRO

6. Connect the DM O/P of modulator to the DM I/P of Demodulator circuit

7. Connect the clock signal to the Bit clock I/P of Demodulator circuit.

8. Observe the demodulated O/P on channel 2 of CRO

9. Connect the demodulated O/P to the filter input of demodulator circuit.

10. Observe the demodulated O/P with filter on CRO

PRECAUTIONS:




http://en.wikipedia.org/wiki/Information


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MODEL WAVEFORMS:

OBSERVATIONS TABLE:




Staircase Signal

DM Signal

Demodulated Signal


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RESULT:

The digital data output of a given analog message signal is observed by using delta

modulator and demodulated the original analog message signal from the modulated signal using

delta demodulator. The staircase waveform according to digital data is obtained from the analog

message signal. From the measurements we can observe that the amplitude and frequency values

are the same at the receiver also.


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VIVA QUESTIONS:

1. What are the advantages of Delta modulator?

2. What are the disadvantages of delta modulator?

3. How to overcome slope overload distortion?

4. How to overcome Granular or ideal noise?

5. What are the differences between PCM & DM?

6. Define about slope over load distortion?

7. What is the other name of Granular noise?

8. What is meant by staircase approximation?

9. What are the disadvantages of Delta modulator?

10. Write the equation for error at present sample?


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FSK MODULATION & DEMODULATION CIRCUIT DIAGRAM


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EXPT. NO: DATE:

FREQUENCY SHIFT KEYING

AIM:

To generate the frequency shift keying signal for a given binary data at modulator end

and also demodulate the original data input from the received FSK input at the receiver end.

APPARATUS:

1. FSK modulation & Demodulation trainer kit

2. Function generator

3. CRO

4. Connecting wires and probes.

THEORY:

In FSK, the waveform is generated by switching the frequency of the carrier between

two values corresponding to the binary information which is to be transmitted. Here the carrier

frequency varies from lowest to highest point i.e. carrier swing is known as Frequency shift

keying. FSK signaling schemes find a wide range of applications in low speed digital data

transmission systems.

Frequency-shift keying (FSK) is a frequency modulation scheme in which digital information

is transmitted through discrete frequency changes of a carrier wave.[1]

The simplest FSK is

binary FSK (BFSK). BFSK uses a pair of discrete frequencies to transmit binary (0s and 1s)

information.[2]

With this scheme, the "1" is called the mark frequency and the "0" is called the

space frequency

Minimum-shift keying

Minimum frequency-shift keying or minimum-shift keying (MSK) is a particular spectrally

efficient form of coherent FSK. Consequently, the waveforms that represent a 0 and a 1 bit differ

by exactly half a carrier period. The maximum frequency deviation is δ = 0.25 fm, where fm is the

maximum modulating frequency. As a result, the modulation index m is 0.25. This is the smallest

FSK modulation index that can be chosen such that the waveforms for 0 and 1 are orthogonal. A

variant of MSK called GMSK is used in the GSM mobile phone standard.

http://en.wikipedia.org/wiki/Frequency_modulation

http://en.wikipedia.org/wiki/Carrier_wave

http://en.wikipedia.org/wiki/Frequency-shift_keying#cite_note-1

http://en.wikipedia.org/wiki/Frequency-shift_keying#cite_note-2

http://en.wikipedia.org/wiki/Modulation_index

http://en.wikipedia.org/wiki/Orthogonal

http://en.wikipedia.org/wiki/GMSK

http://en.wikipedia.org/wiki/GSM

http://en.wikipedia.org/wiki/Mobile_phone


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BLOCK DIAGRAM:

FSK MOUDULATION:

FSK DEMODULATION:


37

Audio FSK

Audio frequency-shift keying (AFSK) is a modulation technique by which digital data is

represented by changes in the frequency (pitch) of an audio tone, yielding an encoded signal

suitable for transmission via radio or telephone. Normally, the transmitted audio alternates

between two tones: one, the "mark", represents a binary one; the other, the "space", represents a

binary zero.

AFSK differs from regular frequency-shift keying in performing the modulation

at baseband frequencies. In radio applications, the AFSK-modulated signal normally is being

used to modulate an RF carrier (using a conventional technique, such as AM or FM) for

transmission.

APPLICATIONS:

AFSK is used in the U.S. based Emergency Alert System to notify stations of the type of

emergency, locations affected, and the time of issue without actually hearing the text of the alert.

AFSK is also used in the United States' Emergency Alert System to transmit warning

information. It is used at higher bitrates for Weather copy used on Weatheradio by NOAA in the

U.S.

The CHU shortwave radio station in Ottawa, Canada broadcasts an exclusive digital time

signal encoded using AFSK modulation

FSK is commonly used in Caller ID and remote metering applications: see FSK standards for use

in Caller ID and remote metering for more details

PROCEDURE:

1. Connect the output of the carrier output provided on kit to the input of carrier input 1 terminal.

2. Also connect one of the Data output to the Data input terminal provided on kit.

3. Connect sine wave of certain frequency to the carrier input 2 terminal.

4. Switch ON function generator and FSK modulation and Demodulation kit.

5. Observe the FSK output by connecting it to CRO. Thus FSK modulation can be achieved.

6. For FSK Demodulation, Connect FSK output terminal to the FSK input terminal of demod.

7. Observe the Demodulated wave at Demodulated output terminal by connecting it to CRO.

http://en.wikipedia.org/wiki/Modulation

http://en.wikipedia.org/wiki/Digital

http://en.wikipedia.org/wiki/Data

http://en.wikipedia.org/wiki/Frequency

http://en.wikipedia.org/wiki/Pitch_(music)

http://en.wikipedia.org/wiki/Sound

http://en.wikipedia.org/wiki/Radio

http://en.wikipedia.org/wiki/Telephone

http://en.wikipedia.org/wiki/Binary_numeral_system

http://en.wikipedia.org/wiki/Baseband

http://en.wikipedia.org/wiki/Radio_frequency


http://en.wikipedia.org/wiki/Amplitude_modulation

http://en.wikipedia.org/wiki/Frequency_modulation

http://en.wikipedia.org/wiki/Emergency_Alert_System

http://en.wikipedia.org/wiki/United_States

http://en.wikipedia.org/wiki/Emergency_Alert_System

http://en.wikipedia.org/wiki/Weatheradio

http://en.wikipedia.org/wiki/NOAA

http://en.wikipedia.org/wiki/CHU_(callsign)

http://en.wikipedia.org/wiki/Shortwave_radio

http://en.wikipedia.org/wiki/Ottawa

http://en.wikipedia.org/wiki/Canada

http://en.wikipedia.org/wiki/Caller_ID

http://en.wikipedia.org/wiki/Remote_metering

http://en.wikipedia.org/wiki/FSK_standards_for_use_in_Caller_ID_and_remote_metering

http://en.wikipedia.org/wiki/FSK_standards_for_use_in_Caller_ID_and_remote_metering


38

MODEL WAVEFORMS:

OBSERVATIONS TABLE:


Modulating Signal

Digital data

Carrier Signal

(HF sine wave)

Carrier Signal

(LF sine wave)

FSK Signal

Demodulated Signal

Digital data


39

PRECAUTIONS:




RESULT:

The FSK signal is observed for a given input data and the demodulated data is observed

from the received FSK signal. Hence plotted the appropriate waveforms.

And also observed, the Frequency is shifted when the input data is keying from o to 1 and

vice versa in the modulated FSK signal and retrieved the original input data from the received

FSK signal. From the measurements we can observe that the amplitude and frequency values are

the same at the receiver.


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41

VIVA QUESTIONS:

1. Define Binary FSK signal?

2. What is meant by carrier swing?

3. Define Frequency deviation of FSK signal?

4. What are the advantages of this FSK signal?

5. Give the differences between FSK & FM?

6. Give the necessary equations for BFSK?

7. What are the applications of FSK?

8. What are the disadvantages of this FSK signal?\


42

CIRCUIT DIAGRAM OF PSK MODULATOR

CIRCUIT DIAGRAM OF PSK DE MODULATOR


43

EXPT. NO: DATE:

PHASE SHIFT KEYING

AIM:

To generate the phase shift keying signal for the given binary data at modulator end &

also demodulate the PSK signal to receive the transmitted binary data.

APPARATUS:

1. PSK Modulation & Demodulation trainer kit

2. CRO

3. CRO Probes


THEORY:

Phase shift keying or discrete phase modulation is another technique available for

communicating digital information over band pass channels. In PSK signaling schemes the

waveforms s1(t) = -Acoswct & S2(T) = Acoswct are used to convey binary digits 0& 1

respectively. The binary PSK waveform Z (t) can be described by, Z (t) = D (t) Acoswct .

Where D (T) is a random binary waveform with period Tb& levels -1&1. The only difference

b/w the ASK&PSK waveform is that in the ASK scheme the carrier is switched on &off whereas

in the PSK scheme the carrier is switched b/w levels +A & -A.

The differentially coherent PSK signaling scheme makes use of a clever technique

designed to get around the need for a coherent reference signal at the receiver.

Phase-shift keying (PSK) is a digital modulation scheme that conveys data by changing, or

modulating, the phase of a reference signal (the carrier wave).

Any digital modulation scheme uses a finite number of distinct signals to represent digital data.

PSK uses a finite number of phases; each assigned a unique pattern of binary digits. Usually,

each phase encodes an equal number of bits. Each pattern of bits forms the symbol that is

represented by the particular phase. The demodulator, which is designed specifically for the

symbol-set used by the modulator, determines the phase of the received signal and maps it back

to the symbol it represents, thus recovering the original data. This requires the receiver to be able

http://en.wikipedia.org/wiki/Digital

http://en.wikipedia.org/wiki/Modulation

http://en.wikipedia.org/wiki/Data#Uses_of_data_in_computing

http://en.wikipedia.org/wiki/Phase_(waves)

http://en.wikipedia.org/wiki/Signal_(information_theory)


http://en.wiktionary.org/wiki/finite

http://en.wikipedia.org/wiki/Bit

http://en.wikipedia.org/wiki/Demodulator


44

BLOCK DIAGRAM:

PSK MODULATOR:

PSK DEMODULATOR:


45

to compare the phase of the received signal to a reference signal — such a system is termed

coherent (and referred to as CPSK).

BPSK (also sometimes called PRK, phase reversal keying, or 2PSK) is the simplest form

of phase shift keying (PSK). It uses two phases which are separated by 180° and so can also be

termed 2-PSK. It does not particularly matter exactly where the constellation points are

positioned, and in this figure they are shown on the real axis, at 0° and 180°. This modulation is

the most robust of all the PSKs since it takes the highest level of noise or distortion to make the

demodulator reach an incorrect decision. It is, however, only able to modulate at 1 bit/symbol (as

seen in the figure) and so is unsuitable for high data-rate applications.

BPSK is functionally equivalent to 2-QAM modulation.

All convey data by changing some aspect of a base signal, the carrier wave (usually a sinusoid),

in response to a data signal. In the case of PSK, the phase is changed to represent the data signal.

There are two fundamental ways of utilizing the phase of a signal in this way:

By viewing the phase itself as conveying the information, in which case the demodulator must

have a reference signal to compare the received signal's phase against; or

By viewing the change in the phase as conveying information — differential schemes, some of

which do not need a reference carrier (to a certain extent).

PROCEDURE:

1. Switch on Physitech’s PSK modulation and demodulation trainer.

2. Connect the carrier O/P of carrier generator to the carrier I/P of modulator.

3. Connect the data O/P of Data generator to the Data I/P of Modulator.

4. Connect CRO terminals to the PSK O/P of modulator.

5. Observe the PSK modulator output on channel 1 of CRO.

6. Connect the PSK O/P of modulator to the PSK I/P of demodulator.

7. Connect the carrier O/P of carrier generator to carrier I/P of demodulator.

8. Observe the PSK demodulated output on channel 2 of CRO by connecting the second channel

terminals to Demod O/P of demodulator.

http://en.wikipedia.org/wiki/Quadrature_amplitude_modulation


http://en.wikipedia.org/wiki/Sine_wave

http://en.wikipedia.org/wiki/Phase_(waves)

http://en.wikipedia.org/wiki/Demodulator

http://en.wikipedia.org/wiki/Phase-shift_keying#Differential_encoding

http://en.wikipedia.org/wiki/Phase-shift_keying#Differential_phase-shift_keying_.28DPSK.29


46

OUTPUT WAVEFORMS:

OBSERVATIONS TABLE:


Modulating Signal

Digital data

Carrier Signal

(HF sine wave)

PSK Signal

Demodulated Signal

Digital data


47

PRECAUTIONS:




RESULT:

The PSK signal is observed for a given input data and the demodulated data is observed

from the received PSK signal. Hence plotted the appropriate waveforms.

And also observed that the PHASE is shifted when the input data is keying from o to 1

and vice versa in the modulated PSK signal and retrieved the original input data from the

received PSK signal. From the measurements we can observe that the amplitude and frequency

values are the same at the receiver also.


48


49

VIVA QUESTIONS:

1. What is the bandwidth requirement of BPSK?

2. What is the expression for error probability of BPSK reception using coherent

matched filter detection?

3. What are the draw backs of BPSK?

4. Draw the Power spectral density of BPSK?

5. What are the major differences between DPSK&BPSK?

6. What are the advantages of BPSK over a PSK signal?

7. Give the necessary equations for BPSK?

8. What are the various types of PSK?


50

CIRCUIT DIAGRAM OF DPSK MODULATOR:

CIRCUIT DIAGRAM OF DPSK DE MODULATOR:


51

EXPT. NO: DATE:

DIFFERENTIAL PHASE SHIFT KEYING

AIM:

To generate differentially phase shift keying signal at modulator end and also demodulate

the original binary data from the DPSK signal at the demodulator end.

APPARATUS:

1. DPSK modulation and demodulation trainer kit

2. CRO

3. CRO Probes


THEORY:

We may view DPSK as the non-coherent vision of PSK. It eliminates the need for

adjustment coherent reference signal at the receiver by connecting two basic operations at the

transmitter.

1. Differential encoding at the transmitter.

2. Phase shift keying

Hence differential encoding means the given input data will be done EX-OR operation

with the previous encoded bit. Now the process of Phase shift keying will be done for both

differentially encoded data and the carrier signal.

Differential encoding

Differential phase shift keying (DPSK) is a common form of phase modulation that conveys data

by changing the phase of the carrier wave. As mentioned for BPSK and QPSK there is an

ambiguity of phase if the constellation is rotated by some effect in the communications through

which the signal passes. This problem can be overcome by using the data to change rather

than set the phase. For example, in differentially encoded BPSK a binary '1' may be transmitted

by adding 180° to the current phase and a binary '0' by adding 0° to the current phase. Another

variant of DPSK is Symmetric Differential Phase Shift keying, SDPSK, where encoding would

be +90° for a '1' and -90° for a '0'.


52

BLOCK DIAGRAM:

DPSK MODULATOR:

DPSK DEMODULATOR:


53

In differentially encoded QPSK (DQPSK), the phase-shifts are 0°, 90°, 180°, -90° corresponding

to data '00', '01', '11', '10'. This kind of encoding may be demodulated in the same way as for

Non-differential PSK but the phase ambiguities can be ignored. Thus, each received symbol is

demodulated to one of the points in the constellation and a comparator then computes the

difference in phase between this received signal and the preceding one. The difference encodes

the data as described above. Symmetric Differential Quadrature Phase Shift Keying (SDQPSK)

is like DQPSK, but encoding is symmetric, using phase shift values of -135°, -45°, +45° and

+135°.

The modulated signal is shown below for both DBPSK and DQPSK as described above. In the

figure, it is assumed that the signal starts with zero phase, and so there is a phase shift in both

signals at .

Timing diagram for DBPSK and DQPSK. The binary data stream is above the DBPSK signal.

The individual bits of the DBPSK signal are grouped into pairs for the DQPSK signal, which

only changes every Ts = 2Tb.

Analysis shows that differential encoding approximately doubles the error rate compared to

ordinary -PSK but this may be overcome by only a small increase in . Furthermore,

this analysis (and the graphical results below) are based on a system in which the only corruption

is additive white Gaussian noise(AWGN). However, there will also be a physical channel

between the transmitter and receiver in the communication system. This channel will, in general,

introduce an unknown phase-shift to the PSK signal; in these cases the differential schemes can

yield a better error-rate than the ordinary schemes which rely on precise phase information.

For a signal that has been differentially encoded, there is an obvious alternative method of

demodulation.

http://en.wikipedia.org/wiki/Comparator

http://en.wikipedia.org/wiki/AWGN


54

MODEL WAVE FORMS:

OBSERVATIONS TABLE:


Modulating Signal

Digital data

Carrier Signal

(HF sine wave)

DPSK Signal

Demodulated Signal

Digital data


55

PROCEDURE:

1. Switch on differential phase shifting keying trainer.

2. Connect the carrier output of carrier generator to the 13th pin of CD4051 (Analog mux) of

Modulator.

3. Connect the bit clock output to the Bit clock input at pin 3 of 7474(8 – bit converter) of

Modulator.

4. Connect the data output of data generator to the input of modulator circuit.

5. Observe the differential data output at pin 2 of 7474 IC on channel; 1 of CRO.

6 .Observe the DPSK modulated output on channel 2 of CRO

7 .During demodulation, connect the DPSK modulated output to the DPSK I/P

Of Demodulator.

8 .Connect the Bit clock O/P to the Bit clock I/P of Demodulator and also connect the carrier

O/P to the carrier I/P of demodulator.

9 .Observe the demodulated data O/P at demodulated O/P of Demodulator.

10. The frequency of modulation data signal should be equal to the demodulated O/P.

PRECAUTIONS:




RESULT:

The DPSK signal is observed for a given input data and the demodulated data is observed

from the received DPSK signal. Hence plotted the appropriate waveforms.

And also observed that the PHASE is shifted when the DIFFERENTIAL input data is keying

from o to 1 and vice versa in the modulated DPSK signal and retrieved the original input data

from the received DPSK signal. From the measurements we can observe that the amplitude and

frequency values are the same at the receiver also.


56


57

VIVA QUESTIONS:

1. What is the difference between PSK&DPSK?

2. What is the band width requirement of a DPSK?

3. Explain the operation of DPSK detection?

4. What are the advantages of DPSK?

5. What is meant by differential encoding?

6. In Differential encoding technique which type of logic gates are used?

7. Is there any change in the output data when the starting reference bit is changed?


58

BLOCK DIAGRAM OF COMPANDING:

Figure 1

EXPERIMENT PROCEDURE:


59

EXPT. NO: DATE:

COMPANDING

AIM:

To observe the dynamic range of the signal and signal-to-Quantization noise ratio(S/Q)

without companding and with companding.

APPARATUS:

1. Companding trainer kit

2. Digital multimeters----2 no

3. Adapter

THEORY:

Companding is a compressing and expanding technique used in digital communications

system. With this technique we can improve noise performance at low level signals and improve

the dynamic range of the signal that can be handled by the channel. While coding the signal we

give higher resolution at low levels and lower resolution at high levels. This makes the signal

compressed in the code domain. By applying the reverse mapping at the decoding end we get

back the original signal. By allocating more bits at lower signals we reduce the quantization

noise (the noise created by the LSB).A-law and µ-law algorits encode 14-bit and 13-bit signed

linear PCM samples to logarithmic 8-bit samples. Companding is non uniform quantization. If

the quantizer characteristics is non linear and the step size is not constant instead if it is variable,

dependent on amplitude of input signal then the quantization is known as Non uniform

quantization. In this the step size is reduced with the reduction in the signal level.

Fig: Companding Model

Compressor

Uniform

quantizer Expander I/p O/p


60

OBSERVATIONS TABLE 1:

OBSERVATIONS TABLE 2:

Vin

Vout

Without Companding

A C Digital data input of

12-bit

Compressed

Code of 7-bit

Decoder o/p or

expanded data 12bit

Error

digital

Error/

Signal

A B C D=C-A E=D/A

Vin

Vout

With Companding

A C Digital data input of

12-bit

Compressed

Code of 7-bit

Decoder o/p or

expanded data 12bit

Error

digital

Error/

Signal

A B C D=C-A E=D/A


61

There are mainly two companding methods. They are:

1. µ- law Companding:

Z(x) = (sgnx) ln (1+µ|x|/xmax)/ln (1+µ) where 0≤|x|/xmax≤1.

2. A-law Companding:

1

1

PROCEDURE:

1. First observe the communication blocks in the signal chain.

2. Apply some dc voltage at the input by using the up/down keys, measure this with multimeter.

3. Note down the codes and the voltages as per the table given below.

4. Observe that higher quantization error Q/S in the case of linear mode compared to the

Companded mode.

PRECAUTIONS:




RESULT:

The dynamic range of the signal and signal-to-Quantization noise ratio(S/Q) is

improved with companding technique are observed.


62


63

VIVA QUESTIONS:

1. What is the use of Companding?

2. How many types of Companding are they & what are they?

3. Companding comes under which type of quantization ?(whether uniform or non uniform)

4. What are the blocks present in Compander?

5. What is the purpose of compressor and expander?


64

BLOCK DIAGRAM OF SOURCE ENCODER AND DECODER:


65

EXPT. NO: DATE:

SOURCE ENCODER AND DECODER

AIM:

To select information having some probability of occurrence of each symbol and

applying a source coding using one of the sources coding techniques i.e.huffman coding,

observing the size of the coded information, sending the minimized packet, decoding at the

receiving end getting back the full information sent.

APPARATUS:

1. Source encoder and decoder trainer kit

2. Adapter

THEORY:

A Conversion of the output of discrete memory less source (DMS) into a

sequence of binary symbols is called source coding. The device that performs this conversion is

called Source Encoder.

Objective of Source Coding is to minimize the average bit rate required for

representation of the source by reducing the redundancy of the information source.

Source coding is a technique of compressing the source information size based

on the probability of occurrence of each information symbol. Decoding is the reverse process to

get back the full source information. In everyday we employ this in transferring big files,

particularly image or voice files by zipping them and transferring to the destination and

unzipping at the destination.

Example: Huffman coding. This Huffman coding is a type of variable length codes. By using this

coding, frequently occurring symbol is assigned with less no. of bits in the code where as rarely

occurred symbol is assigned with large no. of bits. Source coding provides security to our

information.

The important parameters of Source encoder and decoder are:

1. Block size 3.Average data rate

2. Codeword length 4.Efficiency of the encoder


66


OBSERVATIONS TABLE:

Information

Text

Information bits

without coding

Information bits

with coding

Decoded

Information

ABRAKADABRA

DABRAKAABRA

ABRAKAABRAKA

DABRAKADABRA


67

PROCEDURE:

1. First observe the signal chain.

2. Now verify how many bits are taken to transmit ABRAKADABRA in normal and source

coded mode.

3. Apply an input symbol by pressing any one of the input symbol keys. Ex: To transmit a

letter ‘A’, press the key marked ‘A’.

4. Observe how many bits are transmitted for the given input symbol and note down the bits

being transmitted on the LEDS(1=RED, 0=GREEN)

5. Observe if the corresponding output LED is glows corresponding to the symbol pressed

at the input.

PRECAUTIONS:




RESULT:

The source code for the given information & the size of the coded information are

observed and also decoded the full information sent getting back at the receiving end.


68


69

VIVA QUESTIONS:

1. What is the purpose of source encoding and decoding?

2. What are the advantages of source coding?

3. What are the different source coding techniques used?

4. After source coding, message is in which form?

5. Define Shannon’s source coding theorem.


70

BLOCK DIAGRAM OF LINEAR BLOCK CODES ENCODER AND DECODER


71

EXPT. NO: DATE:

LINEAR BLOCK CODES ENCODER AND DECODER

AIM:

To observe that the errors received through a noisy channel can be removed by

employing the error detection and correction code.

APPARATUS:

1. Linear block codes encoder and decoder trainer kit

2. Adapter

THEORY:

Linear block codes are called as channel coding techniques which are used for the

purpose of detecting and correcting errors occurring in the communication channel. When

information is represented in blocks of ‘k’ bits we can add a few extra bits to the information bits

i.e. provide some redundancy and detect/correct the errors from the received data. More

redundancy we provide more correction we can have. Most common example of linear block

codes is Hamming code. By using hamming code technique with given no. of extra bits we can

extract maximum advantage of detection and correction. Hamming code (n.k) places symbols

represented by ‘n’ bits having ‘k’ information bits at a maximum distance from each other

allowing us to detect more errors correct more errors. In this experiment hamming (7, 4) is used

i.e. 4 information bits, 7 bits in the codeword and 3 parity bits (i.e.-k=7-4=3).

A code is linear if the sum of any two code vectors produces another code vector.

This shows that any code vector can be expressed as a linear combination of other code vectors.

k message bits n-k parity bits

Code word of length n bits

Fig: Structure of code word for a linear block code

M0, M1, M2, M3…………….MK-1 C0, C1, C2 ….CN-K-1


72


OBSERVATIONS TABLE:

Type of

error

4-bit Input

message(abcd)

3-Parity

bits(xyz)

Channel

Code(7bit)

(xyzabcd)

Decoder

Input

Decoder

Output

Error

detected

Error

corrected

No

error 1010

------ ------

Single

error 1000

Yes/No Yes/No

Double

error 0111

Yes/No Yes/No


73

PROCEDURE:

1. Observe the signal chain, i.e. the input stage, coding stage, transmission stage and the

Decode stage.

2. Put the mode selection switch in NORMAL/CODE mode and see the process and observe

Output.

3. Now select input message that is to be coded, by shifting the bits 0/1 by means of pressing the

Keys 0, 1, CLEAR.

4. Now the parity bits are added for the given input message by pushing the key ‘CODE A BIT’

Or by pushing ‘CODEALL’.

5. Now the message is coded and displayed in the transmission path. Now push the DECODE

Key, the channel code is decoded and displayed as the output message having no errors.

6. Due to channel noise, errors are introduced in the channel, now errors are introduced by

means of pressing the keys BITSEL and ERRSET. On every push of the BITSEL one bit is

Selected in the channel code, now if ERRSET is pressed the existing bit is inverted to make it

as an error.

7. Now again DECODE key is pressed to display output message. If an error is detected in the

Channel code ERRDETECTED LED glows, if an error is corrected from the channel code

ERRCORRECTED LED glows in the decoder output stage.

8. Observe the decoded output by introducing single and double errors in the channel code.

9. Note down the observations in a table given.

PRECAUTIONS:




RESULT:

Hence errors in the transmission channel can be detected and corrected with linear block

coding In (7,4) hamming code, single bit errors in any position are detected &corrected and

double errors are only detected but not corrected.


74


75

VIVA QUESTIONS:

1. What is the purpose of channel coding?

2. What are the advantages of channel coding?

3. What are the different channel coding techniques used?

4. After channel coding, message is in which form?

5. Define Shannon’s channel coding theorem.

6. How many errors can be detected and corrected using Linear Block Codes?

7. What is the decoding technique used for Linear Block Codes for getting original

message?


76

BLOCK DIAGRAM OF BINARY CYCLIC CODES ENCODER AND DECODER:


77

EXPT. NO: DATE:

BINARY CYCLIC CODES ENCODER AND DECODER

AIM:

To observe that the errors received through a noisy channel can be removed by

employing the error detection and correction code by using algebraic structure.

APPARATUS:

1. Binary cyclic codes encoder and decoder trainer kit

2. Adapter

THEORY:

An (n, k) linear code C is called a cyclic code if every cyclic shift of a code vector in C

is also a code vector in C. In coding theory cyclic codes are the subclass of linear block error

correcting codes that have convenient algebraic structures for efficient error detection and

correction. A linear code is called cyclic code if every cyclic shift of code vector produces some

other code vector i.e. the cyclic shift to the data in an array should also represent the data in the

same array. Example: array (0000) (0101) (1010) (1111)

Cyclic codes form an important subclass of linear codes. These codes are attractive for

two reasons: first, encoding and syndrome computation can be implemented easily by employing

Shift registers with feedback connections (or linear sequential circuits); and second, because they

have considerable inherent algebraic structure

Cyclic codes are of interest and importance because

• They posses rich algebraic structure that can be utilized in a variety of ways.

• They have extremely concise specifications.

• They can be efficiently implemented using simple shift registers.

• Many practically important codes are cyclic.

Error detection in cyclic codes is simpler but error correction is little complicated since the

combination logic circuits in error detector are complex


78


OBSERVATIONS TABLE:

Type of

error

4-bit Input

message(abcd)

3-Parity

bits(xyz)

Channel

Code(7bit)

(abcdxyz)

Decoder

Input

Decoder

Output

Error

detected

Error

corrected

No

error 1010

------ ------

Single

error 1000

Yes/No Yes/No

Double

error 0111

Yes/No Yes/No


79

PROCEDURE:

1. Observe the signal chain, i.e. the input stage, coding stage, transmission stage and the decode

Stage.


Output.

3. Now select input message that is to be coded, by shifting the bits 0/1 by means of pressing the

Keys 0, 1, CLEAR.






means of pressing the keys BITSEL and ERRSET. On every push of the BITSEL one bit is


As an error.






PRECAUTIONS:




RESULT:

Hence errors in the transmission channel can be detected and corrected with cyclic

coding i.e., single bit errors in any position are detected & corrected and double errors are only

detected but not corrected.


80


81

VIVA QUESTIONS:






6. How many errors can be detected and corrected using Binary Cyclic Codes?

7. What is the decoding technique used for Binary Cyclic Codes for getting original

message?


82

BLOCK DIAGRAM OF CONVOLUTION CODES ENCODER AND DECODER:


83

EXPT. NO: DATE:

CONVOLUTION CODES ENCODER AND DECODER

AIM:

To observe error correcting performance and decoding ability of convolution codes.

APPARATUS:

1. Convolution codes encoder and decoder trainer kit

2. Adapter

THEORY:

Convolution codes are one of the type of channel coding techniques used for the purpose

of detecting and correcting errors, occurring in the communication channel. Convolution coding

is a special case of error control coding. Unlike a block coder, convolution code is a memory

based device. Even though a convolution encoder accepts a fixed no. of message symbols and

produces a fixed no. of code symbols, its computations depend not only on the current set of

input symbols but on some of the previous input symbols.

Convolution code normally represented as (n, m, and k) where

n= no. of output bits ,m= no. of message bits ,k=no. of constraint bits/memory bits

Convolution codes are decoded by using Viterbi algorithm.

Convolutional codes are commonly described using two parameters: the code rate and the

constraint length. The code rate, k/n, is expressed as a ratio of the number of bits into the

convolutional encoder (k) to the number of channel symbols output by the convolutional encoder

(n) in a given encoder cycle. The constraint length parameter, K, denotes the "length" of the

convolutional encoder, i.e. how many k-bit stages are available to feed the combinatorial logic

that produces the output symbols. Closely related to K is the parameter m, which indicates how

many encoder cycles an input bit is retained and used for encoding after it first appears at the

input to the convolutional encoder. The m parameter can be thought of as the memory length of

the encoder. Convolutional codes are widely used as channel codes in practical communication


84


OBSERVATIONS TABLE:

Type of

error

4-bit

Input

message

Change

d input

(6-bit)

Channel

Code(12bit)

Decoder

Input

Output

Message

(6-bit)

4-bit

Output

message

Error

detected

Error

corrected

No

error 1010 101000

1111011110

00

1111011110

00

101000 1010 ----- ------

Single

error 1000 100000

Yes/No Yes/No

Double

error 0111 011100

Yes/No Yes/No


85

systems for error correction. The encoded bits depend on the current k input bits and a Trellis

coded modulation (TCM) and turbo codes are two such examples. In TCM, redundancy is added

by combining coding and modulation into a single operation. This is achieved without any

reduction in data rate or expansion in bandwidth as required by only error correcting coding

schemes.

Basic concepts of Convolution Codes

1. State Diagram Representation

2. Tree Diagram Representation

3. Trellis Diagram Representation

PROCEDURE:

1. Observe the signal chain, i.e. the input stage, coding stage, transmission stage and the decode

Stage.


Output.

3. Now select input message that is to be coded, by shifting the bits 0/1 by means of pressing to

Keys 0, 1, CLEAR.






Means of pressing the keys BITSEL and ERRSET. On every push of the BITSEL one bit is


As an error.







86


87

PRECAUTIONS:




RESULT:

Hence errors in the transmission channel can be detected and corrected in the receiver

using convolution coding and viterbi decoding.


88


89

VIVA QUESTIONS:






6. How many errors can be detected and corrected using Convolution Codes?

7. What is the decoding technique used for convolution codes for getting original message?

Digital Logic Design LAB MANUAL

1

EXP NO: 1

LOGIC GATES

AIM:

To study and verify the truth table of logic gates.

COMPONENTS REQUIRED:

• Logic gates (IC) trainer kit.

• Connecting patch chords.

• IC 7408, IC 7432, IC 7402.

THEORY:

Logic gates are the basic components in digital electronics. They are used to create

digital circuits and even complex integrated circuits. For example, complex integrated circuit

may bring already a complete circuit ready to be used - microprocessors and microcontrollers

are the best example - but inside them they were projected using several logic gates.

A gate is a digital electronic circuit having only one output but one or more inputs. The

output or a signal will appear at the output of the gate only for certain input-signal combinations.

There are many types of logic gates; such as AND, OR and NOT, which are usually called the

three basic gates. Other popular gates are the NAND and the NOR gates; which are simply

combinations of an AND or an OR gate with a NOT gate inserted just before the output signal.

Other gates include the XOR "Exclusive-OR" and the XNOR "Exclusive NOR" gates. All the logic

gates used in the exercises below are known as TTL (transistor-to-transistor) logic. These have

the convenient property that the output of any gate can be used directly as input to another gate.

All these TTL circuits are operated from a 5 V power supply, and the binary digits 0 and 1 are

represented by low and high voltages on the gate terminals.

Boolean algebra is a system of mathematical logic. It differs from both ordinary algebra and

the binary number system. Boolean algebra is formulated by a defined set of elements, together with

two binary operators ‘+’ and ‘.’ and unary operator ‘-‘.


2

LOGIC GATES:

AND gate

Fig: 2 input AND Gate

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A

dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes

omitted i.e. AB

OR gate

Fig: 2 input OR Gate

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are

high. A plus (+) is used to show the OR operation.

NOT gate

Fig: NOT Gate

The NOT gate is an electronic circuit that produces an inverted version of the input at its output.


3

It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A.

This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams

below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can

also be done using NOR logic gates in the same way.

Designing the Solution: Pin diagram of all the above gates are:

Figure-1: Pin Diagrams of IC 7408,7432,7404.


4

PROCEDURE:

Plug the chips you will be using into the breadboard. Point all the chips in the same

direction with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch

next to it on the chip package).

Connect +5V and GND pins of each chip to the power and ground bus strips on the

breadboard.

Make the connections as per the circuit diagram.

Switch on VCC and apply various combinations of input according to truth table.

Note down the output readings for logic gates for different combinations of inputs.

CONCLUSIONS

All the truth tables of basic logic gates are verified by using IC’s.


5

EXP NO : 2

IMPLEMENTATION OF UNIVERSAL GATES

AIM:

To realize individual Basic gates with Universal gates. i.e., NAND and NOR Gate.




• IC 7400, IC 7402.

THEORY:

A Logic Gate which can infer any of the gate among Logic Gates. NAND and NOR

Gates are called Universal Gates because all the other gates can be created by using these gates.

Universal Gates:

NAND gate

Fig: NAND Gate

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The

outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with

a small circle on the output. The small circle represents inversion.


6

NOR gate

Fig: NOR Gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all

NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on

the output. The small circle represents inversion.

Pin diagram of all the above gates are:

Fig: Pin Diagrams of IC 7400,04,7402.


7

Implementation of Logic Gates with Universal Gates:

NAND Gate Implementation:

AND Gate:

An AND gate is made by following a NAND gate with a NOT gate. It gives a NOT NAND, i.e.

AND.

OR Gate: An OR gate is made by following a NOT NAND gate with a NAND gate, i.e. OR.

NOT Gate:

A NOT gate is made by joining the inputs of a NAND gate together.

NOR Gate Implementation:

AND Gate:

An AND gate gives a 1 output when both inputs are 1; a NOR gate gives a 1 output only when


8

both inputs are 0. Therefore, an AND gate is made by inverting the inputs to a NOR gate.

OR Gate:

An OR function can be generated using only NOR gates. It can be generated by simply inverting

output of NOR gate.

NOT Gate:

An inverter can be made form a NOR gate by connecting all the inputs together i.e., a single

common input.


9

PROCEDURE:





breadboard.



Note down the output readings for the different combinations of inputs by NAND

and NOR logic gates.

.

CONCLUSIONS

All the truth tables of basic logic gates are verified by using universal Gates.


10

EXP NO : 3

REALIZATION OF BOOLEAN EXPRESSIONS

AIM:

To simplify the given expression and realize it using basic gates and also to verify De-Morgan Laws.




• IC 7408, IC 7432, IC 7402.

THEORY:

Simplification of Boolean functions is mainly used to reduce the gate count of a design.

Less number of gates means less power consumption, sometimes the circuit works faster and

also when number of gates is reduced, cost also comes down. There are many ways to simplify a

logic design.

Sum of Products:

A sum of products expression consists of several product terms logically added. A

product term is a logical product of several variables. The variables may or may not be

complemented. The following are the examples of sum of products expressions.

1. XY+X'Y+XY'

2. AB+ABC+BC'


11

Products of Sums: A product of sums expression consists of several sum terms logically

multiplied. A sum term is the logical addition of several variables. The variables may or may not

be complemented.

The following are examples of product of sums expressions:

A) (A+B) (A'+B')

B) A (B'+C') (B+C)

Canonical SOP and POS Forms:

When each term of a logic expression contains all variables, it’s said to be in the

canonical form. When a sum of products form of logic expression is in canonical form, each

product term is called minterm. Each minterm contains all variables. The canonical form of a

sum of products expression is also called minterm canonical form or standard sum of products.

Similarly, when a product of sums form of logic expression is in canonical form, each sum term

is called a maxterm. Each maxterm contains all variables. The canonical form of a product of

sums expression is also called maxterm canonical form or standard product of sums. When a

logic expression is not in the canonical form, it can be converted into canonical form. In the

canonical form there is uniformity in the expression, which facilitates minimization procedure.

The following are examples of the canonical form of sum of products expressions (or minterm

canonical form):

(i). Z = XY + XY′

(ii). F = XYZ′ + X′YZ + X′YZ′ + XY′Z + XYZ

In case of 2 variables, the maximum possible product terms are 4, for 3 variables, the possible

product terms are 8, for 4 variables 16, and for n variables, 2ⁿ. The following are examples of

canonical form of product of sums expressions (or maxterm canonical form).


12

(i). Z = (X + Y) (X + Y′)

(ii). F = (X′ + Y + Z′) (X′ + Y + Z) (X′ + Y′ + Z′).

In general, for an n-variable logical function there are 2n minterms and an equal number of

maxterms.

De Morgan's laws:

DeMorgan developed a pair of important rules regarding group complementation in

Boolean algebra. The complement of a group of terms, represented by a long bar over more than

one variable. The Complement of a product is equal to the sum of the complements.

Eg: (A+B)'=A'.B'

(A.B)'=A'+B'.

Pin Diagrams:


13

SUM OF PRODUCTS:

1. Z = ∑ (1,4,5,6,7)

Z = A'B'C + AB'C '+ AB'C +ABC'+ ABC

= (A' + A) B'C + AB'C' +AB(C' + C)

= B'C + AB'C' +AB

= B' (C +AC') +AB

= B' (C+C')(C+A) + AB

= B'C + AB' +AB

= B'C + A (B' + B)

= B'C + A

Symbolic Representations:

i) AND – OR – NOT Gate:

Truth Table:

A B C B' B'C B'C + A

0 0 0 1 0 0

0 0 1 1 1 1

0 1 0 0 0 0

0 1 1 0 0 0

1 0 0 1 0 1

1 0 1 1 1 1

1 1 0 0 0 1

1 1 1 0 0 1 PRODUCT OF SUMS: 1. Z = π (0,2,3)

Z = (A + B +C). (A + B' +C). (A + B' +C')

Z’ = ( (A + B +C). (A + B' +C) . (A + B' +C')) '

= (A + B +C) ' + (A + B' + C) ' + (A+B' +C') '

= A'B'C' + A'BC' + A'BC

= A'B'C' +A'B(C' + C)

= A'B'C' + A'B


14

= A' (B'C' + B)

= A' ((B'+ B)(C' + B))

= A' (C' + B)

= A'C' + A'B

Z = (A + C).(A +B')

AND – OR – NOT Gate:

Truth Table:

A B C B' A + C A + B' (A + C). (A + B')

0 0 0 1 0 1 0

0 0 1 1 1 1 1

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 1 1 1 1

1 0 1 1 1 1 1

1 1 0 0 1 1 1

1 1 1 0 1 1 1

De-Morgan’s Law:

i) (X+Y) ' = X' . Y'

Truth Table:

X Y X' Y' X+Y (X+Y) ' X'.Y'

0 0 1 1 0 1 1

0 1 1 0 1 0 0

1 0 0 1 1 0 0

1 1 0 0 1 0 0


15

ii) (X.Y) ' = X ' + Y '

Truth Table:

X Y X' Y' X.Y (X.Y)' X'+Y'

0 0 1 1 0 1 1

0 1 1 0 0 1 1

1 0 0 1 0 1 1

1 1 0 0 1 0 0

PROCEDURE:





breadboard.



Note down the output readings for different Boolean expressions and De-Morgan’s laws for

different combinations of inputs.

CONCLUSIONS

Simplified and verified the Boolean expressions and De-Morgan’s laws using digital IC’s.


16

EXP NO: 4

4 x 1 MULTIPLEXER

AIM:

To design a combinational logic circuit for 4 x 1 Multiplexer (MUX) using logic gates.




• IC 7408, IC 7432, IC 7402.

THEORY:

Multiplexers are very useful components in digital systems. They transfer a large number

of information units over a smaller number of channels, (usually one channel) under the control of

selection signals. Multiplexer means many to one. A multiplexer is a circuit with many inputs

but only one output. By using control signals (select lines) we can select any input to the output.

Multiplexer is also called as data selector because the output bit depends on the input data bit

that is selected. The general multiplexer circuit has 2n input signals, n control/select signals and

1 output signal. De-multiplexers perform the opposite function of multiplexers. They transfer a

small number of information units (usually one unit) over a larger number of channels under the

control of selection signals. The general de-multiplexer circuit has 1 input signal, n control/select

signals and 2 output signals. De-multiplexer circuit can also be realized using a decoder circuit with

enable.


17

Pin Diagrams:

Logic Diagram:


18

Truth Table:

Selection Lines Output

S1 S0 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

Y=S1'S0'D0 + S1'S0D1 + S1S0'D2 + S1S0D3

PROCEDURE

Make the connections as per the circuit diagram. Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard.

Switch on VCC and apply various combinations of input according to truth table and verify the Truth Table.

CONCLUSION:

A combinational logic circuit of 4x1 Multiplexer (MUX) is designed and verified the truth

table.


19

EXP NO: 5

1 x 4 DE-MULTIPLEXER

AIM:

To design a combinational logic circuit for 1x4 De-Multiplexer (De-MUX) using logic

gates.




• IC 7408, IC 7432, IC 7402.

THEORY:

Multiplexers are very useful components in digital systems. They transfer a large number

of information units over a smaller number of channels, (usually one channel) under the control of

selection signals. Multiplexer means many to one. A multiplexer is a circuit with many inputs

but only one output. By using control signals (select lines) we can select any input to the output.

Multiplexer is also called as data selector because the output bit depends on the input data bit

that is selected. The general multiplexer circuit has 2n input signals, n control/select signals and

1 output signal. De-multiplexers perform the opposite function of multiplexers. They transfer a

small number of information units (usually one unit) over a larger number of channels under the

control of selection signals. The general de-multiplexer circuit has 1 input signal, n control/select

signals and 2 output signals. De-multiplexer circuit can also be realized using a decoder circuit with

enable.


20

Pin Diagrams:

Logic Diagram:


21

Truth Table:

Data Selection Lines Output

D S1 S0 D0 D1 D2 D3

D 0 0 D 0 0 0

D 0 1 0 D 0 0

D 1 0 0 0 D 0

D 1 1 0 0 0 D

D0= S1'S0'D, D1= S1'S0D, D2=S1S0'D, D3=S1S0D

PROCEDURE


Switch on VCC and apply various combinations of input according to truth table and verify the Truth Table.

CONCLUSION:

A combinational logic circuit of 1x4 De-Multiplexer (De-MUX) is designed and verified

the truth table.


22

EXP NO: 6

HALF ADDER & FULL ADDER

AIM:

To design a half adder and full adder using Half Adder and verify the truth table.




• IC 7408, IC 7432, IC 7404,IC 7486.

THEORY:

Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B,

is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and

the other is the carry bit, C.

The Boolean functions describing the half-adder are

S =A⊕ B

C=AB

Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This

carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds

two data bits, A and B, and a carry-in bit, Cin , is called a full-adder.

The Boolean functions describing the full-adder are:

S = (x⊕ y)⊕ Cin

C = xy + Cin (x⊕ y)


23

Pin Diagrams:

Logic Diagram:

Half-Adder:

S =A⊕ B

C=AB

Truth Table:

Inputs Output

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1


24

Full Adder:

S = (A⊕ B)⊕ Cin

Cout = AB + Cin (A⊕ B)

Truth Table:

Inputs Output

A B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1


25

PROCEDURE

Make the connections as per the circuit diagram for the half adder circuit, on

the trainer kit.

Switch on the VCC power supply and apply the various combinations of the inputs

according to the respective truth tables.

Note down the output readings for the half adder circuit for the corresponding

combination of inputs.

Verify that the outputs are according to the expected results.

Repeat the procedure for the full adder circuit, the half subtractor and full subtractor

circuits.

CONCLUSION

By using various logic gate ICs we can perform the half adder/full adder and check the

truth tables.


26

EXP NO: 7

FLIP-FLOPS

AIM:

To verify various flip-flops and Truth Tables

1) SR Flip-flop

2) D Flip-flop

3) J,K Flip-flop

4) T Flip-flop


• Logic gates (IC) trainer kit or Flip-flop kit.


• IC 7400, IC, IC 7402, IC, IC 7404.

THEORY:

"Flip-flop" is the common name given to two-state devices which offer basic memory for

sequential logic operations. Flip-flops are heavily used for digital data storage and transfer and

are commonly used in banks called "register" for the storage of binary numerical data.

SR Flip flop:

The S and R inputs of the S-R flipflop are called synchronous control inputs because

data on these inputs affect the flipflop’s output only on the clock pulse.

If there is a HIGH on the S input and LOW on the R input when a clock pulse is

applied, the flip-flop SETS and stores a 1.

If there is a LOW on the S input and HIGH on the R input when a clock pulse is

applied, the flip-flop RESETS and stores a 0.

If there is a LOW on the S input and LOW on the R input when a clock pulse is

applied, the flip-flop NOCHANGE and stores a 0 or 1.

To implement SR flip-flop we require NAND gates and NOR gates.


27

Logic Diagram SR Flipflop:

Graphical symbol

Truth Table:

CLK S R Qn Qn+1

↑ 0 0 0 0

↑ 0 0 1 1

↑ 0 1 0 0

↑ 0 1 1 0

↑ 1 0 0 1

↑ 1 0 1 1

↑ 1 1 0 x

↑ 1 1 1 x

0 x x 0 0

0 x X 1 1

D Flip flop:

The operations of a D flip-flop are much simpler.

It has only one input addition to the clock. It is very useful when a single data bit (0 or 1)

is to be stored.

If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and

stores a 1.

If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and

stores a 0.

To implement D flip-flop we require NAND gates and NOR gates.


28

Logic Diagram:

Graphical symbol

Truth Table:

CLK D Qn Qn+1

↑ 0 0 0

↑ 0 1 0

↑ 1 0 1

↑ 1 1 1

0 x 0 0

0 x 1 1

JK Flip flop:

The J-K flip-flop works very similar to S-R flip-flop.

The only difference is that this flip-flop has NO invalid state.

Logic Diagram:


29

Graphical symbol

Truth Table:

CLK S R Qn Qn+1

↑ 0 0 0 0

↑ 0 0 1 1

↑ 0 1 0 0

↑ 0 1 1 0

↑ 1 0 0 1

↑ 1 0 1 1

↑ 1 1 0 1

↑ 1 1 1 0

0 x x 0 0

0 x X 1 1

T Flip flop:

This type of flip-flop is a simplified version of the JK flip-flop.

It is not usually found as an IC chip by itself, but is used in many kinds of circuits,

especially counter and dividers.

Its only function is that it toggles itself with every clock pulse (on either the leading edge,

on the trailing edge) it can be constructed from the RS flip-flop.

Logic Diagram:

Graphical symbol


30

Truth Table:

CLK D Qn Qn+1

↑ 0 0 0

↑ 0 1 0

↑ 1 0 1

↑ 1 1 0

0 x 0 0

0 x 1 1

PROCEDURE


Switch on VCC and apply proper input to SR, D, JK, T inputs of Flip-Flop. Check the output on logic section.

Change the input and verify the truth tables

CONCLUSION: Verified the truth tables of different flip flops like SR, D, JK and T.


31

EXP NO: 8

MASTER SLAVE FLIP-FLOP

AIM:

To implement the Master Slave Flipflop with JK Flipflop and verify the truth table for

race around condition.




• IC 7400, IC 7404.

THEORY:

The master slave flipflop was developed to make the synchronous operation more

predictable,i.e., to avoid the problems to logic race in clocked flipflops. A master-slave flipflop

is called a pulse triggered flipflop because the length of the time required for its output to change

state equals the width of one clock pulse.

Master-slave flip flop is designed using two separate flip flops. Out of these, one acts as

the master and the other as a slave. The control inputs are applied to the master flipflop and

maintained constant set up. There are three basic types of master slave flipflops- SR, D and JK is

most commonly availablr in IC form.

The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a

series configuration with the slave having an inverted clock pulse. The outputs from Q and Q

from the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the

“Master” flip flop being connected to the two inputs of the “Slave” flip flop. The input signals J

and K are connected to the gated “master” SR flip flop which “locks” the input condition while

the clock (Clk) input is “HIGH” at logic level “1”. As the clock input of the “slave” flip flop is

the inverse (complement) of the “master” clock input, the “slave” SR flip flop does not toggle.

The outputs from the “master” flip flop are only “seen” by the gated “slave” flip flop when the

clock input goes “LOW” to logic level “0”. Then, the circuit accepts input data when the clock


32

signal is “HIGH”, and passes the data to the output on the falling-edge of the clock signal. In

other words, the Master-Slave JK Flip flop is a “Synchronous” device as it only passes data

with the timing of the clock signal.

Pin diagram:

Logic Diagram:

Truth Table:

Inputs Output State Mode

Clk J K Q

↑ 0 0 Q0 No Change

↑ 0 1 0 Reset

↑ 1 0 1 Set

↑ 1 1 Q′0 Toggle


33

PROCEDURE



breadboard.

Switch on VCC and apply various combinations of input according to truth table and

verify the Truth Table.

CONCLUSION: The Master Slave Flipflop with JK Flipflop is designed and verified the truth table.


34

EXP NO: 9

DECADE COUNTER

AIM:

To design and verify the truth table of decade counter.


• Logic gates (IC) trainer kit


• IC 7490.

THEORY:

IC 7490 is a decade counter which drives input by 10 and provides BCD outputs 0 to 9,

this is also called as decimal counter. This counter comprises of a divide-by 2 and divide-by 5

counters. To use as decade counter we have to cascade divide-by 2 and divide-by 5. Outputs Q0

to Q3 are BCD outputs, inputs A and B are clock inputs to the, divide-by 2 and divide-by 5

counters respectively. R01 and R02 are the reset inputs, when these are activated counter output

go to 0000. R91 and R92 are the set inputs to the counter, when these inputs are activated

counter output go to 1001.

Pin Diagram:


35

Logic Diagram:

Truth Table:

Clock Master

Set

R01,R02

Master

Reset

R91,R92

QD

QC

QB

QA

1 0 1 0 0 0 0

1 1 0 0 0 0 1

1 0 0 0 0 0 0

1 0 0 0 0 0 1

1 0 0 0 0 1 0

1 0 0 0 0 1 1

1 0 0 0 1 0 0

1 0 0 0 1 0 1

1 0 0 0 1 1 0

1 0 0 0 1 1 1

1 0 0 1 0 0 0

1 0 0 1 0 0 1

1 0 0 Repeats

PROCEDURE:

Connections are made as per the circuit diagram

Switch on the power supply.

Apply clock pulses and note the outputs after each clock pulse and note done the out puts

QD, QC, QB, QA.

CONCLUSION:

Decade counter is designed and truth tables are verified.


36

EXP NO: 10

MOD – 6 COUNTER

AIM:

To design and verify the Mod-6 Counter using D-Flipflop.


• Logic gates (IC) trainer kit


• IC 7408,IC 7432, IC 7474.

THEORY:

A digital counter is set of flipflops whose states change in response to pulses

applied at the input to the counter. Thus name implies,a counter is used to count pulses. Counters

may be asynchronous counters or synchronous counters. A ripple counter is an asynchronous

counter where only the first flip-flop is clocked by an external clock. All subsequent flip-flops

are clocked by the output of the preceding flip-flop. Asynchronous counters are also called

ripple-counters because of the way the clock pulse ripples it way through the flip-flops. The

Synchronous Counter, the external clock signal is connected to the clock input of EVERY

individual flip-flop within the Counter so that all of the flip-flops are clocked together.

The MOD of the ripple counter or asynchronous counter is 2n if n flip-flops are used. For

a 4-bit counter, the range of the count is 0000 to 1111 (24-1). A counter may count up or count

down or count up and down depending on the input control. The count sequence usually repeats

itself. When counting up, the count sequence goes from 0000, 0001, 0010, ... 1110 , 1111 , 0000,

0001, ... etc. When counting down the count sequence goes in the opposite manner: 1111, 1110,

... 0010, 0001, 0000, 1111, 1110, ... etc.

http://amazon.in/s/?field-keywords=Fundamentals+of+Digital+Logic


37

Pin Diagram:


38

Circuit Diagram:

Truth Table:

Clock

Signal

Q1 Q2 Q3

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 Repeat

7

PROCEDURE



Apply clock pulses for mod-6 counter and note the outputs after each clock pulse.

CONCLUSION:

Mod-6 Counter using D-Flipflop are designed and truth table is verified.


39

EXP NO: 11

4 – BIT RING COUNTER AIM:

To design and verify the truth table of 4- bit Ring Counter.




• IC 7474, IC 7486.

THEORY:

A digital counter is a set of flip-flops whose states change in response to pulses applied at

the input to the counter. The FFs are interconnected such that their combined state at any time is

the binary equivalent of the total number of pulses that have occurred upto that time. A counter is

used to count pulses. Shift register counters are obtained from serial-in, serial-out shift register by

providing feedback from the output of the last FF to input of the FF. These devices are called

counters. The most widely used shift register counter is the Ring Counter as well as Twisted Ring

Counter (Johnson Counter).

Ring counter is a basic register with direct feedback such that the contents of the register

simply circulate around the register when the clock is running. Here the last output that is QD in a

shift register is connected back to the serial input.

Pin Diagram:

D-Flipflop:


40

Circuit Diagrams:

Logic Diagram of a 4 – bit ring counter using D-flip-flops:

Truth Table:

Clock

Signal

Q1 Q2 Q3 Q4

0 1 0 0 0

1 0 1 0 0

2 0 0 1 0

3 0 0 0 1

4 1 0 0 0

5 0 1 0 0

6 0 0 1 0

7 0 0 0 1

8 Repeats

PROCEDURE



Apply clock pulses for ring counter and note the outputs after each clock pulse.

Change the inputs for parity bit generator and verify the truth tables.

CONCLUSION: 4- Bit Ring couner are designed and their truth table are verified using D-Flipflop.


41

EXP NO: 12

SHIFT REGISTERS AIM: To design a 4-bit Shift Register and verify the truth tables using D-Flipflop.

1) SISO (Serial in Serial out)

2) SIPO (Serial in Parallel out)

3) PIPO (Parallel in Parallel out)

4) PISO (Parallel in Serial out)


• Logic gates (IC) trainer kit or Flip-flop kit.


• IC 7474

THEORY:

A data may be available in parallel form or serial form. Data also be transferred in

parallel form or serial for. Parallel data transfer is the simultaneous transmission of all bits of

data from one device to another. Serial data transfer is the transmission of one bit of data at a

time from one device to another. A number of FFs connected together such that data may be

shifted out of them is called a shift register. Data may be shifted into or out of the register either

in serial or parallel form. There four types of shift registers: serial – in, serial – out; parallel – in,

parallel – out; parallel – in, serial – out and serial – in, parallel -out. Data may be shifted from

left to right or right to left i.e., in a bidirectional way. Also, data may be shifted in serially or in

parallel and shifted out serially or parallel.

Pin Diagram:


42

Serial – In, Serial – Out (SIS0):

Truth Table:

Serial - In, Parallel – Out (SIPO):

Truth Table:


43

Parallel – In and Parallel – Out (PIPO):

Truth Table:

PROCEDURE:

Serial In Serial Out (SISO):

1. Connections are made as per circuit diagram.

2. Load the shift register with 4 bits of data one by one serially.

3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.

4. Apply another clock pulse; the second data ‘d1’ appears at QD.

5. Apply another clock pulse; the third data appears at QD.

6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at QD. Thus the data

applied serially at the input comes out serially at QD

Serial In Parallel Out (SIPO):


2. Apply the data at serial i/p

3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.

4. Apply the next data at serial i/p.

5. Apply one clock pulse at clock 2, observe that the data on QA will shift to QB and the new

data applied will appear at QA.

6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the shift register.


44

Parallel In Parallel Out (PIPO):


2. Apply the 4 bit data at A, B, C and D.

3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).

4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD.

CONCLUSION: Shift registers using IC 7474 in all its modes i.e. SIPO, SISO, PIPO are verified.

IC APPLICATIONS LAB MANUAL

1


2

Block Diagram of Op-Amp:

Pin Configuration:


3

EXP NO: DATE:

STUDY OF OP AMPs - IC 741, IC 555, IC 565, IC 566,

IC 1496-FUNCTIONING, PARAMETERS AND

SPECIFICATIONS

IC 741

General Description:

The IC 741 is a high performance monolithic operational amplifier constructed using the planer

epitaxial process. High common mode voltage range and absence of latch-up tendencies make the IC 741

ideal for use as voltage follower. The high gain and wide range of operating voltage provide superior

performance in integrator, summing amplifier and general feedback applications.

Features:

1. No frequency compensation required.

2. Short circuit protection

3. Offset voltage null capability

4. Large common mode and differential voltage ranges

5. Low power consumption

6. No latch-up

Specifications:

1. Voltage gain A = α typically 2,00,000

2. I/P resistance RL = α Ω, practically 2MΩ

3. O/P resistance R =0, practically 75Ω

4. Bandwidth = α Hz. It can be operated at any frequency

5. Common mode rejection ratio = α

(Ability of op amp to reject noise voltage)

6. Slew rate + α V/μsec

(Rate of change of O/P voltage)


4

Block Diagram of IC 555:

Pin Configuration:


5

7. When V1 = V2, VD=0

8. Input offset voltage (Rs ≤ 10KΩ) max 6 mv

9. Input offset current = max 200nA

10. Input bias current : 500nA

11. Input capacitance : typical value 1.4pF

12. Offset voltage adjustment range : ± 15mV

13. Input voltage range : ± 13V

14. Supply voltage rejection ratio : 150 μV/V

15. Output voltage swing: + 13V and – 13V for RL > 2KΩ

16. Output short-circuit current: 25mA

17. supply current: 28mA

18. Power consumption: 85mW

19. Transient response: rise time= 0.3 μs

Overshoot= 5%

Applications:

1. AC and DC amplifiers

2. Active filters

3. Oscillators

4. Comparators

5. Regulators

IC 555:

Description:

The operation of SE/NE 555 timer directly depends on its internal function. The three equal

resistors R1, R2, R3 serve as internal voltage divider for the source voltage. Thus one-third of the source

voltage VCC appears across each resistor.

Comparator is basically an Op amp which changes state when one of its inputs exceeds the

reference voltage. The reference voltage for the lower comparator is +1/3 VCC. If a trigger pulse applied

at the negative input of this comparator drops below +1/3 VCC, it causes a change in state. The upper

comparator is referenced at voltage +2/3 VCC. The output of each comparator is fed to the input terminals

of a flip flop.


6

Block Diagram of IC 565


7

The flip-flop used in the SE/NE 555 timer IC is a bistable multivibrator. This flip flop changes

states according to the voltage value of its input. Thus if the voltage at the threshold terminal rises above

+2/3 VCC, it causes upper comparator to cause flip-flop to change its states. On the other hand, if the

trigger voltage falls below +1/3 VCC, it causes lower comparator to change its states. Thus the output of

the flip flop is controlled by the voltages of the two comparators. A change in state occurs when the

threshold voltage rises above +2/3 VCC or when the trigger voltage drops below +1/3 Vcc.

The output of the flip-flop is used to drive the discharge transistor and the output stage. A high or

positive flip-flop output turns on both the discharge transistor and the output stage. The discharge

transistor becomes conductive and behaves as a low resistance short circuit to ground. The output stage

behaves similarly. When the flip-flop output assumes the low or zero states reverse action takes place

i.e., the discharge transistor behaves as an open circuit or positive VCC state. Thus the operational state of

the discharge transistor and the output stage depends on the voltage applied to the threshold and the

trigger input terminals.

Function of Various Pins of 555 IC:

Pin (1) of 555 is the ground terminal; all the voltages are measured with respect to this pin.

Pin (2) of 555 is the trigger terminal, If the voltage at this terminal is held greater than one-third

of VCC, the output remains low. A negative going pulse from Vcc to less than Vec/3 triggers the

output to go High. The amplitude of the pulse should be able to make the comparator (inside the

IC) change its state. However the width of the negative going pulse must not be greater than the

width of the expected output pulse.

Pin (3) is the output terminal of IC 555. There are 2 possible output states. In the low output

state, the output resistance appearing at pin (3) is very low (approximately 10 Ω). As a result the

output current will goes to zero , if the load is connected from Pin (3) to ground , sink a current I

Sink (depending upon load) if the load is connected from Pin (3) to ground, and sinks zero current

if the load is connected between +VCC and Pin (3).

Pin (4) is the Reset terminal. When unused it is connected to +Vcc. Whenever the potential of

Pin (4) is drives below 0.4V, the output is immediately forced to low state. The reset terminal

enables the timer over-ride command signals at Pin (2) of the IC.


8

Pin Configuration:


9

Pin (5) is the Control Voltage terminal. This can be used to alter the reference levels at which the

time comparators change state. A resistor connected from Pin (5) to ground can do the job.

Normally 0.01μF capacitor is connected from Pin (5) to ground. This capacitor bypasses supply

noise and does not allow it affect the threshold voltages.

Pin (6) is the threshold terminal. In both astable as well as monostable modes, a capacitor is

connected from Pin (6) to ground. Pin (6) monitors the voltage across the capacitor when it

charges from the supply and forces the already high O/p to Low when the capacitor reaches +2/3

VCC.

Pin (7) is the discharge terminal. It presents an almost open circuit when the output is high and

allows the capacitor charge from the supply through an external resistor and presents an almost

short circuit when the output is low.

Pin (8) is the +Vcc terminal. 555 can operate at any supply voltage from +3 to +18V.

Features of 555 IC

1. The load can be connected to o/p in two ways i.e. between pin 3 & ground 1 or

between pin 3 & VCC (supply)

2. 555 can be reset by applying negative pulse, otherwise reset can be connected to +Vcc to

avoid false triggering.

3. An external voltage effects threshold and trigger voltages.

4. Timing from micro seconds through hours.

5. Monostable and bistable operation

6. Adjustable duty cycle

7. Output compatible with CMOS, DTL, TTL

8. High current output sink or source 200mA

9. High temperature stability

10. Trigger and reset inputs are logic compatible.


10

Block Diagram of IC 565

Pin Configuration:


11

Specifications:

1. Operating temperature : SE 555-- -55oC to 125

oC

NE 555-- 0o to 70

oC

2. Supply voltage : +5V to +18V

3. Timing : μSec to Hours

4. Sink current : 200mA

5. Temperature stability : 50 PPM/oC change in temp or 0-005% /

oC.

Applications:

1. Monostable and Astable Multivibrators

2. dc-ac converters

3. Digital logic probes

4. Waveform generators

5. Analog frequency meters

6. Tachometers

7. Temperature measurement and control

8. Infrared transmitters

9. Regulator & Taxi gas alarms etc.

IC 565:

Description:

The Signetics SE/NE 560 series is monolithic phase locked loops. The SE/NE 560, 561, 562, 564, 565, &

567 differ mainly in operating frequency range, power supply requirements and frequency and bandwidth

adjustment ranges. The device is available as 14 Pin DIP package and as 10-pin metal can package.

Phase comparator or phase detector compare the frequency of input signal fs with frequency of VCO

output fo and it generates a signal which is function of difference between the phase of input signal and

phase of feedback signal which is basically a d.c voltage mixed with high frequency noise. LPF remove

high frequency noise voltage. Output is error voltage. If control voltage of VCO is 0, then frequency is

center frequency (fo) and mode is free running mode. Application of control voltage shifts the output

frequency of VCO from fo to f. On application of error voltage, difference between fs & f tends to

decrease and VCO is said to be locked. While in locked condition, the PLL tracks the changes of

frequency of input signal


12

BLOCK DAGRAM OF IC 566

PIN DIAGRAM


13

Specifications:

1. Operating frequency range : 0.001 Hz to 500 KHz

2. Operating voltage range : ±6 to ±12V

3. Inputs level required for tracking : 10mV rms minimum to 3v (p-p) max.

4. Input impedance : 10 KΩ typically

5. Output sink current : 1mA typically

6. Drift in VCO center frequency : 300 PPM/oC typically

(fout) with temperature

7. Drif in VCO centre frequency with : 1.5%/V maximum

supply voltage

8. Triangle wave amplitude : typically 2.4 VPP at ± 6V

9. Square wave amplitude : typically 5.4 VPP at ± 6V

10. Output source current : 10mA typically

11. Bandwidth adjustment range : <±1 to >± 60%

Center frequency fout = 1.2/4R1C1 Hz

= free running frequency

FL = ± 8 fout/V Hz

V = (+V) – (-V)

fc = ± 2/1

3 210)6.3(2

xCx

f L

Applications:

1. Frequency multiplier

2. Frequency shift keying (FSK) demodulator

3. FM detector

IC 566:

Description:

The NE/SE 566 Function Generator is a voltage controlled oscillator of exceptional linearity with

buffered square wave and triangle wave outputs. The frequency of oscillation is determined by an

external resistor and capacitor and the voltage applied to the control terminal. The oscillator can be


14

programmed over a ten to one frequency range by proper selection of an external resistance and

modulated over a ten to one range by the control voltage with exceptional linearity.

Schematic of IC1496:

Pin Configuration:


15

Specifications:

Maximum operating Voltage --- 26V

Input voltage --- 3V (P-P)

Storage Temperature --- -65oC to + 150

oC

Operating temperature --- 0oC to +70

oC for NE 566

-55oC to +125

oC for SE 566

Power dissipation --- 300mv

Applications:

1. Tone generators.

2. Frequency shift keying

3. FM Modulators

4. clock generators

5. signal generators

6. Function generator

IC 1496

Description:

IC balanced mixers are widely used in receiver IC’s. The IC versions are usually described as

balanced modulators. Typical example of balanced IC modulator is MC1496. The circuit consists of a

standard differential amplifier (formed by Q5 _ Q6 combination) driving a quad differential amplifier

composed of transistor Q1 – Q4. The modulating signal is applied to the standard differential amplifier

(between terminals 1 and 4). The standard differential amplifier acts as a voltage to current converter. It

produces a current proportional to the modulating signal. Q7 and Q8 are constant current sources for the

differential amplifier Q5 – Q6. The lower differential amplifier has its emitters connected to the package

pins ( 2 & 3) so that an external emitter resistance may be used. Also external load resistors are employed

at the device output (6 and 12 pins).The output collectors are cross-coupled so that full wave balanced

multiplication takes place. As a result, the output voltage is a constant times the product of the two input

signals.


16

Circuit Diagrams:

Fig 1: Adder

Fig 2: Subtractor


17

EXP NO: DATE:

OP AMP APPLICATIONS– ADDER, SUBTRACTOR,

COMPARATOR CIRCUITS

Aim: To design adder, subtractor and comparator for the given signals by using operational amplifier.

Apparatus required:

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 - 1

2 Resistor 1kΩ 4

3 Diode 0A79 2

4 Regulated Power supply (0 – 30V),1A 2

5 Function Generator (.1 – 1MHz), 20V p-p 1

6 Cathode Ray Oscilloscope (0 – 20MHz) 1

7 Multimeter 3 ½

digit display 1

Theory:

Adder: A two input summing amplifier may be constructed using the inverting mode. The adder can

be obtained by using either non-inverting mode or differential amplifier. Here the inverting mode is used.

So the inputs are applied through resistors to the inverting terminal and non-inverting terminal is

grounded. This is called “virtual ground”, i.e. the voltage at that terminal is zero. The gain of this

summing amplifier is 1, any scale factor can be used for the inputs by selecting proper external resistors.

Subtractor: A basic differential amplifier can be used as a subtractor as shown in the circuit diagram.

In this circuit, input signals can be scaled to the desired values by selecting appropriate values for the

resistors. When this is done, the circuit is referred to as scaling amplifier. However in this circuit all

external resistors are equal in value. So the gain of amplifier is equal to one. The output voltage Vo is

equal to the voltage applied to the non-inverting terminal minus the voltage applied to the inverting

terminal; hence the circuit is called a subtractor.


18

Fig 3: Comparator


19

Comparator: The circuit diagram shows an op-amp used as a comparator. A fixed reference voltage

Vref is applied to the (-) input, and the other time – varying signal voltage Vin is applied to the (+) input;

Because of this arrangement, the circuit is called the non-inverting comparator. Depending upon the

levels of Vin and Vref, the circuit produces output. In short, the comparator is a type of analog-to-digital

converter. At any given time the output waveform shows whether Vin is greater or less than Vref. The

comparator is sometimes also called a voltage-level detector because, for a desired value of Vref, the

voltage level of the input Vin can be detected

Procedure:

A) Adder:

1. Connect the circuit as per the diagram shown in Fig 1.

2. Apply the supply voltages of +15V to pin7 and pin4 of IC741 respectively.

3. Apply the inputs V1 and V2 as shown in Fig 1.

4. Apply two different signals (DC/AC ) to the inputs

5. Vary the input voltages and note down the corresponding output at pin 6 of the IC 741 adder circuit.

6. Notice that the output is equal to the sum of the two inputs.

B) Subtractor:

1. Connect the circuit as per the diagram shown in Fig 2.

2. Apply the supply voltages of +15V to pin7 and pin4 of IC741 respectively.

3 Apply the inputs V1 and V2 as shown in Fig 2.

4. Apply two different signals (DC/AC ) to the inputs

5. Vary the input voltages and note down the corresponding output at pin 6 of the IC

741 subtractor circuit.

6. Notice that the output is equal to the difference of the two inputs.


20

Observations:

Adder:

V1(V) V2(V) Vo(V)=-(V1+V2)

2.5

3.8

2.5

4.0

Subtractor:

V1(V) V2(V) Vo(V)=(V1-V2)

2.5

4.1

3.3

5.7

Comparator:

Vin(V) Vref(V) Vo(V)

2

5

0.5

7.2


21

Precautions:

Check the connections before giving the power supply.

Readings should be taken carefully.

Result:

For adder, subtractor and comparator circuits, the practical values are compared with the

theoretical values and they are nearly equal.

NAME THEORETICAL PRACTICAL

ADDER

SUBTRACTOR

COMPARATOR


22

Model Calculations:

a) Adder

Vo = - (V1 + V2)

If V1 = and V2 = , then

Vo =

b) Subtractor

Vo = V2 – V1

If V1= and V2 = , then

Vo =

c) Comparator

If Vin < Vref, Vo = -Vsat - VEE

Vin > Vref, Vo = +Vsat = +VCC


23

Inference:

Different applications of opamp are observed.

Viva Questions:

1. What is the saturation voltage of 741 in terms of VCC?

Ans: 90% of VCC

2. What is the maximum voltage that can be given at the inputs?

Ans: The inputs must be given in such a way that the output should be less

than Vsat.


24

CIRCUIT DIAGRAMS

Integrator


25

EXP NO: DATE:

INTEGRATOR AND DIFFERENTIATORCIRCUITS USING IC 741

Aim: To design and verify the operation of an integrator and differentiator for a given input.

Apparatus required:


1 741 IC - 1

2 Capacitors 0.1μf, 0.01μf Each one

3 Resistors 159Ω, 1.5kΩ Each one

4 Regulated Power supply (0 – 30)V,1A 1

5 Function generator (1Hz – 1MHz) 1


Theory

Integrator: In an integrator circuit, the output voltage is integral of the input signal. The output

voltage of an integrator is given by

Vo = -1/R1Cf Vidt

t

o

At low frequencies the gain becomes infinite, so the capacitor is fully charged and behaves like an open

circuit. The gain of an integrator at low frequency can be limited by connecting a resistor in shunt with

capacitor.

Differentiator: In the differentiator circuit the output voltage is the differentiation of the input

voltage. The output voltage of a differentiator is given by Vo = -RfC1 dt

dVi.The input

impedance of this circuit decreases with increase in frequency, thereby making the circuit sensitive to

high frequency noise. At high frequencies circuit may become unstable.


26

Differentiator

Design equations:

Integrator:

Choose T = 2πRfCf

Where T= Time period of the input signal

Assume Cf and find Rf

Select Rf = 10R1

Vo (p-p) = dtVCR

ppi

T

of

)(

2/

1

1

Differentiator

Select given frequency fa = 1/(2πRfC1), Assume C1 and find Rf

Select fb = 10 fa = 1/2πR1C1 and find R1

From R1C1 = RfCf, find Cf


27

Procedures:

Integrator

1. Connect the circuit as per the diagram shown in Fig 1

2. Apply a square wave/sine input of 4V(p-p) at 1KHz

3. Observe the output at pin 6.

4. Draw input and output waveforms as shown in Fig 3.

Differentiator

1. Connect the circuit as per the diagram shown in Fig 2

2. Apply a square wave/sine input of 4V(p-p) at 1KHz

3. Observe the output at pin 6

4. Draw the input and output waveforms as shown in Fig 4


28

Wave Forms:

Integrator

Fig 3: Input and output waves forms of integrator


29

Precautions: Check the connections before giving the power supply.



30

Differentiator

Fig 4 :Input and output waveforms of Differentiator


31

Result: For a given square wave and sine wave, output waveforms for integrator and differentiator are

observed.


INTEGRATOR

DIFFERENTIATOR


32

Sample readings:

Integrator

Input –Square wave Output - Triangular

Amplitude(VP-P)

(V)

Time period

(ms)

Amplitude (VP-P)

(V)

Time period

(ms)

8 1

Input –sine wave Output - cosine

Amplitude(VP-P)

(V)

Time period

(ms)

Amplitude (VP-P)

(V)

Time period

(ms)

8 1

Differentiator

Input –square wave Output - Spikes

Amplitude (VP-P)

(V)

Time period

(ms)

Amplitude (VP-P)

(V)

Time period

(ms)

8 1

Input –sine wave Output - cosine

Amplitude (VP-P)

(V)

Time period

(ms)

Amplitude (VP-P)

(V)

Time period

(ms)

8 1


33

Inferences: Spikes and triangular waveforms can be obtained from a given square waveform by

using differentiator and integrator respectively.

Viva Questions:

1. What are the problems of ideal differentiator?

Ans: At high frequencies the differentiator becomes unstable and breaks into oscillation. The

differentiator is sensitive to high frequency noise.

2. What are the problems of ideal integrator?

Ans: The gain of the integrator is infinite at low frequencies.

3. What are the applications of differentiator and integrator?

Ans: The differentiator used in waveshaping circuits to detect high frequency components in an

input signal and also as a rate-of –change detector in FM demodulators.

The integrator is used in analog computers and analog to digital converters and signal-wave

shaping circuits.

4. What is the need for Rf in the circuit of integrator?

Ans: The gain of an integrator at low frequencies can be limited to avoid the saturation problem if

the feedback capacitor is shunted by a resistance Rf

5. What is the effect of C1 on the output of a differentiator?

Ans: It is used to eliminate the high frequency noise problem.


34

Model Calculations:

Integrator:

For T= 1 msec

fa= 1/T = 1 KHz

fa = 1 KHz = 1/(2πRfCf)

Assuming Cf= 0.1μf, Rf is found from Rf=1/(2πfaCf)

Rf=1.59 KΩ

Rf = 10 R1

R1= 159Ω

Differentiator

For T = 1 msec

f= 1/T = 1 KHz

fa = 1 KHz = 1/(2πRfC1)

Assuming C1= 0.1μf, Rf is found from Rf=1/(2πfaC1)


35


36

Circuit diagrams:

Fig: Low pass filter


37

EXP NO: DATE:

Active Filter Applications – LPF, HPF (first order)

Aim: To design and obtain the frequency response of

i) First order Low Pass Filter (LPF)

ii) First order High Pass Filter (HPF)

Apparatus required:


1 IC 741 - 1

2 Resistors

Variable Resistor

10k ohm

20kΩ pot

3

1

3 Capacitors 0.01μf 1



6 Function Generator (1Hz – 1MHz) 1

Theory:

a) LPF:

A LPF allows frequencies from 0 to higher cut of frequency, fH. At fH the gain is 0.707 Amax, and

after fH gain decreases at a constant rate with an increase in frequency. The gain decreases 20dB each

time the frequency is increased by 10. Hence the rate at which the gain rolls off after fH is 20dB/decade or

6 dB/ octave, where octave signifies a two fold increase in frequency. The frequency f=fH is called the

cut off frequency because the gain of the filter at this frequency is down by 3 dB from 0 Hz. Other

equivalent terms for cut-off frequency are -3dB frequency, break frequency, or corner frequency.

b) HPF:

The frequency at which the magnitude of the gain is 0.707 times the maximum value of gain is

called low cut off frequency. Obviously, all frequencies higher than fL are pass band frequencies with the

highest frequency determined by the closed –loop band width all of the op-amp.


38

Fig: High pass filter

Design:

First Order LPF: To design a Low Pass Filter for higher cut off frequency fH = 4 KHz and pass band

gain of 2

fH = 1/( 2πRC )

Assuming C=0.01 µF, the value of R is found from

R= 1/(2πfHC) Ω =3.97KΩ

The pass band gain of LPF is given by AF = 1+ (RF/R1)= 2

Assuming R1=10 KΩ, the value of RF is found from

RF=( AF-1) R1=10KΩ

First Order HPF: To design a High Pass Filter for lower cut off frequency fL = 4 KHz and

pass band gain of 2

fL = 1/( 2πRC )

Assuming C=0.01 µF,the value of R is found from

R= 1/(2πfLC) Ω =3.97KΩ

The pass band gain of HPF is given by AF = 1+ (RF/R1)= 2

Assuming R1=10 KΩ, the value of RF is found from

RF=( AF-1) R1=10KΩ


39

Procedure:

First Order LPF

1. Connections are made as per the circuit diagram shown in Fig 1.

2. Apply sinusoidal wave of constant amplitude as the input such that op-amp does not go into

saturation.

3. Vary the input frequency and note down the output amplitude at each step as shown in Table (a).

4. Plot the frequency response as shown in Fig 3 .

First Order HPF

1. Connections are made as per the circuit diagrams shown in Fig 2.

2. Apply sinusoidal wave of constant amplitude as the input such that op-amp does not go into

saturation.

3. Vary the input frequency and note down the output amplitude at each step as shown in Table (b).

4. Plot the frequency response as shown in Fig 4


40

Tabular Form and Sampled Values:

a)LPF b) HPF

Input voltage Vin = 4V

Frequency

O/P

Voltage(V)

Voltage

Gain

Vo/Vi

Gain

indB

100Hz

200Hz

300Hz

500Hz

750Hz

900Hz

1KHz

2KHz

3KHz

4KHz

5KHz

6KHz

7KHz

8KHz

9KHz

10KHz

Frequency O/P

Voltage(V)

Voltage

Gain

Vo/Vi

Gain

indB

100Hz

200Hz

300Hz

500Hz

700Hz

800Hz

1KHz

2KHz

3KHz

4KHz

5KHz

6KHz

7KHz

8KHz

9KHz

10KHz


41

Precautions:



Inferences:

By interchanging R and C in a low-pass filter, a high-pass filter can be obtained.

Viva Questions:

1. What is meant by frequency scaling?

Ans: Change of cut off frequency from one value to the other.

2. How do you convert an original frequency (cut off) fH to a new cut off frequency fH?

Ans: By varying either resistor R or capacitor C values

3. What is the effect of order of the filter on frequency response characteristics?

Ans: Each increase in order will produce -20 dB/decade additional increases in roll off rate.

4. What modifications in circuit diagrams require to change the order of the filter?

Ans: Order of the filter is changed by RC network.


42

Model graphs :

Fig (3)

Fig(4)

Frequency response characteristics

Frequency response characteristics

of LPF of HPF


43

Result: First order low-pass filter and high-pass filter are designed and frequency response

characteristics are obtained.


LPF

HPF


44

Circuit diagrams:

Fig 1: Wideband pass filter


45

EXP NO: DATE:

Active Filter Applications – BPF & Band Reject (Wideband) and

Notch Filters

Aim: To design and obtain the frequency response of

i) Wide Band pass filter

ii) Wide Band reject filter

iii) Notch filter

Apparatus required:

Theory:

Band pass filter: A band pass filter has a pass band between two cutoff frequencies fH and fL such

that fH > fL. Any input frequency outside this pass band is attenuated. There are two types of band-pass

filters. Wide band pass and Narrow band pass filters. We can define a filter as wide band pass if its

quality factor Q <10. If Q>10, then we call the filter a narrow band pass filter. A wide band pass filter

can be formed by simply cascading high-pass and low-pass sections. The order of band pass filter

depends on the order of high pass and low pass sections.


1 741 IC - 3

2 Resistors

Resistors

5.6kΩ

39kΩ

9

2

3 Resistors (20kΩ pot) 2

4 Capacitors

Capacitors

Capacitors

0.01μf

0.1μf

0.2μf

2

2 1

5 Regulated Power supply (0 – 30)V,1A 1

6 Function Generator (1Hz – 1MHZ) 1



46

Fig 2: Wideband reject filter


47

Band Rejection Filter: The band-reject filter is also called a band-stop or band-elimination

filter. In this filter, frequencies are attenuated in the stop band while they are passed outside this

band. Band reject filters are classified as wide band-reject narrow band-reject. Wide band-

reject filter is formed using a low pass filter, a high-pass filter and summing amplifier. To

realize a band-reject response, the low cut off frequency fL of high pass filter must be larger than

high cut off frequency fH of low pass filter. The pass band gain of both the high pass and low

pass sections must be equal.

Notch Filter:

The narrow band reject filter, often called the notch fitter is commonly used for the rejection of a

single frequency. The most commonly used notch filter is the twin-T network .This is a passive

filter composed of two T-shaped networks. One T network is made up of two resistors and a

capacitor, while the other uses two capacitors and a resistor. There are several ways to make the

notch filter. One way is to subtract the band pass filter output from its input .The notch-out

frequency is the frequency at which maximum attenuation occurs and is given by

fN = 1/( 2πRC )


48

Fig 3: Notch filter


49

Design:

Band pass filter: To design a band pass filter having fH = 4KHz and fL = 400Hz and pass band

gain of 2.

As shown in Fig 1,the first section consisting of Op Amp,RF,R1,R and C is the high pass filter

and second consisting of low pass filter. The design of low pass and high pass filters.

Low Pass Filter Design:

Assuming C’=0.01μf, the value of R’ is found from

R’ = 1/(2πfH C’) Ω =3.97KΩ

The pass band gain of LPF is given by ALPF = 1+ (R’ F / R’1 )=2

Assuming R’1=5.6 KΩ, the value of R’F is found from R’F =( AF-1) R’1=5.6KΩ

High Pass Filter Design:

Assuming C=0.01μf, the value of R is found from

R = 1/(2πfLC) Ω =39.7KΩ

The pass band gain of HPF is given by AHPF = 1+ (RF / R1 )=2

Assuming R1=5.6 KΩ, the value of RF is found from

RF = ( AF-1) R1=5.6KΩ

Band reject filter: To design a band reject filter with fH = 4 KHz, fL = 400Hz and pass band

gain of 2

Low Pass Filter Design:

Assuming C’=0.01μf, the value of R’ is found from

R’ = 1/(2πfH C’) Ω =3.97KΩ

The pass band gain of LPF is given by ALPF = 1+ (R’ F / R’1 )=2

Assuming R’1=5.6 KΩ, the value of R’F is found from

R’F =( AF-1) R’1=5.6KΩ

High Pass Filter Design:

Assuming C=0.01μf, the value of R is found from

R = 1/ (2πfLC) Ω =39.7KΩ

The pass band gain of HPF is given by AHPF = 1+ (RF / R1) =2

Assuming R1=5.6 KΩ, the value of RF is found from

RF = (AF-1) R1=5.6KΩ


50

Observations:

a) Band pass filter: b) Band Reject Filter

Input voltage (Vi) = 0.5V

Frequeny O/P

Voltage

Vo(V)

Gain

Vo/Vi

Gain

indB

100Hz

200Hz

300Hz

400Hz

500Hz

750Hz

900Hz

1KHz

1.5KHz

2KHz

2.5KHz

3KHz

4KHz

5KHz

6KHz

7KHz

8KHz

9KHz

10KHz

Frequency O/P

Voltage(V)

Gain

Vo/Vi

Gain indB

50Hz

70Hz

100Hz

200Hz

300Hz

400Hz

500Hz

700Hz

900Hz

1KHz

2KHz

3KHz

4KHz

5KHz

6KHz

7KHz

8KHz

9KHz

10KHz


51

Adder circuit design: Select all resistors equal value such that gain is unity.

Assume R2=R3=R4=5.6 KΩ

Notch Filter Design: fN = 400Hz

Assuming C=0.1μf,the value of R is found from

R = 1/ (2πfNC)=39 KΩ

Procedure:

Wide Band Pass Filter:

1. Connect the circuit as per the circuit diagram shown in Fig1

2. Apply sinusoidal wave of 0.5V amplitude as input such that opamp does not go into

saturation (depending on gain).

3. Vary the input frequency from 100 Hz to 100 KHz and note down the output amplitude at

each step as shown in Table (a).

4. Plot the frequency response as shown in Fig 4.

Wide Band Reject Filter:

1. Connect the circuit as per the circuit diagram shown in Fig 2

2. Apply sinusoidal wave of 0.5V amplitude as input such that opamp does not go into


3. Vary the input frequency from 100 Hz to 100 KHz and note down the output amplitude at

each step as shown in Table( b).

4. Plot the frequency response as shown in Fig 5.

Notch Filter:

1. Connect the circuit as per the circuit diagram shown in Fig 3

2. Apply sinusoidal wave of 2Vp-p amplitude as input such that opamp does not go into


3. Vary the input frequency from 100 Hz to 4 KHz and note down the output amplitude at each

step as shown in Table( c).

4. Plot the frequency response as shown in Fig 6


52

c) Notch filter

Input voltage=2Vp-p

Frequency O/P

Voltage(V)

Vo/Vi Gain in

dB

100Hz

200Hz

300Hz

400Hz

500Hz

600Hz

700Hz

800Hz

900Hz

1 KHz

2 KHz

3 KHz

4 KHz


53

Precautions:



Result:

i) The frequency response of wide band pass filter is plotted as shown in Fig 4.

ii) The frequency response of wide band reject filter is plotted as shown in Fig 5.

iii) The frequency response of notch filter is plotted as shown in Fig 6


BAND PASS

FILTER

BAND REJECT

FILTER

NOTCH FILTER


54

Model graphs:

Fig 4 : Frequency response of Fig 5 : Frequency response wide

bandpass filter of wide band reject filter

Fig 6: Frequency response of notch filter


55

Inferences: Cascade connection of HPF and LPF produces wideband pass filter and parallel

connection of the above filters gives wideband reject filter. The notch filter is used to reject the single

frequency.

Viva Questions:

1. What is the relation between fC & fH, fL?

Ans: LHC fff

2. How do you increase the gain of the wideband pass filter?

Ans: By increasing the gain of either LPF or HPF

3. What is the application of Notch filter?

Ans: The rejection of single frequency such as the 50-Hz power line frequency hum

4. What is the order of the filter (each type) ?.What modifications you suggest for the

Ans: circuit diagram to increase the order of the filter?

Order of the BPF & BRF’S are the order of the HPF & LPF..Order of the

BPF& BRF’s are increased by increasing order of HPF&LPF.

5. What is the gain roll off outside the pass band?

Ans: Gain roll off outside the pass band is (20n) db/dec where ’n’ indicates the order of the filter.

6. What is the difference between active and passive filters?

Ans: Active filters use Op Amp as active element, and resistors and capacitors as the passive elements.

7. What are the advantages of active filters over passive filters?

Ans: Gain and frequency adjustment.

No loading problem.

Low cost


56

RC Phase shift Oscillator

Wein Bridge Oscillator


57

EXP NO: DATE:

RC PHASE SHIFT & WEIN BRIDGE OSCILLATORS

AIM: To Design a RC Phase Shift & Wein Bridge Oscillators of output frequency 200 Hz.

APPARATUS :

NAME OF THE COMPONENT VALUE Qty

1. Resistor 3.3 K 3

2. Resistor 33K 2

3. Resistor 12K 1

4. Variable Resistor 1.2M,50K Each one

5. Capacitor 0.1μf 3

6. Capacitor 0.05 μf 2

7. 741 IC Refer Appendix –A 1

8. Bread Board 1

9. Dual Channel Power Supply (0-30V) 1

10. Cathode Ray Oscilloscope (0 – 20MHz) 1

THEORY:

RC Phase shift oscillator:

The op-amp is used in inverting mode and so it provides 1800 phase shift. The additional phase

1800deg provided by RC feedback network to obtain total phase shift of 3600.The feedback

network consists of three identical RC stages. Each RC stage provides 600phase shift ,so that

total phase shift provided by feed back network is 1800. Here the gain of the inverting op-amp

should be at least 29, or Rf = 29R1.Frequency of oscillation fo = 1/ (2πRC 6)

Wien Bridge Oscillator:

It is a audio frequency oscillator. Feed back signal in this circuit is connected to non inverting

input terminal so that op-amp is working as a non inverting amplifier. So the feed back network

need not provide any phase shift. The circuit can be viewed as a Wein-Bride with a series RC

network in one arm and parallel RC network in ad joint arm.R1 and Rf are connected in the

remaining two arms. Here Rf = 2R1.

CALCULATIONS (theoretical):


58

RC Phase shift Oscillator:

i. The frequency of oscillation fo is given by fo = 1/(2π )

ii. The gain Av at the above frequency must be at least 29 i.e Rf/R1=29

iii. fo= 200Hz

Let C = 0.1μf , Then R= 3.25K (choose 3.3k)

To prevent the loading of the amplifier because of RC networks it is necessary that

R1≥10R Therefore R1=10R=33 k Then Rf= 29 (33 k) = 957 k (choose Rf=1M)

Wein Bridge Oscillator:

The frequency of oscillation fo is exactly the resonant frequency of the balanced Wein Bridge and

is given by fo = 1/(2πRC )

The gain required for sustained oscillations is given by Av= 3. i.e., Rf=2R1

Let C = 0.05uf Then fo = 1/ (2πRC ) => R=3.3K

Now let R1=12K, then Rf =2R1=24K

Use Rf =50K potentiometer

MODEL WAVE FORMS:

RC Phase shift Oscillator:

1. The frequency of oscillation = ______

Wein Bridge Oscillator:

2. The frequency of oscillation = ______


59

PROCEDURE:

1. Construct the circuits as shown in the circuit diagrams.

2. Adjust the potentiometer Rf that an output wave form is obtained.

3. Calculate the output wave form frequency and peak to peak voltage

4. Compare the theoretical and practical values of the output waveform frequency

RESULT:

1. The frequency of oscillation of the RC phase shift oscillator = --------Hz

2. The frequency of oscillation of the Wein Bridge oscillator = --------Hz

VIVA-VOICE:

1. State the two condition of oscillations

2. Classify the oscillators

3. What is the phase shift in case of the RC phase shift oscillator?

4. In phase shift oscillator what phase shift does the op-amp provide?


60

Circuit Diagram:

Fig1: Function generator


61

EXP NO: DATE:

Function Generator using OPAMPs

Aim: To generate square wave and triangular wave form by using OPAMPs.

Apparatus required:


1 741 IC - 2

2 Capacitors 0.01μf,0.001μf Each one

3 Resistors

Resistors

86kΩ ,68kΩ ,680kΩ

100kΩ

Each one

2


5 Cathode Ray Oscilloscope (0 -20MHz) 1

Theory:

Function generator generates waveforms such as sine, triangular, square waves and so on of

different frequencies and amplitudes. The circuit shown in Fig1 is a simple circuit which generates

square waves and triangular waves simultaneously. Here the first section is a square wave generator and

second section is an integrator. When square wave is given as input to integrator it produces triangular

wave.


62

Design:

Square wave Generator:

T= 2RfC ln (2R2 +R1/ R1)

Assume R1 = 1.16 R2

Then T= 2RfC

Assume C= and find Rf =

Assume R1= and find R2 =

Integrator:

Take R3 Cf >> T

R3 Cf = 10T

Assume Cf= find R3 =

Take R3Cf = 10T

Assume Cf = 0.01μf

R3 = 10T/C

= 20K


63

Procedure:

1. Connect the circuit as per the circuit diagram shown above.

2. Obtain square wave at A and Triangular wave at Vo2 as shown in Fig 1.

3. Draw the output waveforms as shown in Fig 2(a) and (b).


64

Model Calculations:

For T= 2 m sec

T = 2 Rf C

Assuming C= 0.1μf

Rf = Sample readings:

Square Wave:

Vp-p = 26 V(p-p)

T = 1.8 msec

Triangular Wave:

Vp-p = 1.3 V

T= 1.8 msec

2.10-3

/ 2.01.10-6

= 10 KΩ

Assuming R1 = 100 K

R2 = 86 KΩ

Wave Forms:

Fig 2 (a):

Output at ‘A’

(b): Output at V02


65

Precautions:



.

Result: Square wave and triangular wave are generated and the output waveforms are observed.


SQUAREWAVE

TRIANGULARWAVE

Inferences: Various waveforms can be generated.

Viva Questions:

1. How do you change the frequency of square wave?

Ans: By changing resistor and capacitor values

2. What are the applications of function generator?

Ans: Function generators are used for Transducer linearization and sine shaping.


66

Circuit Diagram:

Fig1:Monostable Circuit using IC555


67

EXP NO: DATE:

IC 555 Timer-Monostable Operation Circuit

Aim: To generate a pulse using Monostable Multivibrator by using IC555

Apparatus required:

S.No Equipment/Component

name

Specifications/Value Quantity

1 555 IC - 1


3 Resistor 10kΩ 1


5 Function Generator (1HZ – 1MHz) 1

6 Cathode ray oscilloscope (0 – 20MHz) 1

Theory:

A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-generating circuit

in which the duration of the pulse is determined by the RC network connected externally to the 555 timer.

In a stable or stand by mode the output of the circuit is approximately Zero or at logic-low level. When

an external trigger pulse is obtained, the output is forced to go high ( VCC). The time for which the

output remains high is determined by the external RC network connected to the timer. At the end of the

timing interval, the output automatically reverts back to its logic-low stable state. The output stays low

until the trigger pulse is again applied. Then the cycle repeats. The Monostable circuit has only one

stable state (output low), hence the name monostable. Normally the output of the Monostable

Multivibrator is low.


68

Design:

Consider VCC = 5V, for given tp

Output pulse width tp = 1.1 RA C

Assume C = in the order of microfarads & Find RA?

Typical values:

If C=0.1 µF , RA = 10k then tp = 1.1 mSec

Trigger Voltage =4 V


69

Procedure:

1. Connect the circuit as shown in the circuit diagram.

2. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.

3. Observe the output waveform and measure the pulse duration.

4. Theoretically calculate the pulse duration as Thigh=1.1. RAC

5. Compare it with experimental values.


70

Waveforms:

Fig 2 (a): Trigger signal

(b): Output Voltage

(c): Capacitor Voltage

Sample Readings:

Input Trigger Output wave Capacitor output


71

Precautions:



Result: The input and output waveforms of 555 timer monostable Multivibrator are observed as shown

in Fig 2(a), (b), (c).


MONOSTABLE

MULTIVIBRATOR

USING IC555

PULSEWIDTH


72


73

Inferences: Output pulse width depends only on external components RA and C connected to IC555.

Viva Questions:

1. Is the triggering given is edge type or level type? If it is edge type, trailing or raising edge?

Ans: Edge type and it is trailing edge

2. What is the effect of amplitude and frequency of trigger on the output?

Ans: Output varies proportionally.

3. How to achieve variation of output pulse width over fine and course ranges?

Ans: One can achieve variation of output pulse width over fine and course ranges by

varying capacitor and resistor values respectively

4. What is the effect of Vcc on output?

Ans: The amplitude of the output signal is directly proportional to Vcc

5. What are the ideal charging and discharging time constants (in terms of R and C) of capacitor

voltage?

Ans: Charging time constant T=1.1RC Sec

Discharging time constant=0 Sec

6. What is the other name of monostable Multivibrator? Why?

Ans: i) Gating circuit .It generates rectangular waveform at a definite time and thus could be used in

gate parts of the system.

ii) One shot circuit. The circuit will remain in the stable state until a trigger pulse is received. The

circuit then changes states for a specified period, but then it returns to the original state.

7. What are the applications of monostable Multivibrator?

Ans: Missing Pulse Detector, Frequency Divider, PWM, Linear Ramp Generator


74

Circuit Diagram:

Fig.1 555 Astable Circuit


75

EXP NO: DATE:

IC 555 Timer - Astable Operation Circuit

Aim: To generate unsymmetrical square and symmetrical square waveforms using IC555.

Apparatus required:


1 IC 555 1

2 Resistors 3.6kΩ,7.2kΩ Each one


4 Diode OA79 1



Theory:

When the power supply VCC is connected, the external timing capacitor ‘C” charges towards VCC

with a time constant (RA+RB) C. During this time, pin 3 is high (≈VCC) as Reset R=0, Set S=1 and this

combination makes Q =0 which has unclamped the timing capacitor ‘C’.

When the capacitor voltage equals 2/3 VCC, the upper comparator triggers the control flip flop on

that Q =1. It makes Q1 ON and capacitor ‘C’ starts discharging towards ground through RB and

transistor Q1 with a time constant RBC. Current also flows into Q1 through RA. Resistors RA and RB

must be large enough to limit this current and prevent damage to the discharge transistor Q1. The

minimum value of RA is approximately equal to VCC/0.2 where 0.2A is the maximum current through the

ON transistor Q1.

During the discharge of the timing capacitor C, as it reaches VCC/3, the lower comparator is

triggered and at this stage S=1, R=0 which turns Q =0. Now Q =0 unclamps the external timing

capacitor C. The capacitor C is thus periodically charged and discharged between 2/3 VCC and 1/3 VCC

respectively. The length of time that the output remains HIGH is the time for the capacitor to charge from

1/3 VCC to 2/3 VCC. The capacitor voltage for a low pass RC circuit subjected to a step input of VCC volts

is given by VC = VCC [1- exp (-t/RC)]

Total time period T = 0.69 (RA + 2 RB) C ; f= 1/T = 1.44/ (RA + 2RB) C


76

Model calculations:

Given f=1 KHz. Assuming c=0.1μF and D=0.25

1 KHz = 1.44/ (RA+2RB) x 0.1x10-6 and 0.25 =( RA+RB)/ (RA+2RB)

Solving both the above equations, we obtain RA & RB as

RA = 7.2K Ω

RB = 3.6K Ω

Design:

Formulae: f= 1/T = 1.44/ (RA+2RB) C

Duty cycle (D) = tc/T = RA + RB/(RA+2RB)


77

Procedure:

I) Unsymmetrical Square wave

1. Connect the circuit as per the circuit diagram shown without connecting the diode OA 79.

2. Observe and note down the waveform at pin 6 and across timing capacitor.

3. Measure the frequency of oscillations and duty cycle and then compare with the given values.

4. Sketch both the waveforms to the same time scale.

II) Symmetrical square waveform generator:

1. Connect the diode OA79 as shown in Figure to get D=0.5 or 50%.

2. Choose Ra=Rb = 10KΩ and C=0.1μF

3. Observe the output waveform, measure frequency of oscillations and the duty cycle and then sketch

the o/p waveform.


78

Waveforms:

Fig 2(a): Unsymmetrical square wave output

(b): Capacitor voltage of Unsymmetrical square wave output

(c): Symmetrical square wave output

Sample Readings:

Parameter Unsymmetrical Symmetrical

Voltage VPP

Time period T

Duty cycle


79

Precautions:



Result:

Both unsymmetrical and symmetrical square waveforms are obtained and time period at the

output is calculated.


ASTABLE

MULTIVIBRATOR

USING IC555 –

DUTY CYCLE


80


81

Inferences: Unsymmetrical square wave of required duty cycle and symmetrical square waveform

can be generated.

Viva Questions:

1. What is the effect of C on the output?

Ans: Time period of the output depends on C

2. How do you vary the duty cycle?

Ans: By varying R A or RB.

3. What are the applications of 555 in astable mode?

Ans: FSK Generator, Pulse Position Modulator, Square wave generator

4. What is the function of diode in the circuit?

Ans: To get symmetrical square wave.

5. On what parameters Tc and Td designed?

Ans: R A , RB and C

6. What are charging and discharging times

Ans: The time during which the capacitor charges from (1/3) Vcc to (2/3) Vcc

is equal to the time the output is high is known as charging time and is

given by Tc=0.69(RA+RB)C

The time during which the capacitor discharges from (2/3) Vcc to (1/3) Vcc is equal to the

time the output is low is known as discharging time and is given by Td=0.69(RB) C.


82

Circuit Diagrams:

Fig 1: Schmitt trigger circuit using IC 741


83

EXP NO: DATE:

Schmitt Trigger Circuits- using IC 741 & IC 555

Aim: To design the Schmitt trigger circuit using IC 741 and IC 555

Apparatus required:


1 IC 741 - 1

2 555IC - 1


4 Multimeter 1

5 Resistors 100 Ω

56 KΩ

2

1

6 Capacitors 0.1 μf, 0.01 μf Each one

7 Regulated power supply (0 -30V),1A 1

Theory:

The circuit shows an inverting comparator with positive feed back. This circuit converts orbitrary

wave forms to a square wave or pulse. The circuit is known as the Schmitt trigger (or) squaring circuit.

The input voltage Vin changes the state of the output Vo every time it exceeds certain voltage levels called

the upper threshold voltage Vut and lower threshold voltage Vlt.

When Vo= - Vsat, the voltage across R1 is referred to as lower threshold voltage, Vlt. When

Vo=+Vsat, the voltage across R1 is referred to as upper threshold voltage Vut. The comparator with positive

feed back is said to exhibit hysterisis, a dead band condition.


84

Fig 2: Schmitt trigger circuit using IC 555


85

Design:

Vutp = [R1/(R1+R2 )](+Vsat)

Vltp = [R1/(R1+R2 )](-Vsat)

Vhy = Vutp – Vltp

=[R1/(R1+R2)] [+Vsat – (-Vsat)]

Procedure:

1. Connect the circuit as shown in Fig 1 and Fig2.

2. Apply an orbitrary waveform (sine/triangular) of peak voltage greater than UTP to the input of a

Schmitt trigger.

3. Observe the output at pin6 of the IC 741 and at pin3 of IC 555 Schmitt trigger circuit by varying the

input and note down the readings as shown in Table 1 and Table 2

4. Find the upper and lower threshold voltages (Vutp, VLtp) from the output wave form.


86

Wave forms:

Fig 3: (a) Schmitt trigger input wave form

(b) Schmitt trigger output wave form

Sample readings:

Table 1:

Parameter Input Output

741 555

Voltage( Vp-p) 3.6 4

Time period(ms) 0.72 1

Table 2:

Parameter

Vutp

Vltp


87

Precautions:



Results:

UTP and LTP of the Schmitt trigger are obtained by using IC 741 and IC 555 as shown in Table 2.


SCHMITT

TRIGGER USING

IC741-UTP,LTP

SCHMITTTRIGGER

USING IC 555-

UTP,LTP

Viva Questions:

1. What is the other name for Schmitt trigger circuit?

Ans: Regenerative comparator

2. In Schmitt trigger which type of feed back is used?

Ans: Positive feedback.

3. What is meant by hysteresis?

Ans: The comparator with positive feedback is said to be exhibit hysteresis, a deadband

condition. When the input of the comparator is exceeds Vutp, its output switches from + Vsat to - Vsat and

reverts back to its original state,+ Vsat ,when the input goes below Vltp

4. What are effects of input signal amplitude and frequency on output?

Ans: The input voltage triggers the output every time it exceeds certain voltage levels (UTP and

LTP). Output signal frequency is same as input signal frequency.

Inferences: Schmitt trigger produces square waveform from a given signal.


88

Fig: LM 565 VCO with constant control voltage.


89

EXP NO: DATE:

IC 565 – PLL APPLICATIONS VCO

Aim: To Design a Phase Locked Loop Application (Voltage Controlled Oscillator) using IC LM565.

Apparatus Required:

S. No. Component Specification Quantity

1 IC LM 565 1

2 Resistors 1.5k 1

10k 1

4.7k 2

2k 1

3 Capacitor 0.047μF,

0.1μF 1

4 Variable Resistor 10k 1

5 Fixed Power Supply ±15V 1

6 Connecting Wires Single Strand As Required

7 CRO 0-30MHz 1

8 CRO Probes Crocodile Clips 3 9 Bread Board 1

Theory:

This oscillator uses a special IC chip, the LM565 that is designed to function as a phase locked loop

(PLL). The chip contains a VCO (which we will utilize in this experiment) and a phase detector. A

combination of an input control voltage on pin 7 and the RC time constant formed by the components

on pins 8 and 9 set the VCO output frequency. The VCO within the LM565 is not designed like a

conventional oscillator. It is really a current controlled oscillator. Remember that as the charging

current in a capacitor is increased, the rate of capacitor charging (as evidenced in its voltage rise) also

increases. The same is true for capacitor discharging as well. The LM565 simply translates the

control voltage on pin 7 into a charging and discharging current for the timing capacitor, C1. So

what is the function of the resistors on pin 8? The resistors on pin 8 also help set the charge and

discharge current for the timing capacitor C1. In other words, the output frequency of the LM565

VCO depends on three factors:

1) The control voltage on pin 7;

2) The total resistance on pin 8 (R3 and R4);

3) The capacitance on pin 9 (C1).

When a capacitor is charged by a constant current, its voltage rises linearly (straightline).

Thus, one of the output waveforms of the LM565 is a triangle wave. The other output is a square

wave -- the result of the triangle wave going through a Schmitt trigger.


90


91

Two different LM565 VCO circuits will be examined in this experiment, and they are

shown in Figures 1 and 2. In Figure 1, the control voltage of the VCO is held constant by

resistors R1 and R2, and the RC time-constant is varied by R3. (Note that the total resistance Rt

in Figure 1 is the series combination of R3 and R4). In Figure 2, the timing resistance Rt is equal

to R2, and is constant. A potentiometer has been substituted in R1's place, allowing the control

voltage to be varied over a range of approximately 7.5 V to 15 V. Note that the control voltage

should be adjusted to be in the range 11.25 V to 15 V in part two of this experiment.

Procedure:

1. Connections are made as per the circuit diagram.

2. Measure the output voltage and frequency of both triangular and squares.

3. Vary the values of R1 and C1 and measure the frequency of the waveforms.

4. Compare the measured values with the theoretical values.

Precautions:

1. Connect the wires properly.

2. Maintain proper Vcc levels.

Result:

The NE/SE 565 is operated as Voltage Controlled Oscillator also the output frequency for

various values of R1 and C1 are observed.

Viva Questions:

1. What are the applications of VCO?

2. Draw the pin diagram of NE/SE 565.

3. What is the need of connecting 0.0047μF capacitor between pin 5 and pin 6?


92

Circuit Diagram:

Fig1: Voltage Controlled Oscillator


93

EXP NO: DATE:

IC 566 – VCO Applications

Aim: i) To observe the applications of VCO-IC 566

ii) To generate the frequency modulated wave by using IC 566

Apparatus required:

S.No Equipment/Component Name Specifications/Value Quantity

1 IC 566 - 1

2 Resistors 10KΩ

1.5KΩ

2

1

3 Capacitors 0.1 μF

100 pF

1

1

4 Regulated power supply 0-30 V, 1 A 1

5 Cathode Ray Oscilloscope 0-20 MHz 1

6 Function Generator 0.1-1 MHz 1

Theory:

The VCO is a free running Multivibrator and operates at a set frequency fo called free running

frequency. This frequency is determined by an external timing capacitor and an external resistor. It can

also be shifted to either side by applying a d.c control voltage vc to an appropriate terminal of the IC. The

frequency deviation is directly proportional to the dc control voltage and hence it is called a “voltage

controlled oscillator” or, in short, VCO.

The output frequency of the VCO can be changed either by R1, C1 or the voltage VC at the

modulating input terminal (pin 5). The voltage VC can be varied by connecting a R1R2 circuit. The

components R1 and C1 are first selected so that VCO output frequency lies in the centre of the operating

frequency range. Now the modulating input voltage is usually varied from 0.75 VCC which can produce a

frequency variation of about 10 to 1.


94

Design:

1. Maximum deviation time period =T.

2. fmin = 1/T.

where fmin can be obtained from the FM wave

3. Maximum deviation, ∆f= fo - fmin

4. Modulation index β = ∆f/fm

5. Band width BW = 2(β+1) fm = 2 (∆f+fm)

6. Free running frequency,fo = 2(VCC -Vc) / R1C1VCC


95

Procedure:

1. The circuit is connected as per the circuit diagram shown in Fig1.

2. Observe the modulating signal on CRO and measure the amplitude and frequency of the signal.

3. Without giving modulating signal, take output at pin 4, we get the carrier wave.

4. Measure the maximum frequency deviation of each step and evaluate the modulating Index.

mf = β = ∆f/fm


96

Waveforms:

Sample readings:

VCC=+12V; R1=R3=10KΩ; R2=1.5KΩ; fm=1KHz

Free running frequency, fo = 26.1KHz

fmin = 8.33KHz

∆f= 17.77 KHz

β = ∆f/fm = 17.77

Band width BW ≈ 36 KHz


97

Precautions:



Result:

Frequency modulated waveforms are observed and modulation Index, B.W required for FM is

calculated for different amplitudes of the message signal.


VCO IC566- FREE

RUNNING

FREQUENCY

Inferences:

During positive half-cycle of the sine wave input, the control voltage will increase, the frequency

of the output waveform will decrease and time period will increase. Exactly opposite action will take

place during the negative half-cycle of the input as shown in Fig (b).

Viva Questions :

1. What are the applications of VCO?

Ans: VCO is used in FM, FSK, and tone generators, where the frequency needs to be controlled

by means of an input voltage called control voltage.

2. What is the effect of C1 on the output?

Ans: The frequency of the output decreases for an increase in C1.


98

Circuit Diagram:


99

EXP NO: DATE:

Voltage Regulator using IC723

Aim: To design a low voltage variable regulator of 2 to 7V using IC 723.

Apparatus required:

S.No

Equipment/Component name Specifications/Value Quantity

1 IC 723 - 1

2 Resistors 3.3KΩ,4.7KΩ,

100 Ω

Each one

3 Variable Resistors 1KΩ, 5.6KΩ Each one

4 Regulated Power supply 0 -30 V,1A 1

5 Multimeter 3 ½

digit display 1

Theory:

A voltage regulator is a circuit that supplies a constant voltage regardless of changes in

load current and input voltage variations. Using IC 723, we can design both low voltage and

high voltage regulators with adjustable voltages.

For a low voltage regulator, the output VO can be varied in the range of voltages Vo <

Vref, where as for high voltage regulator, it is VO > Vref. The voltage Vref is generally about 7.5V.

Although voltage regulators can be designed using Op-amps, it is quicker and easier to use IC

voltage Regulators.

IC 723 is a general purpose regulator and is a 14-pin IC with internal short circuit current

limiting, thermal shutdown, current/voltage boosting etc. Furthermore it is an adjustable voltage

regulator which can be varied over both positive and negative voltage ranges. By simply varying

the connections made externally, we can operate the IC in the required mode of operation.

Typical performance parameters are line and load regulations which determine the precise

characteristics of a regulator. The pin configuration and specifications are shown in the

Appendix-A.


100

Design of Low voltage Regulator :-

Assume Io= 1mA,VR=7.5V

RB = 3.3 KΩ

For given Vo

R1 = ( VR – VO ) / Io

R2 = VO / Io


101

Procedure:

a) Line Regulation:

1. Connect the circuit as shown in Fig 1.

2. Obtain R1 and R2 for Vo=5V

3. By varying Vn from 2 to 10V, measure the output voltage Vo.

4. Draw the graph between Vn and Vo as shown in model graph (a)

5. Repeat the above steps for Vo=3V

b) Load Regulation: For Vo=5V

1. Set Vi such that VO= 5 V

2. By varying RL, measure IL and Vo

3. Plot the graph between IL and Vo as shown in model graph (b)

4. Repeat above steps 1 to 3 for VO=3V.


102

Sample Readings:

a) Line Regulation:

Vo set to 5V Vo set to 3V

Model graphs:

Line Regulation:

Vi(V) Vo(V)

0

1

2

3

4

5

6

7

8

9

10

Vi(V) Vo(V)

0

1

2

3

4

5

6

7

8

9

10


103

Precautions:



Results:

Low voltage variable Regulator of 2V to 7V using IC 723 is designed. Load and Line

Regulation characteristics are plotted.


LINE

REGULATION

LOAD

REGULATION


104

b) Load Regulation:

Vo set to 5V

Vo set to 3V

Load Regulation:

IL (mA) Vo(V)

46

44

40

35

28

20

18

16

12

8

6

4

2

IL (mA) Vo(V)

24

22

20

18

16

14

12

10

8

6

4

2


105

Inferences:

Variable voltage regulators can be designed by using IC 723.

Viva Questions:

1. What is the effect of R1 on the output voltage?

Ans: R1 decreases for an increase in the output voltage.

2. What are the applications of voltage regulators?

Ans: Voltage regulators are used as control circuits in PWM, series type switch mode

supplies, regulated power supplies, voltage stabilizers.

3. What is the effect of Vi on output?

Ans: Output varies linearly with input voltage up to some value (o/p voltage+ dropout

voltage) and remains constant.


106

Circuit Diagrams:

Fig 1: Positive Voltage Regulator


107

EXP NO: DATE:

Three Terminal Voltage Regulators- 7805, 7809, 7912

Aim: To obtain the regulation characteristics of three terminal voltage regulators.

Apparatus required:


Name

Specifications/Values Quantity

1 Bread board - 1

2 IC7805 Refer appendix A 1



5 Multimeter 3 ½

digit display 1

6 Milli ammeter 0-150 mA 1

7 Regulated power supply 0-30 V 1

8 Connecting wires

9 Resistors pot 100Ω ,1k Ω Each one

Theory:

A voltage regulator is a circuit that supplies a constant voltage regardless of changes in

load current and input voltage. IC voltage regulators are versatile, relatively inexpensive and are

available with features such as programmable output, current/voltage boosting, internal short

circuit current limiting, thermal shunt down and floating operation for high voltage applications.

The 78XX series consists of three-terminal positive voltage regulators with seven voltage

options. These IC’s are designed as fixed voltage regulators and with adequate heat sinking can

deliver output currents in excess of 1A.

The 79XX series of fixed output voltage regulators are complements to the 78XX series

devices. These negative regulators are available in same seven voltage options.


108

Circuit Diagrams:

Fig 1: Positive Voltage Regulator

Fig 2: Negative Voltage Regulator


109

Typical performance parameters for voltage regulators are line regulation, load regulation,

temperature stability and ripple rejection. The pin configurations and typical parameters at 250C

are shown in the Appendix-B.

Procedure:

a) Line Regulation:

1. Connect the circuit as shown in Fig 1 by keeping S open for 7805.

2. Vary the dc input voltage from 0 to 10V in suitable stages and note down the output

voltage in each case as shown in Table1 and plot the graph between input voltage and

output voltage.

3. Repeat the above steps for negative voltage regulator as shown in Fig.2 for 7912 for an

input of 0 to -15V.

4. Note down the dropout voltage whose typical value = 2V and line regulation typical

value = 4mv for Vin =7V to 25V.

b) Load regulation:

1. Connect the circuit as shown in the Fig 1 by keeping S closed for load regulation.

2. Now vary R1 and measure current IL and note down the output voltage Vo in each case as

shown in Table 2 and plot the graph between current IL and Vo.

3. Repeat the above steps as shown in Fig 2 by keeping switch S closed for

negative voltage regulator 7912.

c) Output Resistance:

Ro= (VNL – VFL) Ω

IFL

VNL - load voltage with no load current

VFL - load voltage with full load current

IFL - full load current.


110

Sample readings:

a) Line regulation b) Load Regulation

1) IC 7805 1) IC 7805

2) IC 7809 2) IC 7809

Input Voltage

Vi,(V)

Output Voltage

Vo(V)

0

5

6

7

10

Load Current

IL(mA)

Output Voltage

Vo(V)

44

40

30

20

16

8

Input Voltage

Vi,(V)

Output Voltage

Vo(V)

0

5

10

12

14

Load Current

IL(mA)

Output Voltage

Vo(V)

56

48

33

25

21

15


111

Precautions:



Result:

Line and load regulation characteristics of 7805, 7809 and 7912 are plotted.


LINE

REGULATION IC-

7805,7809,7912

LOAD

REGULATION IC-

7805,7809,7912


112

3)7912 3) IC 7912

Graphs:

IC 7805

.

Input Voltage

Vi,(V)

Output Voltage

Vo(V)

0

-10

-12

-14

-15

Load Current

IL(mA)

Output Voltage

Vo(V)

56

46

38

28

24

20


113

Inferences:

Line and load regulation characteristics of fixed positive and negative three terminal

voltages are obtained. These voltage regulators are used in regulated power supplies.


114

IC 7809

IC7912

% load regulation = VNL - VFL x 100

VFL


115

Viva Questions:

1. Mention the IC number for a negative fixed three terminal voltage regulator of 12V.

Ans: IC 7912

2. Explain the significance of IC regulators in power supply

Ans: To get constant dc voltages.

3. What is drop-out voltage?

Ans: The difference between input and output voltages is called dropout voltage

4. What is the role of C1 and C2?

Ans: C1 is used to cancel the inductive effects.

C2 is used to improve the transient response of regulator.

4. What are C1 and C2 called?

Ans: Bypass capacitors


116

Fig 1: Binary weighted resistor DAC


117

EXP NO: DATE:

4 bit DAC using OP AMP

Aim: To design 1) weighted resistor DAC

2) R-2R ladder Network DAC

Apparatus required:


name

Specifications/Value Quantity

1 741 IC - 1

2 Resistors 1KΩ,2KΩ,4KΩ,

8KΩ

Each one

3 Regulated Power supply 0-30 V , 1A 1

4 Multimeter(DMM) 3 ½

digit display 1

5 connecting wires

6 Digital trainer Board 1

Theory:

Digital systems are used in ever more applications, because of their increasingly

efficient, reliable, and economical operation with the development of the microprocessor, data

processing has become an integral part of various systems Data processing involves transfer of

data to and from the micro computer via input/output devices. Since digital systems such as

micro computers use a binary system of ones and zeros, the data to be put into the micro

computer must be converted from analog to digital form. On the other hand, a digital-to-analog

converter is used when a binary output from a digital system must be converted to some

equivalent analog voltage or current. The function of DAC is exactly opposite to that of an

ADC.


118

Circuit Diagrams:

Fig 2: R – 2R Ladder DAC


119

A DAC in its simplest form uses an op-amp and either binary weighted resistors or R-2R ladder

resistors. In binary-weighted resistor op-amp is connected in the inverting mode, it can also be

connected in the non inverting mode. Since the number of inputs used is four, the converter is

called a 4-bit binary digital converter.

Design:

1. Weighted Resistor DAC

Vo = -Rf R

b

R

b

R

b

R

b DcBA

248

For input 1111, Rf = R = 4.7KΩ

Vo = - 512

1

4

1

8

1x

R

R f

Vo = - 9.375 V

2.R-2R Ladder Network:

Vo = -Rf R

b

R

b

R

b

R

b DcBA

24816

X 5

For input 1111, Rf = R= 1KΩ

Procedure:

1. Connect the circuit as shown in Fig 1.

2. Vary the inputs A, B, C, D from the digital trainer board and note down the output at pin 6.

For logic ‘1’, 5 V is applied and for logic ‘0’, 0 V is applied.

3. Repeat the above two steps for R – 2R ladder DAC shown in Fig 2.


120

Observations:

Weighted resistor DAC

S.No D C B A Theoretical Voltage(V) Practical Voltage(V)

1 0 0 0 0

2 0 0 0 1

3 0 0 1 0

4 0 0 1 1

5 0 1 0 0

6 0 1 0 1

7 0 1 1 0

8 0 1 1 1

9 1 0 0 0

10 1 0 0 1

11 1 0 1 0

12 1 0 1 1

13 1 1 0 0

14 1 1 0 1

15 1 1 1 0

16 1 1 1 1


121

Precautions:



Results:

Outputs of binary weighted resistor DAC and R-2R ladder DAC are observed.


4-bit DAC R-2R

LADDER

4-bit WEIGHTED

DAC


122

R-2R Ladder Network:

S.No D C B A Theoretical Voltage(V) Practical Voltage(V)

1 0 0 0 0

2 0 0 0 1

3 0 0 1 0

4 0 0 1 1

5 0 1 0 0

6 0 1 0 1

7 0 1 1 0

8 0 1 1 1

9 1 0 0 0

10 1 0 0 1

11 1 0 1 0

12 1 0 1 1

13 1 1 0 0

14 1 1 0 1

15 1 1 1 0

16 1 1 1 1

Model Graph:

Decimal Equivalent of Binary inputs


123

Inferences:

Different types of digital-to-analog converters are designed.

Viva Questions:

1. How do you obtain a positive staircase waveform?

Ans: By giving negative reference voltage.

2. What are the drawbacks of binary weighted resistor DAC?

Ans: Wide range of resistors is required in binary weighted resistor DAC.

3. What is the effect of number of bits on output ?

Ans: Accuracy degenerates as the number of binary inputs is increased beyond four.


124

APPENDIX-A

IC723

Pin Configuration

Specifications of 723:

Power dissipation : 1W

Input Voltage : 9.5 to 40V

Output Voltage : 2 to 37V

Output Current : 150mA for Vin-Vo = 3V

10mA for Vin-Vo = 38V

Load regulation : 0.6% Vo

Line regulation : 0.5% Vo


125

APPENDIX-B

Pin Configurations:

78XX 79XX

Plastic package

Typical parameters at 25oC:

Parameter LM 7805 LM 7809 LM 7912

Vout,V 5 9 -12

Imax,A 1.5 1.5 1.5

Load Reg,mV 10 12 12

Line Reg,mV 3 6 4

Ripple Rej,dB 80 72 72

Dropout 2 2 2

Rout,mΩ 8 16 18

ISL,A 2.1 0.45 1.5


126

REFERENCES

1. D.Roy Choudhury and Shail B.Jain, Linear Integrated Circuits, 2nd

edition, New Age

International.

2. James M. Fiore, Operational Amplifiers and Linear Integrated Circuits: Theory and Application,

WEST.

3. Malvino, Electronic Principles, 6th edition, TMH

4. Ramakant A. Gayakwad, Operational and Linear Integrated Circuits,4th edition, PHI.

5. Roy Mancini, OPAMPs for Everyone, 2nd

edition, Newnes.

6. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3rd edition, TMH.

7. William D. Stanley, Operational Amplifiers with Linear Integrated Circuits, 4th edition, Pearson.

8. www.analog.com

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