Digital block implementation methodology for a 130nm process

Digital block implementation methodology for a 130nm processMicroelecronics User Group meeting

TWEPP 2009 – Paris

Sandro BonaciniCERN PH/ESE

[email protected]

Sandro Bonacini - PH/ESE - [email protected]

Motivation

Implementation of digital blocks for small (~200 kgate) logic cores for digital or mixed signal ASICs

Using the IBM 130 nm standard cell library Separate substrate/ground and n-well/VDD biasing for mixed

signal designs

Defined methodology compatible with mixed signal design flows Open Access based


Design flow components Tools

Virtuoso 6.1.3 (OA based) SOC Encounter 7.1 Conformal 7.2 EXT 7.1.2 (QRC) Assura 3.2 Calibre 2008.3

Design Kits IBM CMOS8RF DM design kit V1.6

3 thin, 2 thick, 3 RF metals. IBM CMOS8RF LM design kit V1.6

6 thin, 2 thick metals.


Digital design flowRTL synthesis

Floorplanning& power routing

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

SignoffRC extraction

Timing analysis

DRC

DFM

LVS

Logical Equivalence

CheckingClock tree synthesis

Routing

Timing optimization

Timing optimization

Tape-out

Automated task

User task


RTL compilerscript [.tcl]

Abstract layoutDefinition [.lef]

Capacitancetables [.CapTbl]

Max timingLiberty libraries

[.lib]

Synthesis

RTL synthesis

RTL description[.v] / [.vhd]

Timingconstraints

[.sdc]

Mapped netlist[.v]

Conformal script[.lec]

Synthesis,mapping andtiming reports

Timing constraints: Clock definitions Input delays,

fanout, transition, etc.

Output load, etc.


RTL Compiler [rc]




Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization


Timing analysis

DRC

DFM

LVS

Logical Equivalence


Routing

Timing optimization

Timing optimization

Tape-out

Automated task

User task

Logical Equivalence

Checking


Logic Equivalence Checking

Tool: Conformal

Logical Equivalence

Checking

Max timingLiberty libraries

[.lib]

Mapped netlist[.v]

Conformal script[.lec]


LECreport


Synthesized netlist

User RTL code




Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization


Timing analysis

DRC

DFM

LVS

Logical Equivalence


Routing

Timing optimization

Timing optimization

Tape-out

Automated task

User task



Tool: Encounter

Design import and floorplanning

Mapped netlist[.v]


Open AccessStandard cells

library [.oa]

QX tech file[.tch]

Capacitancetables [.CapTbl]

Min/Max timingLiberty libraries

[.lib]

Open AccessFloorplanned

Design[.oa]

ReportsFloorplanning

& power routing


Design import


Floorplanning & power routing

Define Chip/core size target area utilization I/O placement module placement in

case of TMR or other special constraints

Power planning/routing Core/block rings and

stripes




Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization


Timing analysis

DRC

DFM

LVS

Logical Equivalence


Routing

Timing optimization

Timing optimization

Tape-out

Automated task

User task

Placement


Placement

Encounter command file

Placement

Scan-chain reorder

Open AccessFloorplannedDesign [.oa]

Connect cells power/ground

Add tap cells

Open AccessPlaced

Design [.oa]

Reports


Power/ground connections

Placement

Tap cellsStandard cells




Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization


Timing analysis

DRC

DFM

LVS

Logical Equivalence


Routing

Timing optimization

Timing optimization

Tape-out

Automated task

User task

Congestion analysis


Congestion analysis

Use Encounter Trialroute to estimate congested areas

Manually add placement partial blockage

Change position of I/Os or blocks

…or increase number of routing metals

Open AccessPlaced

Design [.oa]

Congestion analysis

Placement optimization

Open AccessPlaced

Design [.oa]




Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization


Timing analysis

DRC

DFM

LVS

Logical Equivalence


Routing

Timing optimization

Timing optimization

Tape-out

Automated task

User task

Timing optimization

Clock tree synthesis

Routing

Timing optimization

Timing optimization


Automatic P&R steps

Timing optimization

Open AccessPlaced

Design [.oa]

Clock tree synthesis

Routing

Open AccessRouted

Design [.oa]

Timing optimization

Timing optimization

Reports


Clock tree synthesis & signal routing




Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization


Timing analysis

DRC

DFM

LVS

Logical Equivalence


Routing

Timing optimization

Timing optimization

Tape-out

Automated task

User task


Timing analysis

DFM


Design for manufacturing


Cells & metal fill

Open AccessRouted

Design [.oa]

Antenna fix

Via optimization

Timing analysis

Open AccessFinal

Design [.oa]

Signoff timingreport

Delay file[.sdf]

Final netlist[.v]

Signal integrity analysis


Antenna fix

Re-routes long nets

Inserts tie-down diodes


Via optimization


Cells & metal fill


Timing closure

If signoff timing analysis reports violations increase buffer sizes add extra buffers reroute signals check constraints exploit useful skew annotate native post-route RC

extraction tool re-run optimization




Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization


Timing analysis

DRC

DFM

LVS

Logical Equivalence


Routing

Timing optimization

Timing optimization

Tape-out

Automated task

User task

DRC

LVS

Logical Equivalence

Checking


Virtuoso

OA design is present in Virtuoso Easily

included in a mixed-signal chip


Thank you…

Design flow …is soon to be available

Implementation of digital blocks Using the IBM 130 nm standard cell library Defined methodology compatible with mixed signal design

flows

Open Access based

Digital block implementation methodology for a 130nm process

Documents

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