Digilab 7-Segment Displays Lab 4. selyInstruction name “000”true if b = a false otherwise =...
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Digilab 7-Segment Displays Lab 4
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Transcript of Digilab 7-Segment Displays Lab 4. selyInstruction name “000”true if b = a false otherwise =...
Digilab 7-Segment Displays
Lab 4
Lab 4
a(n-1:0)y(n-1:0)
sel(2:0)
n-line
ALU3
b(n-1:0)
sel y Instruction name
“000” true if b = afalse otherwise
=
“001” true if b /= afalse otherwise
<>
“010” true if b < a (unsigned)false otherwise
U<
“011” true if b > a (unsigned)false otherwise
U>
“100” true if b <= a (unsigned)false otherwise
U<=
“101” true if b < a (signed)false otherwise
<
“110” true if b > a (signed)false otherwise
>
“111” true if b <= a (signed)false otherwise
<=
Digilab2 – DIO1 Boards
Four 7-segmentdisplays
dig1 dig2 dig3 dig4
Digilab2 Board – Common Anodes
A1 A2 A3 A4
AtoG(6 downto 0)
Pins
Pins
switches
7-segment displaysLEDs
pushbuttons
Digilab XLA
Digilab Board
dig3 dig2 dig1dig4
Digilab XLA Board – Common Anodes
A4 A3 A2 A1
CA CB CC CD CE CF CG
Pins
Pins
7-Segment Decoder
a
b
c
d
e
f
g
dp
a b c d e f g dp
q0
q1
q2
q3
seg7dec
a-g LOW to turn on segment
library IEEE;use IEEE.std_logic_1164.all; entity seg7dec is port (q: in STD_LOGIC_VECTOR(3 downto 0);
AtoG: out STD_LOGIC_VECTOR(6 downto 0));end seg7dec;
7-Segment Decoder
architecture seg7dec_arch of seg7dec isbegin process(q) begin case q is when "0000" => AtoG <= "0000001"; when "0001" => AtoG <= "1001111"; when "0010" => AtoG <= "0010010"; when "0011" => AtoG <= "0000110"; when "0100" => AtoG <= "1001100"; when "0101" => AtoG <= "0100100"; when "0110" => AtoG <= "0100000"; when "0111" => AtoG <= "0001101"; when "1000" => AtoG <= "0000000"; when "1001" => AtoG <= "0000100"; when "1010" => AtoG <= "0001000"; when "1011" => AtoG <= "1100000"; when "1100" => AtoG <= "0110001"; when "1101" => AtoG <= "1000010"; when "1110" => AtoG <= "0110000"; when others => AtoG <= "0111000"; end case; end process;end seg7dec_arch;
Digilab2 Board – Common Anodes
A1 A2 A3 A4
AtoG(6 downto 0)
Pins
Pins
Multiplex displays
1 0 0 0
0 0 0 0 1 1 0
Multiplex displays
0 1 0 0
0 0 0 1 1 1 1
Multiplex displays
0 0 1 0
1 0 0 1 1 0 0
Multiplex displays
0 0 0 1
0 1 1 1 0 0 0
Lab 4
ALU3
Acode
seg7dec
Lab4
SW(5:8)
SW(1:4)
cclk
BTN4
AtoG(6:0)
A(1:4)Aen(1:4)
Asel(1:0)
a
b
y
sel
y1
q1(2:0)
“1111”
clkdivctr2bit
clk
clr
q
IBUFG
mclk
bnbnbuf
q1(1:0)
q1(2)
LD(1:8)
ldg‘1’
A(1:4)
led
signal clkdiv: std_logic_vector(23 downto 0);begin
-- Divide the master clock (50MHz) down -- to a lower frequency.process (mclk)begin
if mclk = '1' and mclk'Event thenclkdiv <= clkdiv + 1;
end if;end process;
cclk <= clkdiv(17); -- 190 Hz = 50MHz/2^18
-- A 2-bit up-counterlibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all; entity ctr2bit is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (1 downto 0) );end ctr2bit;
ctr2bit.vhd
architecture ctr2bit_arch of ctr2bit isbeginprocess (clk, clr)variable COUNT: STD_LOGIC_VECTOR (1 downto 0);begin if clr = '1' then q <= "00"; elsif clk'event and clk='1' then COUNT := COUNT + 1; q <= COUNT; end if;end process;end ctr2bit_arch;
ctr2bit.vhd
Lab 4
ALU3
Acode
seg7dec
Lab4
SW(5:8)
SW(1:4)
cclk
BTN4
AtoG(6:0)
A(1:4)Aen(1:4)
Asel(1:0)
a
b
y
sel
y1
q1(2:0)
“1111”
clkdivctr2bit
clk
clr
q
IBUFG
mclk
bnbnbuf
q1(1:0)
q1(2)
LD(1:8)
ldg‘1’
A(1:4)
led
library IEEE;use IEEE.std_logic_1164.all; entity Acode is port ( Aen: in STD_LOGIC_VECTOR (3 downto 0); Asel: in STD_LOGIC_VECTOR (1 downto 0); A: out STD_LOGIC_VECTOR (3 downto 0) );end Acode;
Acode.vhd
architecture Acode_arch of Acode isbegin process(Aen, Asel) begin A <= "0000"; case Asel is when "00" => if Aen(1) = '1' then A <= "1000"; end if; when "01" => if Aen(2) = '1' then A <= "0100"; end if; when "10" => if Aen(3) = '1' then A <= "0010"; end if; when others => if Aen(4) = '1' then A <= "0001"; end if; end case; end process; end Acode_arch;
Acode.vhd
Lab 4
ALU3
Acode
seg7dec
Lab4
SW(5:8)
SW(1:4)
cclk
BTN4
AtoG(6:0)
A(1:4)Aen(1:4)
Asel(1:0)
a
b
y
sel
y1
q1(2:0)
“1111”
clkdivctr2bit
clk
clr
q
IBUFG
mclk
bnbnbuf
q1(1:0)
q1(2)
LD(1:8)
ldg‘1’
A(1:4)
led
-- System Library Components
component IBUFGport (
I : in STD_LOGIC; O : out std_logic
);end component;
U00: IBUFG port map (I => bn, O => bnbuf);
ALU3
Acode
seg7dec
Lab4
SW(5:8)
SW(1:4)
cclk
BTN4
AtoG(6:0)
A(1:4)Aen(1:4)
Asel(1:0)
a
b
y
sel
y1
q1(2:0)
“1111”
clkdivctr2bit
clk
clr
q
IBUFG
mclk
bnbnbuf
q1(1:0)
q1(2)
LD(1:8)
ldg‘1’
A(1:4)
led
