Differential Amplifiers 10

8/22/2019 Differential Amplifiers 10

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1

Differential Amplifiers

1. General Considerations

2. Bipolar Differential Pair

3. MOS Differential Pair

4. Cascode Differential Amplifiers

5. Offset Voltage

6. Common-Mode Rejection

7. Distortion in Differential Pairs

8. Differential Pair with Active LoadFrancisco Duque

E.I.I., UEx2012-2013


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Differential Amplifiers 2


Linear

System

Linear i ty pr in cip le

)(1 tv

)(2 tv )()( 2 tvktvo

)(1 tva

)(2 tvb

)()( 1 tvktvo )()( 1 tvaktvo

)()( 2 tvbktvo

)()( 21 tvbtva )()()( 21 tvbtvaktvo

Linear

System

Linear

System

Linear

System

Linear

System


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Two-signals representat ion: CM and DM components

2

)()()( 21

tvtvtv

cm

)()()( 21 tvtvtvdm

2

)()()(1

tvtvtv dmcm

2

)()()(2

tvtvtv dmcm

)(2, tvi

)(1, tvi

)(1, tvo

)(2, tvo

)(, tv dmi

)(, tv cmi)(, tv cmo

)(, tv dmo

The response of any linear system with two input signals

can be described in terms of its response to CM input

signals (common-mode response) and its response to DM

input signals (differential response).

Linear

SystemLinear

System


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An audio amplifier is constructed above that takes on a

rectified AC voltage as its supply and amplifies an audio

signal from a microphone.

Audio amplifier example to understand the need

for differential circuits


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(1) Humming Noise in Audio Amplifier Example

However, VCCcontains a ripple from rectification that leaks

to the output and is perceived as a humming noise by the

user. Voutis measured respect to ground and differs by RCIC

from VCC.

CCCCout IRVV


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(1) Supply Ripple Rejection

Now Voutis not referenced to ground. Instead, is measured

respect to another point that itself experiences the same

supply ripple.

Since both node Xand Ycontain the ripple, their difference

will be free of ripple.

invYX

rY

rinvX

vAvv

vv

vvAv

Perfect symmetrical circuit(Q1=Q2 and RC1=RC2).


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(1) Ripple-Free Differential Output

Since the signal is taken as a difference between two nodes,an amplifierA 1 that senses differential signals is needed.


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(1) Common Inputs to Differential Amplifier

Signals cannot be applied in phase to the inputs of a differential

amplifier, since the outputs will also be in phase, producing

zero differential output.

0

YX

rinvY

rinvX

vv

vvAv

vvAv


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(1) Differential Inputs to Differential Amplifier

When the inputs are applied differentially, the outputs are

180 out of phase; enhancing each other when sensed

differentially.

Of course, all CM signals still being removed.

invYX

rinvY

rinvX

vAvv

vvAv

vvAv

2


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(1) Differential Signals

A pair of differential signals can be generated, among otherways, by a transformer.

Differential (DM) signals have the property that they sharethe same average value to ground and are equal inmagnitude but opposite in phase.


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(1) Single-ended vsDifferential Signals

Single-ended signals (referenced to ground)

Differential (balanced) signals

CM

CM

VtVV

VtVV

sin

sin

02

01


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(1) Differential Pair

With the addition of a tail current (IEE orISS), the circuits

above operate as an elegant, yet robust differential pair.

Ideally, differential pairs are perfectly symmetric structures.

Bipolar differential pair(Q1=Q2 and RC1=RC2)

MOS differential pair(M1=M2 and RD1=RD2)


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2. Bipolar Differential Pair

2

221

21

EE

CCCYX

EE

CC

BEBE

IRVVV

III

VV

Q1 and Q2 operate in the active region

Qual i tat ive Analys is: Common -Mode Reject io n

If the circuit is perfectly symmetric (matched) there is not

response (differential output signal) to any common-mode

signal (input signal, supply noise, etc.).

CMEE

CCC VI

RV 2


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(2) Common-Mode Rejection and Common-Mode

Voltage Range

Due to the fixed tail current source (ideal), the input common-

mode value can vary without changing the output common-

mode value. That is, the circuit rejects input CM variations.

To avoid saturation (Q1 and Q2 ), the collector voltages must not

fall below the base voltages

CM

EE

CCC V

I

RV 2


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(2) Differential Response (I)

CCY

EECCCX

C

EEC

VV

IRVV

I

II

02

1

Response to a large posi t ive input d i f ference

EECC III 21


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(2) Differential Response (II)

CCX

EECCCY

C

EEC

VV

IRVV

I

II

01

2

Response to a large negative inpu t dif ference

EECC III 21


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(2) Differential Pair Characteristics

None-zero differential input produces variations in output

currents and voltages, whereas common-mode input

produces no variations.

2

EE

CCC

IRV is called the output CM level.


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(2) Small-Signal Analysis

Since the input (base) to Q1 and Q2 rises and falls by the same

amount, and their emitters are tied together, the rise in IC1 has the

same magnitude as the fall in IC2.

II

I

II

I

EE

C

EE

C

2

2

2

1

Response to small inpu t dif ferences (quali tat ively

analysis)


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For small changes at inputs, the gms are the same, and the

respective increase and decrease ofIC1 and IC2 are the same,

node P must stay constant to accommodate these changes.

Therefore, node P can be viewed as AC ground node.

VgI

VgI

V

mC

mC

P

2

1

0

AC ground



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(2) Small-Signal Differential Gain

Since the output changes by -2gmVRCand input by 2V, the smallsignal gain isgmRC, similar to that of the CE stage. However, toobtain same gain as the CE stage, power dissipation is doubled.

Cm

Cm

in

out

v

RgV

RVg

V

VA

2

2


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(2) Large Signal Analysis (I)

T

inin

EE

C

T

inin

T

inin

EE

C

V

VV

II

V

VV

V

VVI

I

212

21

21

1

exp1

exp1

exp

EECC

C

CTinin

III

I

IVVV

21

2

121 ln

T

BE

SCV

VII exp


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(2) Large Signal Analysis (II)

T

ininEEC

outout

V

VVIR

VV

2tanh21

21

Input/Outpu t Character ist ic s

Linear Region

(almost)


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(2) Linear/Nonlinear Regions

The left column operates in linear region, whereas the right column

operates in nonlinear region.

EECCC IRV

CCV

2EECCC IRV


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(2) Equivalent Half Circuit

Since VPis grounded, we can treat the differential pair as two CE

half circuits, with its gain equal to one half circuits single-ended

gain.

Cm

inin

outout Rgvv

vv

21

21


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(2) Example: Intrinsic Differential Gain

Om

inin

outout rgvv

vv

21

21

The intrinsic gain of any circuit or device is the theoretical

maximum gain that it can provide. This is achieved when the load

has an infinite resistance (ideal current source).


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(2) Extension of AC Ground Concept

It can be shown that ifR1 = R2, and points A and B go up and

down by the same amount respectively, VX does not move.

By extension, any node in the axis of symmetry of a perfectly

matched circuit is an AC Ground Node.

021 XVRR


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(2) Half Circuit (Example I)

1311 |||| RrrgA OOmv

Equivalent half circuit

App l ication of the concept of AC ground


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(2) Half Circuit (Example II)

1311 |||| RrrgA OOmv




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(2) Half Circuit (Example III)

m

E

C

v

g

R

RA

1




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(2) Half Circuit (Example IV)

m

E

C

v

g

R

RA

1

2




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3. MOS Differential Pair

Similar to its bipolar counterpart, MOS differential pair produces

zero differential output as VCMchanges.

2

SS

DDDYXIRVVV

Qual i tat ive Analys is: Common -Mode Reject io n


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(3) Equilibrium Overdrive Voltage

The equilibrium overdrive voltage is defined as the overdrivevoltage (VOV = VGSVTH) seen by M1 and M2 when both of themcarry a current ofISS/2.

SS

equilTHGS IVV

L

WCoxn

22

THGSD VVI


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(3) Minimum Common-Mode Output Voltage

In order to maintain M1 and M2 in saturation, the common-

mode output voltage cannot fall below the value above.

This value usually limits voltage gain.

THCM

SS

DDD

VVI

RV 2


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(3) Differential Response


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(3) Small-Signal Response

Similar to its bipolar counterpart, the MOS differential pairexhibits the same AC ground node (P) and small signal gain.

Dmv

P

RgA

V

0


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(3) MOS Differential Pairs Large-Signal Response (I)

SSDD

ininDD

III

VVII

21

21,21 2

2,1,,

2

2

,,

2

2

2

,,

1

2/1

22

2/1

22

inindmi

equilTHGS

dmidmi

SS

SS

D

equilTHGS

dmidmi

SS

SS

D

VVV

VV

VVI

II

VV

VVI

II

(3) MOS Differential Pairs Large Signal Response


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(3) MOS Differential Pairs Large-Signal Response

(II)

2

2

,

,21

2/1

equilTHGS

dmi

dmiSSDDVV

VVIII


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(3) Maximum Differential Input Voltage (III)

There exists a finite differential input voltage that completely

steers the tail current ISS from one transistor to the other. This

value is known as the maximum differential input voltage.

equilTHGSinindmi

VVVVV 2max21max,

equilTHGSdmi VVV 2, );0(

21 SSDD III

ZONERATESLEW

(3) Contrast Between MOS and Bipolar Differential


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(3) Contrast Between MOS and Bipolar Differential

Pairs

In a MOS differential pair, there exists a finite differential

input voltage to completely switch the current from one

transistor to the other, whereas, in a bipolar pair that

voltage is infinite.

MOS Bipolar


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(3) The effects of Doubling the Tail Current

Since ISS is doubled and W/L is unchanged, the equilibriumoverdrive voltage for each transistor must increase byto accommodate this change, thus Vin,max increases byas well. Moreover, since ISS is doubled, the differentialoutput swing will double.

2

2


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(3) The Effects of Doubling W/L

Since W/L is doubled and the tail current remains unchanged,the equilibrium overdrive voltage will be lowered by toaccommodate this change, thus Vin,max will be lowered byas well. Moreover, the differential output swing will remainunchanged since neitherISS norRD has changed.

2

2


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(3) Small-Signal Analysis of MOS Differential Pair

When the Vi,dm is small compared to (VGS-VTH)equil=(ISS/)1/2, theoutput differential current is linearly proportional to it, and

small-signal model can be applied.

dmiSS

equilTHGS

dmi

dmiSSDDVI

VV

VVIII ,2

2

,

,21

2/1


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(3) AC Ground and Half Circuit

Applying the same analysis as the bipolar case, we willarrive at the same conclusion that node Pwill not move forsmall input signals and the concept of half circuit can beused to calculate the gain.

Cmv

P

RgA

V

0


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(3) MOS Differential Pair Half Circuit Example I

13

3

1 ||||1

0

OO

m

mvrr

ggA



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(3) MOS Differential Pair Half Circuit Example II

3

1

0

m

m

vg

gA



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(3) MOS Differential Pair Half Circuit Example III

mSS

DD

vgR

RA

12

2

0


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4. Cascode Differential Pair

133131

||OOOmmvrrrrggA

B ipo lar Case


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(4) Bipolar Telescopic Cascode

)||(|||| 575531331 rrrgrrrggA OOmOOmmv


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(4) Example: Bipolar Telescopic Parasitic Resistance

opOOmmv

OOmOop

RrrrggA

Rrr

RrrgrR

||)||(

2||||

2||||1

31331

157

15755


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(4) MOS Cascode Differential Pair

1331 OmOmv rgrgA

( ) OS C


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(4) MOS Telescopic Cascode

)||( 7551331 OOmOOmmv rrgrrggA

(4) E l MOS T l i P iti R i t


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(4) Example: MOS Telescopic Parasitic Resistance

)||(

]1[||

1331

77515

OmOopmv

OOmOop

rgrRgA

rrgRrR

5 Off t V lt


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5. Offset Voltage

Offset voltage is due to mismatches between components ordevices that ideally should be identical.

021

21

21

outoutout

inin

DDD

VVV

VV

RRR

RI

VVV

VV

RRR

RRR

SS

outoutout

inin

D

DD

D

DD

2

2

2

21

21

2

1

Output of fset vo l tage

(5) I t f d ff t lt


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(5) Input referred offset voltage

Input referred offset voltage (VOS) is the output offset voltagedivided by the small-signal gain.

VOS means the dc input differential voltage necessary tocompensate all the circuit mismatches and therefore, fix Vout = 0.

D

DSS

Dm

DSS

v

outout

OSR

RI

Rg

RI

A

VVV

1

21 2

02,1,. outoutoutOSdmin VVVVV

6 C M d R j ti


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6. Common-Mode Rejection

If the tail current source is not ideal, then when a input CMvoltage is applied, the currents in Q1 and Q2 and hence outputCM voltage, will change.

mEE

C

CMin

CMout

gR

R

V

V

2/1

2/

,

,

Effect of Fini te Tail Impedance

(6) Input CM Noise with Ideal and Non-Ideal Tail


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( ) p

Current

As it can be seen, the differential output voltages for both casesare the same. So, for small input CM noise the differential pair isnot affected.

EER EER

(6) CM t DM C i A


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(6) CM to DM Conversion, ACM-DM

If finite tail impedance and asymmetry are both present, thenthe differential output signal will contain a portion of inputcommon-mode signal.

SSm

D

CM

out

Rg

R

V

V

2/1

(6) Common Mode Rejection Ratio (CMRR)


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(6) Common-Mode Rejection Ratio (CMRR)

CMRR defines the ratio of wanted amplified differential input

signal to unwanted converted input common-mode noise that

appears at the output.

DMCM

DM

A

A

CMRR

7 Distortion in Differential Pairs


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General cons iderat ions fo r harmonic d istor t ion

Transfer characteristic (input vsoutput) is not a straight line in

circuits with active devices.

Both, small-signal and large-signal, have nonlinearity problems.

7. Distortion in Differential Pairs

NonlinearSystem)(tvin )(tvout

2

21 ininout vGvGv

Let us assume:where G1 and G2 are constant.

tBtBB

tVGtVGvtVv outin

12110

1

22

1211111

2coscos

coscoscos

2nd harmonic distortion is introduced:

1

22

B

BHD

2cos12

1cos2

(7) High order harmonic distortion


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(7) High order harmonic distortion

NonlinearSystem

)(tvin )(tvout

tBtBtBBvtVv

vGvGvGv

out

in

inininout

1312110

11

3

3

2

21

3cos2coscoscos

nthharmonic distortion:1B

BHD n

n

Power delivered at the fundamental frequency:L

R

BP

2

2

11

Total power output:

1

2

3

2

2

2

3

2

2

2

1 12

1PHDHD

RBBBP

L

Total Harmonic Distortion: 23

2

2

1 HDHDTHD

(7) Distortion in MOS Differential Pair


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SS

i

iSS

SS

i

iSSDDDI

VVI

I

VVIIII

42

1

41

32

21

xxxxx 2

11

16

1

8

1

2

111

325.0 3coscos34

1cos3



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tI

At

I

AAIIII

tAV

SSSS

SSDDD

i

1

3

1

3

21

1

3cos162

1cos

162

3

cos

01

22

BBHD

22

1

3

3 32

1

32

1

equilTHGSSS VV

A

I

A

B

B

HD

Cancellation of even harmonics is a typical performance feature

of differential circuit structures.

8 Differential Pair with Active Load


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Different ial to Single-ended Conversion

Many circuits require a differential to single-ended

conversion, however, the above topology is not very good.

8. Differential Pair with Active Load

(8) Supply Noise Corruption


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(8) Supply Noise Corruption

The most critical drawback of this topology is supply noise

corruption, since no common-mode cancellation mechanism

exists. Also, we lose half of the signal.

(8) Better Alternative


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(8) Better Alternative

This circuit topology performs differential to single-ended

conversion with no loss of gain.

(8) Active Load


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(8) Active Load

With current mirror used as the load, the signal currentproduced by the Q1 can be replicated onto Q4.

This type of load is different from the conventional static

load and is known as an active load.

(8) Differential Pair with Active Load


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(8) Differential Pair with Active Load

The input differential pair decreases the current drawn from

RL by I and the active load pushes an extra I into RL bycurrent mirror action; these effects enhance each other.

(8) Active Load vs Static Load


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(8) Active Load vs. Static Load

The load on the left responds to the input signal andenhances the single-ended output, whereas the load on theright does not.

(8) MOS Differential Pair with Active Load


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(8) MOS Differential Pair with Active Load

Similar to its bipolar counterpart, MOS differential pair can

also use active load to enhance its single-ended output.

(8) Asymmetric Differential Pair


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(8) Asymmetric Differential Pair

Because of the vastly different resistance magnitude at the

drains of M1 and M2, the voltage swings at these two nodes

are different and therefore node P cannot be viewed as a

virtual ground.

(8) Thevenin Equivalent of the Input Pair


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(8) Thevenin Equivalent of the Input Pair

oNThev

ininoNmNThev

rR

vvrgv

2

)( 21

(8) Simplified Differential Pair with Active Load


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(8) Simplified Differential Pair with Active Load

)||(21

OPONmN

inin

out rrgvv

v

(8) Proof of VA


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I

A

(8) Proof of VA

Differential Amplifiers 10

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