DfR Advanced Packaging
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© 2004 - 2007 © 2004 - 2010 © 2004 – 2010 Advanced Packaging DfR Solutions Open House December 14, 2011 Presented by: Greg Caswell
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description of several advanced packaging technologies along with issues and resolutions.
Transcript of DfR Advanced Packaging
© 2004 - 2007© 2004 - 2010© 2004 – 2010
Advanced Packaging
DfR Solutions Open House
December 14, 2011
Presented by: Greg Caswell
© 2004 - 2007© 2004 - 2010
o Package on Package -3D(PoP)
o System in Package 3D (SiP)
o Through Silicon Via (TSV)
o Bottom Terminated Components
o QFN
o LFCSP
o .3 mm pitch CSP
o Copper Wire Bonding
Agenda
© 2004 - 2007© 2004 - 2010
Roadmap vs Market Application
© 2004 - 2007© 2004 - 2010
Benefits of PoP
o The benefits of PoP are well known. They include
o Less board real estate
o Better performance (shorter communication paths between the micro and memory)
o Lower junction temperatures (at least compared to stacked die)
o Greater control over the supply chain (opportunity to upgrade memory and multiple vendors)
o Easier to debug and perform F/A (again, compared to stacked die or multi-chip module or system in package)
o Ownership is clearly defined: Bottom package is the logic manufacturer, the top package is the memory manufacturer, and the two connections (at least for one-pass) are the OEM
© 2004 - 2007© 2004 - 2010
Benefits of PoP
o The benefits of PoP are well known. They include
o Less board real estate
o Better performance (shorter communication paths between the micro and memory)
o Lower junction temperatures (at least compared to stacked die)
o Greater control over the supply chain (opportunity to upgrade memory and multiple vendors)
o Easier to debug and perform F/A (again, compared to stacked die or multi-chip module or system in package)
o Ownership is clearly defined: Bottom package is the logic manufacturer, the top package is the memory manufacturer, and the two connections (at least for one-pass) are the OEM
© 2004 - 2007© 2004 - 2010
PoP addresses integration challenges to enable semiconductor advancements . . .
. . . to cost affectively deliver physical world benefits.
Smartphone advancements aided by PoP technology
and cost of ownership benefits.
© 2004 - 2007© 2004 - 2010
PoP
Stacked Packages = PoP – 3D 101
Double stack
Triple stack
Double stack
Courtesy: ASE
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8
Thermal Comparison
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PoP Assembly Process
o Assembly of PoP can be through
one or two reflows
o Most commonly single
reflow (aka, one-pass)
o Top package is typically
dipped before placement
o Flux (sticky) or solder paste
9
© 2004 - 2007© 2004 - 2010
1st Generation PoP – Infrastructure Development
OEMsArchitecture
stacking
12 major OEMs in Handset and DSC market adopting PoP
Industry
StandardsJEDEC – JC.11.2 Design guide, JC11.11 POD, JC-63 pin outs
Equipment Panasonic, Siemens, Fuji, Unovis, Assembléon, Hitachi
EMS / ODM 5 major EMS providers in production or development
Logic IDM 15 major IDMs adopted PoP
Memory IDM 8 major Memory suppliers adopted PoP
AmkorFull service – Develop, Design, Model, Standards, bottom,
top PoP, Modules, pre-stacked engineering samples, BLR
Practical Components – stocks Amkor 12, 14 & 15mm bottom / top DC samples
www.amkor.com Design, stacking, test and Brd level reliability (joint study papers)
© 2004 - 2007© 2004 - 2010
o Mold
o Material property
o Shrinkage
o Thickness
• Laminate Substrate– Properties– Thickness– Cu ratio– Routing
• Die attach– Material property– Thickness
• Die– Die size– Die Thickness
Design Factors Impacting Warpage
© 2004 - 2007© 2004 - 2010
Package Warpage
o Due to mismatch in CTE between the substrate, mold compound and die
o Die attach can also play a role
o High Tg mold compounds are used to balance CTE mismatch between die and substrate
o Effect of mold compound becomes negligible at reflow temperatures
12
© 2004 - 2007© 2004 - 2010
Warpage and Yields
13
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Warpage and Reflow Profile
14
Ramkumar, 2008 European Electronic Assembly Reliability Summit
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1st Gen PoP Technologies limit PoP I/O and Bottom Stacked
Die Density – Requiring New Technologyo Die stacking in bottom package requires thicker mold cap
o New memory architectures require higher I/O interfaces
o Higher Semiconductor density requires package size reduction
o Thin form factors and increased battery size require thinner PoP stacks
o Improved warpage control required when go thinner with higher density
o A new bottom PoP technology is needed to continue growth
Multiple die in bottom package0.50mm pitch
© 2004 - 2007© 2004 - 2010
Thru Mold Via Technology (TMV®)
o Enabling technology for next generation PoP reqmts
o Improves warpage control and PoP thickness reduction
o TMV removes bottlenecks for fine pitch memory interfaces
o Increases die to package size ratio (30%)
o Improves fine pitch board level reliability
o Supports Wirebond, FC, stacked die and passive
integration
© 2004 - 2007© 2004 - 2010
Construction and package stack-up for the TMV PoPTest Vehicle
Reference : "Surface Mount Assembly and Board Level Reliability for High
Density PoP (Package on Package) Utilizing Through Mold Via
Interconnect Technology - Joint Amkor and Sony Ericsson", Paper
© 2004 - 2007© 2004 - 2010
Categories of SiP – examples of 3DCategories of SiP – examples of 3D
Horizontal Placement
StackedStructure
Interposer Type
Interposer-less Type
Wire Bonding Type Flip Chip Type
Wire Bonding Type
Wire Bonding +Flip Chip Type Flip Chip Type
Terminal Through Via Type
Embedded StructureChip(WLP) Embedded + Chip on Surface Type
3D Chip EmbeddedType
WLP Embedded + Chip on Surface Type
© 2004 - 2007© 2004 - 2010
SiP: from Die to Package to Hybrid Stacking
The Road to 3D Packaging
2011 2012~2010 2013
die stacking
8 dies
4 dies
TRD PoP
PIP FCCSP
aMAP PoP
aWLP PoP
aMAP PoP(Cu pillar)
Bare-die FC PoP
3D IC PoP
Exposed-die aMAP PoP
2.5D IC SiP
CoC FBGA
Hybrid FCCSP
ASICASIC
EDS PoP
aEDSi PoP
Courtesy: ASE
© 2004 - 2007© 2004 - 2010
TSV Development
Courtesy:ASE
© 2004 - 2007© 2004 - 2010
Silicon Interposer
Chip 1 Chip 2
Si Interposer
65 nm ASICSi Interposer w/ TSV
Substrate
Courtesy ASE
© 2004 - 2007© 2004 - 2010
XBit: Aug 17, 2011: Samsung announcement of 32 Gbit Memory with TSV
Samsung TSV Implementation
© 2004 - 2007© 2004 - 2010
Through-Silicon-Vias
o Through Silicon Vias (TSV) are the next generation technology for system in package devices
o Similar to plated through holes in a PCB
o Promised advantages include
o Thinner packages
o Greater level of integration between active die.
o Process still being optimized and cost must be reduced for widespread adoption.
© 2004 - 2007© 2004 - 2010
� TSV is rarely justified by just miniaturization alone
� More cost-effective to thin, stack and wire bond
� Cost can be 2X-4X price of flip chip ($200/wafer is the goal) and 5X-10X the price of wire bonding
� TSV will be justified by performance
� Increase in inter-die I/O
� Increase in bandwidth
� Decrease in interconnect length
TSV (cont.)
24
http://www.intel.com/technology/itj/2007/v11i3/3-
bandwidth/6-architectures.htm (August 22, 2007)
© 2004 - 2007© 2004 - 2010
o Via First, before Front End of Line (FEOL)
o Vias etched in bare wafer prior to fab
o Not likely
o Back End of Line (BEOL)
o Via First, before BEOL
o Via Last, after BEOL
o Vias can be created at various stages of the process
o By the wafer provider, IC manufacturer, or packaging house
TSV Processes
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TSV Process – BEOL
© 2004 - 2007© 2004 - 2010
o Three primary failure mechanisms
o Cracking of the Copper Plating
o Cracking of the Silicon /Change in Resistance of Silicon
o Interfacial Delamination of Via Wall from Silicon
o Challenges
o The exact process and architecture (materials, design) for TSV has yet to be finalized
o Can lead to large changes in stress state
How Can Through Silicon Vias (TSV) Fail?
© 2004 - 2007© 2004 - 2010
o Via walls can be straight (etch) or tapered (laser)
o Vias can be filled (likely) or not filled (aka, annular)
TSV Design
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o Depending on Via First or Via Last design layout, TSV can have a ‘floor’ of copper
o Also known as Carpeted or Nailheading
TSV Design
S. Barnat et. al., EuroSIME 2010
© 2004 - 2007© 2004 - 2010
o Will the via be filled?
o If yes, with what material?
o Copper
o Tungsten
o Conductive polymer
TSV Materials
Why Tungsten?
Low CTE mismatch with
Silicon
© 2004 - 2007© 2004 - 2010
o Solid Fill (copper, nickel, tungsten, aluminum, etc.)o Most robust (fatigue)o High stress in silicono Longest processo Enhanced thermal performanceo Greater density (think filled microvias)
o Polymer Fillo Still robusto Reduced stress in silicono Shorter process, more expensive material
o No Fill (annular)o Least robusto Lowest stress in silicono Fastest process, lowest cost
Via Fill (Tradeoffs)
© 2004 - 2007© 2004 - 2010
o Will copper in TSV experience fatigue cracking?
o Classic circumferential fatigue cracking of copper plating is currently unlikely for two reasons
o Reason #1: Hole Fill
o Most TSV concepts seem to be moving to a solid plug design (fully filled)
o A partial fill or plated barrel likely a process defect (pinch off due to non-optimized leveler)
Cracking of Copper TSV
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o Filled PCB vias (copper, solder, or conductive fill) do not fail when subjected to temperature cycling
o KEY EXCEPTION
o Partially filled PCB vias fail faster
due to the presence of a stress concentration
Example: Filled PCB Vias
© 2004 - 2007© 2004 - 2010
o Reason #2: Unfilled Via and Compressive Stresso Unlike in PCB, the ‘matrix’ (i.e., silicon) has a lower coefficient of
thermal expansion (CTE) than the barrel
o There is also a lower CTE mismatch
o PCB: 50ppm vs. 17ppm (33) / TSV: 2ppm vs. 17ppm (-15)
o If electroplated, stress free state should be at room temperatureo Any increase in temperature, due to hot spots or change in ambient
conditions, will place the copper plating under an axial compressive stress
o The tensile stress then arises circumferentiallyo Could induce cracking along the length of
the via, but will not cause electrical failure
Cracking of Copper TSV (cont.)
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o Lu claimed very large stresses in the copper plating for annular TSV
Cracking of Copper TSV – Possible Exceptions
Lu, Dissertation, UTexas, 2010
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o Liu measured (XRD) similar stress levels in filled TSV
Cracking of Copper TSV – Possible Exceptions
Liu, ECTC, 2009
Note zero stress state
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o One publication seems to show stress-driven cracking of TSV, but little additional information is provided
Cracking of Copper TSV – Possible Exceptions (cont.)
J. McDonald, Thermal and
Stress Analysis Modeling for 3D
Memory over Processor Stacks,
SEMATECH Workshop on
Manufacturing and Reliability
Challenges for 3D IC’s using
TSV’s, 2008
© 2004 - 2007© 2004 - 2010
o Stresses within the silicon can be computed using plane-strain analytical solution known as Lamé stress solution
Cracking of Silicon – Single TSV
Cylindrical
o σxx and σyy are inplanestresses
o B is modulus, ΔαΔT is thermal mismatch strain, r is TSV radius
Cartesian
o σr and σθ are radial and circumferential stresses
o E is modulus, εT = (αf-αm)∆T (thermal mismatch strain), Dfis TSV diameter, υ is Poisson’s ratio
Ignores elastic mismatchLu, Dissertation, UTexas, 2010
Zhang, IEEE Trans. ED, 2011
© 2004 - 2007© 2004 - 2010
Stresses in Silicon
Zhang, IEEE Trans. ED, 2011
© 2004 - 2007© 2004 - 2010
o Are these stresses high enough to cracking semiconductor-grade silicon?
o Unlikely
o Fracture strengths of silicon wafers have been reported between 1 – 20 GPa
o Some debate about silicon and fatigue
o Dauskardt reports no fatigue behavior
o Ritchie reports fatigue behavior up to 0.5 fracture strength
Stresses in Silicon (cont.)
Ritchie, Failure of Silicon, 2003
© 2004 - 2007© 2004 - 2010
o This failure mechanism is the most likely failure mode of TSVs
o Very high stresses
o Very complex stresses
o Difficult to measure material properties
o Key material properties not controlled (i.e., fracture strength)
Interfacial Failure of TSV
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o Analysis by Dudek identified risk of micro cracking and delamination problems at the upper via pad in a local model.
o R. Dudek, et. al., Thermo-Mechanical Reliability Assessment for 3D Through-Si Stacking, EuroSimE, 2009
o Liu found that Cu/SiO2 interfacial cracks and SiO2 cohesive cracks are likely to initiate and propagate at the corners of electroplated Cu pads, where large stress gradients and plastic deformation exist
o X. Liu, et. al., Failure Mechanisms and Optimum Design for Electroplated Copper TSV, ECTC, 2009
Interfacial Delamination (cont.)
© 2004 - 2007© 2004 - 2010
o Interfacial delamination of TSVs was found to be mainly driven by a shear stress concentration at the TSV/Si interface
o Can result in TSV extrusion, fracturing the overlaying dielectric material
Interfacial Delamination
P. Garrou, “Researchers Strive for Copper TSV Reliability,” Semi Int, 03-Dec-2009.
© 2004 - 2007© 2004 - 2010
o Ability to predict TSV reliability still in its infancy
o Hampered by little published test data (primarily simulation)
o Any prediction must taken into account changes in interfacial material
o Don’t simulate/test nominal; investigate realistic worst-case
o However, there is no need to reinvent the wheel
o A significant amount of relevant material, especially in regards to interfacial reliability can be found in studies on fiber-reinforced ceramic composites
TSV Failures (Summary)
© 2004 - 2007© 2004 - 2010© 2004 – 2010
Manufacturability and
Reliability of 0.3mm Pitch Chip
Scale Packages and QFNs
© 2004 - 2007© 2004 - 2010 46
Reliability and Next Generation Technologies
o One of the most common drivers for failure is inappropriate adoption of new technologieso The path from consumer (high volume, short lifetime) to high rel is not always clear
o Obtaining relevant information can be difficulto Information is often segmented
o Focus on opportunity, not risks
o Can be especially true for component packagingo Fine pitch CSP (Chip Scale Packages)
© 2004 - 2007© 2004 - 2010 47
Solder Wearout
o Design change: More silicon, less plastic
o Increases mismatch in coefficient of thermal expansion (CTE)
BOARD LEVEL ASSEMBLY AND RELIABILITY
CONSIDERATIONS FOR LNCSP TYPE
PACKAGES, Ahmer Syed and WonJoon Kang,
Amkor Technology.
© 2004 - 2007© 2004 - 2010 48
Solder Wearout (cont.)
o Hotter devices
o Increases change in temperature (∆T)
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
0 50 100 150 200
Change in Temperature (oC)
Ch
ara
cte
risti
c L
ife (
Cyc
les t
o F
ail
ure
)
tf = ∆∆∆∆Tn
n = 2 (SnPb)
n = 2.3 (SnNiCu)
n = 2.7 (SnAgCu)
© 2004 - 2007© 2004 - 2010 49
.3 mm CSP: Why Not?
o .3 mm CSP is a ‘next generation’ technology for non-consumer electronic OEMs due to concerns with
o Manufacturability
o Compatibility with other OEM processes
o Reliability
o Acceptance of this package, especially in long-life, severe environment, high-reliability applications, is currently limited as a result
© 2004 - 2007© 2004 - 2010
Chip Scale Packages
Wafer Level CSP
Lead Frame Chip Scale Package
© 2004 - 2007© 2004 - 2010
o Board Fabricatorso A first step in adapting to .3 mm pitch(12 mil)
o 2 mil traces and spaces
o Why? Bond pad will be .15mm
o 2 mil trace is only size that will fit between
o Most likely use via in pad
o Copper Thicknesso Board fabricators introducing a reduction in copper foil thickness to
work with these smaller components
o Going down to .25 ounce copper – good for lateral etching, trace width control, uniform trace width.
ISSUE IS REDUCED RELIABILITY DUE TO POTENTIAL FOR TRACE CRACKING
Design and Fab Thoughts?
© 2004 - 2007© 2004 - 2010 52
Fine Pitch CSP Manufacturability: Bond Pads
o Non Solder Mask Defined Pads Preferred (NSMD)o Copper etch process has tighter process control than solder mask processo Makes for more consistent, strong solder joints since solder bonds to both tops and sides of
pads
o Use solder mask defined pads (SMD) with careo Can be used to avoid bridging between pads, especially between thermal and signal
pads. o Pads can significantly grow in size based on PCB manufacturer capabilities
NSMD
Images courtesy of Screaming Circuits
© 2004 - 2007© 2004 - 2010
o Continued reduction in apertures and bond pad dimensions are driving toward Types 5 or 6 shown in the chart to facilitate .3mm pitch components
o While changes in the solder paste is expected – this move toward “nanosolder” - the increasing ratio of surface area to volume in these small particle systems may start to influence coalescence behavior and storage times as well.
Solder Paste
© 2004 - 2007© 2004 - 2010
o The actual minimum area ratio tends to change for different solder paste types. o For standard Type 3, the number tends to be 0.66, while pastes with
even smaller powder have minimum area ratios closer to 0.5. Regardless, for a 0.15 mm (6 mil) bond pad, maintaining either of these ratios would require stencil thicknesses of less than 4 mil.
o These stencil requirements can be problematic for larger or non-fine pitch components, which can potentially experience solder starvation or solder bridging or solder balls (if the stencil aperture is widened to introduce more paste on pad).
o All of these challenges are, of course, before attempting to select the type of stencil technology (electroformed or laser cut) or the process parameters (pressure, speed, etc.).
Stencils
© 2004 - 2007© 2004 - 2010 55
Manufacturability: Stencil Design
Datasheet says solder paste coverage should be 40-80%
Drawing supplied in same datasheet is for 26% coverage
© 2004 - 2007© 2004 - 2010
o As usual, reliability is often the last issue to be considered.
o While minimum modeling or testing has been performed, the relatively small volume of solder and the non-uniformity of the interconnect geometry (0.15 mm bond pads on board and 0.075 mm bond pads on package) could create unique scenarios in regards to solder joint response to the application of stresses.
o This is in addition to the increasing introduction of mixed mode (shear and tensile stresses) that are greatly accelerating creep and fatigue damage accumulation.
Reliability
© 2004 - 2007© 2004 - 2010
o While the move to 0.3 mm pitch CSPs will be challenging, there is significant opportunity for leveraging the experiences of other portions of the supply chain.
o Examples include wafer-level bumping, which has been stencil printing 0.15mm pitch solder bumps for some time period,
o BGA substrates, which has been using 2 mil width and spacing on advanced packages, and
o 01005s, which have bond pads only 7 mil wide.
Success will be ensured through adopting the information gained from these other processes, being aware of the potential gaps in this knowledge, and implementing industry best practices and physics of failure to understand margins and interconnect robustness.
.3mm CSP Reliability Conclusions
© 2004 - 2007© 2004 - 2010 58
LFCSP Manufacturability: Bond Pads
o Can lose solder volume and standoff height through vias in thermal padso May need to tent, plug, or cap vias to keep sufficient paste volumeo Reduced standoff height reduces cleanability and pathways for flux outgassing
o Increased potential for contamination related failureso Tenting and plugging vias is often not well controlled and can lead to placement
and chemical entrapment issues o Exercise care with devices placed on opposing side of LNCSPo Can create placement issues if solder “bumps” are created in viaso Can create solder short conditions on the opposing deviceo Capping is a more robust, more expensive process that eliminates these concerns
Images courtesy of Screaming Circuits
Thermal
vias capped
with solder
mask
© 2004 - 2007© 2004 - 2010 59
Bond Pads
o Extend bond pad 0.2 – 0.3 mm beyond package footprint
o May or may not solder to cut edge
o Allows for better visual inspection
o Need X-ray for best results
o Allows for verification of bridging, adequate solder coverage and void percentage
o Cannot detect head in pillow or fractures
o Note: Lack of good criteria for acceptable voiding of the thermal pad. Depends upon thermal needs.
© 2004 - 2007© 2004 - 2010 60
Manufacturability: Reflow & Moisture
o LFCSP solder joints are more susceptible to dimensional changes
o Case Study: Military supplier experienced solder separation under LFCSP
o LFCSP supplier admitted that the package was more susceptible to moisture absorption that initially expectedo Resulted in transient swelling during reflow soldering
o Induced vertical lift, causing solder separation
o Was not popcorningo No evidence of cracking or delamination in component package
© 2004 - 2007© 2004 - 201061
Corrective Actions: Manufacturing
• Verify good MSL (moisture sensitivity level) handling and procedure procedures
• Reflow Profile: Specify and confirm
• Room temperature to preheat: maximum 2-3oC/sec
• Preheat to at least 150oC
• Preheat to maximum temperature: maximum 4-5oC/sec
• Cooling: maximum 2-3oC/sec
• In conflict with profile from J-STD-020C which allows up to 6oC/sec
• Make sure assembly is less than 60oC before any cleaning processes
© 2004 - 2007© 2004 - 2010 62
Manufacturability: LFCSP Joint Inspection
Goal is 2-3 mils of post-reflow solder thickness
© 2004 - 2007© 2004 - 2010 63
Manufacturability: Board Flexure
o Area array devices are known to have board flexure limitationso In circuit testing (ICT), board depanelization, connector insertion, manual assembly operations, shock and vibration, etc. are common causes.
o For SAC attachment, maximum microstrain can be as low as 500 υε
o Use IPC-JEDEC 9701 and 9704 specifications
o .3mm CSPs and LFCSPs have an even lower level of complianceo Limited quantifiable knowledge in this area
o Must be conservative during board build
o IPC is working on a specification similar to BGAs
© 2004 - 2007© 2004 - 2010 64 64
Pad Cratering
o Drivers
o Finer pitch components
o More brittle laminates
o Stiffer solders (SAC vs. SnPb)
o Presence of a large heat sink
o Difficult to detect using standard procedures
o X-ray, dye-n-pry, ball shear, and ball pull
Intel (2006)
© 2004 - 2007© 2004 - 2010 65 65
Solutions to Pad Crateringo Board Redesign
o Solder mask defined vs. non-solder mask defined
o Limitations on board flexureo 750 to 500 microstrain, Component dependent
o More compliant soldero SAC305 is relatively rigid, SAC105 and SNC are possible alternatives
o New acceptance criteria for laminate materialso Intel-led industry efforto Attempting to characterize laminate material using high-speed ball pull and shear testing, Results inconclusive to-date
o Alternative approacho Require reporting of fracture toughness and elastic modulus
© 2004 - 2007© 2004 - 2010 66
Reliability: Thermal Cycling
o Order of magnitude reduction in time to
failure from QFP
o 3X reduction from BGA
o Driven by die / package ratio
o 40% die; tf = 8K cycles (-40 / 125C)
o 75% die; tf = 800 cycles (-40 / 125C)
o Driven by size and I/O#
o 44 I/O; tf = 1500 cycles (-40 / 125C)
o 56 I/O; tf = 1000 cycles (-40 / 125C)
o Very dependent upon solder bond with
thermal pad
BGA: 3,000 to 8,000
LFCSP: 1,000 to 3,000
QFP: >10,000
© 2004 - 2007© 2004 - 2010 67 67
Electro-Chemical Migration: Details
o Insidious failure mechanism
o Self-healing: leads to large number of no-trouble-found (NTF)
o Can occur at nominal voltages (5 V) and room conditions (25C, 60%RH)
o Due to the presence of contaminants on the surface of the board
o Strongest drivers are halides (chlorides and bromides)
o Weak organic acids (WOAs) and polyglycols can also lead to drops in the surface insulation resistance
o Primarily controlled through controls on cleanliness
o Minimal differentiation between existing Pb-free solders, SAC and SnCu, and SnPb
o Other Pb-free alloys may be more susceptible (e.g., SnZn)
elapsed time 12 sec.
© 2004 - 2007© 2004 - 2010 68
Reliability: Dendritic Growth / Electrochemical Migration
o Large area, multi-I/O and low standoff can trap flux under the LNCSP
o Processes using no-clean flux should be requalified
o Particular configuration could result in weak organic acid concentrations above maximum (150 – 200 ug/in2)
o Aqueous Cleaning processes will likely experience dendritic growth without modifications like:
o Increase in water temperature
o Additions of saponifiers or solvents
o Changes to number and angle of impingement jets
© 2004 - 2007© 2004 - 2010
Cleanliness Controls: Ion Chromatographyo Contamination tends to be controlled through industrial specifications (IPC-
6012, J-STD-001)
o Primarily based on original military specification
o 10 µg/in2 of NaCl ‘equivalent’
o Calculated to result in 2 megaohm surface insulation resistance (SIR)
o Not necessarily best practice
o Best practice is contamination controlled through ion chromatography (IC) testing
o IPC-TM-650, Method 2.3.28A
*Based on R/O/I testing
PaulsGeneral Electric
NDCEE DoD* IPC* ACI
Chloride (µµµµg/in2) 2 3.5 4.5 6.1 6.1 10
Bromide (µµµµg/in2) 20 10 15 7.8 7.8 15
© 2004 - 2007© 2004 - 2010© 2004 – 2010
Physics-of-Failure Approach to
Copper Wire Bonding
© 2004 - 2007© 2004 - 2010
o Initial marketing activities for fine pitched applications initiated in mid-2000’s
o Replacement of gold wire bonding initiated in 2007-2008 due to gold pricing, but stunted due to economic recession
o Rapid implementation and replacement of gold wire bonding starting in 2009
Copper Wire Bonding – Market Status
Current state of suppliers
© 2004 - 2007© 2004 - 2010
o The major issues in regards to copper wire bonding are bonding force (and risk of silicon damage) and reduced nobility (greater risk of corrosion)
o In response, some suppliers have been forced too Redesign the bond pad and underlying structure
o Modified the molding compound (lower pH, reduced halogen content)
o Still unresolvedo Preferred bond pad material (Al and Pd)
o The need for Pd coating over copper wire bond
o Type of forming gas used in process (N2 or N2H2)
Design Changes in Response to Copper Wire Bonding
© 2004 - 2007© 2004 - 2010
o Palladium (Pd) coating creates galvanic couple with copper
o Studies have demonstrated thinning or loss of Pd coating during bonding
o Uncertain if JEDEC test with acceleration factor based on Peck’s equation (based on aluminum/gold galvanic couple) is still valid
o Push out of aluminum pad
o Could result in subsurface cracking (metal migration?)
o Uncertain if existing JEDECtemp cycling test is sufficient todrive crack growth
Major concerns identified by DfR
© 2004 - 2007© 2004 - 2010
o Copper-aluminum forms intermetallics at a much slower rate
o Most common activation energy of 1.26 – 1.47 eV
o Micron reported 0.63 eV
o Molding compound has little effect
Other Systems (Cu-Al)
HJ Kim, IEEE CPT, 2003
L Levine, Update onHigh Volume Copper Ball Bonding
L. England, ECTC, 2007
C. Breach, The Great Debate: Copper vs. Gold Ball Bonding
© 2004 - 2007© 2004 - 2010
o Cu-Al shows improved performance over Au-Al
o Not to the extent expected based on intermetallic growth
o Different failure mode (gradual vs. sudden)
Other Systems (Cu-Al)(cont.)
Cu-Al
Au-Al
© 2004 - 2007© 2004 - 2010
o Different intermetallics form at different temperatureso Can a 150C/200C test be extrapolated to 85C?
o Some indications that oxidation of the wedge bond may be a critical weak pointo Additional testing and modeling may be necessary
Cu-Al and Elevated Temperature – Concerns
© 2004 - 2007© 2004 - 2010
o Copper is not as noble as goldo Noble coatings (palladium) can
come off during bondingo Palladium (Pd) coating can also
create galvanic couple with copper
o Studies have shown early failures during temp/humidity testingo Some dependency on molding
compound (need lower pH, lower halogen content)
o Uncertain if JEDEC test with acceleration factor based on Peck’s equation (based on aluminum/gold) is still valid
Copper Wire Bond and Temperature/Humidity
H. Clauberg, Chip Scale Review, Dec 2010
Halogen-Free Molding Compounds
© 2004 - 2007© 2004 - 2010
o Power module industry believes copper wire is more robust than aluminumo Changes being implemented for electric drivetrain
o Part of improvement is believed to be due to reduced temperature variation from improved thermal conductivity
o Part of improvement could be due to recrystallizationo Can result in self-healing
o Part of improvement could be more robust fatigue behavior
Copper Wire and Temperature Cycling
D. Siepe, CIPS 2010
N. Tanabe, Journal de Physique IV, 1995
© 2004 - 2007© 2004 - 2010
o Copper clearly superior
Copper vs. Gold – Temperature Cycling
N. Tanabe, Journal de Physique IV, 1995
G. Pasquale, J. Microelectromech Sys.,, 2011
© 2004 - 2007© 2004 - 2010
o Copper clearly superior
Aluminum vs. Copper – Temperature Cycling
10
100
106 108107 109
N. Tanabe, Journal de Physique IV, 1995J. Bielen, EuroSime, 2006
