Device reliability challenges for modern semiconductor circuit … · 2020. 6. 9. · the Creative...

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Adv. Radio Sci., 7, 201–211, 2009 www.adv-radio-sci.net/7/201/2009/ © Author(s) 2009. This work is distributed under the Creative Commons Attribution 3.0 License. Advances in Radio Science Device reliability challenges for modern semiconductor circuit design – a review C. Schl ¨ under Infineon Technologies AG, Corporate Reliability Methodology, Otto-Hahn-Ring 6, 81739 Munich, Germany Abstract. Product development based on highly integrated semiconductor circuits faces various challenges. To ensure the function of circuits the electrical parameters of every de- vice must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1). Degradation mechanisms like Negative Bias Temperature Instability (NBTI) or Hot Carrier Injection (HCI) lead to parameter drifts during operation adding on top of the process variations. The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced tech- nologies. The assignment of tasks to ensure the product life- time has to be changed for the future. Up to now technology development has the main responsibility to adjust the tech- nology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology develop- ment only. Device degradation becomes a collective chal- lenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliabil- ity will be one of the key requirements for modern product designs. An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device param- eter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR) will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be Correspondence to: C. Schl¨ under ([email protected]) Process variation / mismatch 230 260 290 320 350 380 410 440 470 V th Window for correct circuit function Degradation Degradation Process variation / mismatch Process variation / mismatch 230 260 290 320 350 380 410 440 470 V th Window for correct circuit function Window for correct circuit function Degradation Degradation Degradation Degradation Fig. 1: Specific window for correct circuit function Fig. 1. Specific window for correct circuit function. In worst case process variations and parameter degradation add up. described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed. 1 Device degradation Negative Bias Temperature Instability (NBTI) and Hot Car- rier Injection (HCI, also called “hot carrier stress” HCS) are nowadays the most critical device degradation mecha- nisms and became a limiting factor in scaling of modern CMOS technologies (Schl ¨ under, 2005, 2007; Martin, 2009). Figure 2 shows the chain of causation of circuit IC failures based on device degradation. The circuit function determines the operation points of every involved device. The opera- tion of the transistors leading to device stress depending on the operation point and other factor like operation tempera- ture, device geometry etc. Damage mechanisms occur lead- ing to changes mainly of the gate oxide and adjoining parts of the transistors. These damages lead in turn to a change of the electrical behavior of the devices, which is described by electrical parameters. If this electrical parameter degradation Published by Copernicus Publications on behalf of the URSI Landesausschuss in der Bundesrepublik Deutschland e.V.

Transcript of Device reliability challenges for modern semiconductor circuit … · 2020. 6. 9. · the Creative...

Page 1: Device reliability challenges for modern semiconductor circuit … · 2020. 6. 9. · the Creative Commons Attribution 3.0 License. Advances in Radio Science Device reliability challenges

Adv. Radio Sci., 7, 201–211, 2009www.adv-radio-sci.net/7/201/2009/© Author(s) 2009. This work is distributed underthe Creative Commons Attribution 3.0 License.

Advances inRadio Science

Device reliability challenges for modern semiconductor circuitdesign – a review

C. Schlunder

Infineon Technologies AG, Corporate Reliability Methodology, Otto-Hahn-Ring 6, 81739 Munich, Germany

Abstract. Product development based on highly integratedsemiconductor circuits faces various challenges. To ensurethe function of circuits the electrical parameters of every de-vice must be in a specific window. This window is restrictedby competing mechanisms like process variations and devicedegradation (Fig. 1). Degradation mechanisms like NegativeBias Temperature Instability (NBTI) or Hot Carrier Injection(HCI) lead to parameter drifts during operation adding on topof the process variations.

The safety margin between real lifetime of MOSFETs andproduct lifetime requirements decreases at advanced tech-nologies. The assignment of tasks to ensure the product life-time has to be changed for the future. Up to now technologydevelopment has the main responsibility to adjust the tech-nology processes to achieve the required lifetime. In future,reliability can no longer be the task of technology develop-ment only. Device degradation becomes a collective chal-lenge for semiconductor technologist, reliability experts andcircuit designers. Reliability issues have to be considered indesign as well to achieve reliable and competitive products.For this work, designers require support by smart softwaretools with built-in reliability know how. Design for reliabil-ity will be one of the key requirements for modern productdesigns.

An overview will be given of the physical device damagemechanisms, the operation conditions within circuits leadingto stress and the impact of the corresponding device param-eter degradation on the function of the circuit. Based on thisunderstanding various approaches for Design for Reliability(DfR) will be described. The function of aging simulatorswill be explained and the flow of circuit-simulation will be

Correspondence to:C. Schlunder([email protected])

Device reliability challenges for modern semiconductor circuit design A Review

Christian Schlünder

Infineon Technologies AG, Corporate Reliability Methodology, Otto-Hahn-Ring 6, D-81739 Munich, Germany +49 89 234 52934; fax: +49 89 234 9557544; e-mail: [email protected]

ABSTRACT Product development based on highly integrated semiconductor

circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1). Degradation mechanisms like Negative Bias Temperature Instability (NBTI) or Hot Carrier Injection (HCI) lead to parameter drifts during operation adding on top of the process variations.

The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs.

An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR) will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.

DEVICE DEGRADATION Negative Bias Temperature Instability (NBTI) and Hot Carrier

Injection (HCI, also called ‘hot carrier stress’ HCS) are nowadays the most critical device degradation mechanisms and became a limiting factor in scaling of modern CMOS technologies [1-3].

Process variation / mismatch

230 260 290 320 350 380 410 440 470Vth

Window for correct circuit function

Degradation DegradationProcess variation / mismatchProcess variation / mismatch

230 260 290 320 350 380 410 440 470Vth

Window for correct circuit functionWindow for correct circuit function

Degradation DegradationDegradation Degradation

Fig. 1: Specific window for correct circuit function

Device Stress

conditions

Electrical parameter

degradation

Damage mechanisms

Application failure

Circuit function

chain of causation

Fig. 2: Chain of causation of IC-failures

Fig. 2 shows the chain of causation of circuit IC failures based on device degradation. The circuit function determines the operation points of every involved device. The operation of the transistors leading to device stress depending on the operation point and other factor like operation temperature, device geometry etc. Damage mechanisms occur leading to changes mainly of the gate oxide and adjoining parts of the transistors. These damages lead in turn to a change of the electrical behavior of the devices, which is described by electrical parameters. If this electrical parameter degradation leaves a circuit specific window, the circuit fails and finally the application malfunctions.

Beside the two most important degradation mechanisms NBTI and HCI, which cause transistor parameter shifts during IC operation, plasma induced damage (PID) can also contribute to MOS transistor parameter drifts. PID is a degradation of MOS devices, which occurs during processing and in fact, it can accelerate the NBTI and HCI degradation during circuit operation. PID is not discussed in this review, details can be found elsewhere [3]. Generally, in a semiconductor manufacturing environment variations in processing conditions influence not only the parameter mismatch but also vary reliability degradation. In order to keep track of the reliability variations, very fast reliability measurements are performed on a continuous basis on productive wafers [4].

HOT CARRIER STRESS Hot Carrier Stress describes a degradation of the electrical

parameters of MOSFETs under a dynamic stress mode [5-10]. The lateral electrical field between source and drain of a current driving transistor can lead to high energetic carriers. A part of these ‘hot’ carriers cause impact ionization (electron hole pair generation). One carrier of the pair drains in the substrate, the other one can damage the gate oxide and adjacent spacer oxides. The schematic in Fig. 3 illustrates the stress condition for HCS. A gate-source potential drives

Fig. 1. Specific window for correct circuit function. In worst caseprocess variations and parameter degradation add up.

described. Furthermore, the difference between full customand semi custom design and therefore, the different requiredapproaches will be discussed.

1 Device degradation

Negative Bias Temperature Instability (NBTI) and Hot Car-rier Injection (HCI, also called “hot carrier stress”→ HCS)are nowadays the most critical device degradation mecha-nisms and became a limiting factor in scaling of modernCMOS technologies (Schlunder, 2005, 2007; Martin, 2009).

Figure 2 shows the chain of causation of circuit IC failuresbased on device degradation. The circuit function determinesthe operation points of every involved device. The opera-tion of the transistors leading to device stress depending onthe operation point and other factor like operation tempera-ture, device geometry etc. Damage mechanisms occur lead-ing to changes mainly of the gate oxide and adjoining partsof the transistors. These damages lead in turn to a change ofthe electrical behavior of the devices, which is described byelectrical parameters. If this electrical parameter degradation

Published by Copernicus Publications on behalf of the URSI Landesausschuss in der Bundesrepublik Deutschland e.V.

Page 2: Device reliability challenges for modern semiconductor circuit … · 2020. 6. 9. · the Creative Commons Attribution 3.0 License. Advances in Radio Science Device reliability challenges

202 C. Schlunder: Device reliability challenges for modern semiconductor circuit design

Device reliability challenges for modern semiconductor circuit design A Review

Christian Schlünder

Infineon Technologies AG, Corporate Reliability Methodology, Otto-Hahn-Ring 6, D-81739 Munich, Germany +49 89 234 52934; fax: +49 89 234 9557544; e-mail: [email protected]

ABSTRACT Product development based on highly integrated semiconductor

circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1). Degradation mechanisms like Negative Bias Temperature Instability (NBTI) or Hot Carrier Injection (HCI) lead to parameter drifts during operation adding on top of the process variations.

The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs.

An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR) will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.

DEVICE DEGRADATION Negative Bias Temperature Instability (NBTI) and Hot Carrier

Injection (HCI, also called ‘hot carrier stress’ HCS) are nowadays the most critical device degradation mechanisms and became a limiting factor in scaling of modern CMOS technologies [1-3].

Process variation / mismatch

230 260 290 320 350 380 410 440 470Vth

Window for correct circuit function

Degradation DegradationProcess variation / mismatchProcess variation / mismatch

230 260 290 320 350 380 410 440 470Vth

Window for correct circuit functionWindow for correct circuit function

Degradation DegradationDegradation Degradation

Fig. 1: Specific window for correct circuit function

Device Stress

conditions

Electrical parameter

degradation

Damage mechanisms

Application failure

Circuit function

chain of causation

Fig. 2: Chain of causation of IC-failures

Fig. 2 shows the chain of causation of circuit IC failures based on device degradation. The circuit function determines the operation points of every involved device. The operation of the transistors leading to device stress depending on the operation point and other factor like operation temperature, device geometry etc. Damage mechanisms occur leading to changes mainly of the gate oxide and adjoining parts of the transistors. These damages lead in turn to a change of the electrical behavior of the devices, which is described by electrical parameters. If this electrical parameter degradation leaves a circuit specific window, the circuit fails and finally the application malfunctions.

Beside the two most important degradation mechanisms NBTI and HCI, which cause transistor parameter shifts during IC operation, plasma induced damage (PID) can also contribute to MOS transistor parameter drifts. PID is a degradation of MOS devices, which occurs during processing and in fact, it can accelerate the NBTI and HCI degradation during circuit operation. PID is not discussed in this review, details can be found elsewhere [3]. Generally, in a semiconductor manufacturing environment variations in processing conditions influence not only the parameter mismatch but also vary reliability degradation. In order to keep track of the reliability variations, very fast reliability measurements are performed on a continuous basis on productive wafers [4].

HOT CARRIER STRESS Hot Carrier Stress describes a degradation of the electrical

parameters of MOSFETs under a dynamic stress mode [5-10]. The lateral electrical field between source and drain of a current driving transistor can lead to high energetic carriers. A part of these ‘hot’ carriers cause impact ionization (electron hole pair generation). One carrier of the pair drains in the substrate, the other one can damage the gate oxide and adjacent spacer oxides. The schematic in Fig. 3 illustrates the stress condition for HCS. A gate-source potential drives

Fig. 2. Chain of causation of IC-failures.

leaves a circuit specific window, the circuit fails and finallythe application malfunctions.

Beside the two most important degradation mechanismsNBTI and HCI, which cause transistor parameter shifts dur-ing IC operation, plasma induced damage (PID) can alsocontribute to MOS transistor parameter drifts. PID is a degra-dation of MOS devices, which occurs during processing andin fact, it can accelerate the NBTI and HCI degradation dur-ing circuit operation. PID is not discussed in this review,details can be found elsewhere (Martin, 2009). Generally,in a semiconductor manufacturing environment variations inprocessing conditions influence not only the parameter mis-match but also vary reliability degradation. In order to keeptrack of the reliability variations, very fast reliability mea-surements are performed on a continuous basis on productivewafers (Martin and Vollertsen, 2004).

2 Hot Carrier Stress

Hot Carrier Stress describes a degradation of the electricalparameters of MOSFETs under a dynamic stress mode (Huet al., 1985; LaRosa et al., 1997; Thewes et al., 1999; Chenet al., 1999; Lu et al., 2004; Bravaix et al., 2009). The lateralelectrical field between source and drain of a current driv-ing transistor can lead to high energetic carriers. A part ofthese “hot” carriers cause impact ionization (electron holepair generation). One carrier of the pair drains in the sub-strate, the other one can damage the gate oxide and adjacentspacer oxides. The schematic in Fig. 3 illustrates the stresscondition for HCS. A gate-source potential drives the transis-tor into strong inversion, and the drain-source-voltage formsthe lateral field. In a classic model lucky electrons can col-lect enough energy within the drift zone beyond the pinchoff point to create impact ionization. The injected carrierscan damage gate- and spacer-oxide at the drain side of thetransistor. Therefore the device is damaged inhomogenously,the device is no longer symmetrical. Beside the drain-source

the transistor into strong inversion, and the drain-source-voltage forms the lateral field. In a classic model lucky electrons can collect enough energy within the drift zone beyond the pinch off point to create impact ionization. The injected carriers can damage gate- and spacer-oxide at the drain side of the transistor. Therefore the device is damaged inhomogenously, the device is no longer symmetrical. Beside the drain-source voltage also the gate-source voltage has an effect on the degradation. VGS affects the amount of carriers within the channel and also the energy which carriers can collect. These effects lead to a specific VGS for maximal damage.

DD

SS

GG

VV ggss

VV ddssDD

SS

GG

VV ggss

VV ddss

Fig. 3: Schematic Hot carrier stress condition

At lower VGS the amount of carriers within the inversion layer is

decreased. For higher gate-voltage the drift zone will be reduced and correspondingly the carriers can collect less energy. The worst case gate-source voltage for a given drain-source voltage can be determined by set of a measurements. The gate current of p-MOS devices is a measure for the amount electron hole pair generation under hot carrier stress conditions. For n-channel device the injected gate current is hard to measure (especially for thicker oxides) since the injected electrons slow down in the electric field between gate and drain node. The substrate current is measured alternatively. While the measured current highlights only the quantity of potentially injected carrier and not their energy, the worst case condition for HCS damages is at slightly lower gate voltages. Since the maximum of the substrate current curve is reasonably flat, the error is negligible.

Furthermore, HCS shows temperature dependence. At lower temperature the mean free path for the carrier is longer. They can collect higher energies. Accordingly, the worst case for HCS is at the lowest (product-) temperature. The injected carriers impact the electrical parameters of stressed devices, especially the threshold voltage and the carrier mobility (gm). For n-MOSFETs the HCS degradation leads to an increase of the threshold voltage of and to a reduction of the carrier mobility. The drive current capability of n-MOSFETs degrades.

For the degradation of pMOSFETs we have to consider the technology node, especially the gate length and the work function formed by the material for the gate electrode. A classic buried channel p-MOS device degrades in the opposite direction to n-MOS devices. Electron trapping leads to lower threshold voltages, increased drain current and higher off-currents. For modern technologies with boron doped polysilicon gates for surface channel pMOSFETs (dual workfunction) the p-channel devices show a contrary behavior. In this case the damage is dominated by hole trapping. In general the degradation is comparable to n-channel transistors. The threshold voltage increases and the drain current decreases. At modern dual work function technologies HCS leads to a reduction of drive current capability of the transistor independently of channel type.

Also the worst case condition for HCS differs with different technology nodes. In modern technologies (below quarter micron) the

mean free path plays no longer the dominant part for the p-MOS degradation. The energy of the hot carriers and therefore, the degradation has its maximum at higher temperatures. The worst case operation point shifts to VDS = VGS. For the latest technology nodes (below 65nm node), the worst case condition is at VDS = VGS and higher temperature even for n-channel devices. For a lifetime assessment it has to be considered that the operation point VDS = VGS = VDD is very untypical within circuit function. Only the charge/discharge of very large capacitances can lead to operation points close to VDS = VGS = VDD.

NEGATIVE BIAS TEMPERATURE INSTABILITY NBTI for pMOSFETs describes the parameter degradation under a

static stress mode at elevated temperature [11-13, 6]. A high gate-source voltage drives the device in inversion. The carrier channel is formed, but since the drain-source voltage equals zero, no current flows in the channel region. Fig. 4 illustrates the schematic for the NBTI stress condition. Due to the missing lateral field in contrast to HCS, a homogenous damage of the whole active region can be obtained. Therefore, NBTI shows only weak dependence on the geometry, based on oxide edge effects.

DD

SS

GG

VVggss

Fig. 4: Schematic NBTI stress condition

The high electrical field across the gate oxide in combination with

an elevated temperature leads to an electrochemical reaction in the region of the interface between silicon and gate oxide. Fig. 5 shows a schematic of this interface. Due to slightly different lattice structures of monocrystaline silicion and the amorphous oxide, an interface region is formed during and after gate oxide processing, which consists of only a few atomic layers and many dangling blonds. The open dangling bonds act as interface states. They can catch (channel-) carriers, trap them for a certain time and emit them back into channel. Filled interface states shift the threshold voltage and can reduce the channel carrier mobility.

During high temperature steps after gate oxide process these dangling bonds were passivated typically by hydrogen. Additional anneals under hydrogen atmosphere support this process. Such saturated bonds are no longer electrical active and do not disturb the transistor function. During negative bias temperature stress these passivated bonds break open within an electrochemical reaction.

The bonds ‘dangle’ again and act as interface states. Filled donor type interface states counteract the charge on the gate electrode. For each trapped hole in an interface state one electron of the charge on the gate electrode is missing for controlling the channel. In other words one carrier is missing in the channel. As a result the absolute value of the threshold value increases. Additionally holes can be trapped within the oxide bulk with the same effect.

Fig. 3. Schematic Hot carrier stress condition.

voltage also the gate-source voltage has an effect on thedegradation.VGS affects the amount of carriers within thechannel and also the energy which carriers can collect. Theseeffects lead to a specificVGS for maximal damage.

At lower VGS the amount of carriers within the inversionlayer is decreased. For higher gate-voltage the drift zonewill be reduced and correspondingly the carriers can collectless energy. The worst case gate-source voltage for a givendrain-source voltage can be determined by set of a measure-ments. The gate current of p-MOS devices is a measure forthe amount highlights only the quantity electron hole pairgeneration under hot carrier stress conditions. For n-channeldevice the injected gate current is hard to measure (especiallyfor thicker oxides) since the injected electrons slow down inthe electric field between gate and drain node. The substratecurrent is measured alternatively. While the measured cur-rent highlights only the quantity of potentially injected car-rier and not their energy, the worst case condition for HCSdamages is at slightly lower gate voltages. Since the max-imum of the substrate current curve is reasonably flat, theerror is negligible.

Furthermore, HCS shows temperature dependence. Atlower temperature the mean free path for the carrier is longer.They can collect higher energies. Accordingly, the worst casefor HCS is at the lowest (product-) temperature. The injectedcarriers impact the electrical parameters of stressed devices,especially the threshold voltage and the carrier mobility (gm).For n-MOSFETs the HCS degradation leads to an increase ofthe threshold voltage of and to a reduction of the carrier mo-bility. The drive current capability of n-MOSFETs degrades.

For the degradation of pMOSFETs we have to considerthe technology node, especially the gate length and thework function formed by the material for the gate elec-trode. A classic buried channel p-MOS device degradesin the opposite direction to n-MOS devices. Electron trap-ping leads to lower threshold voltages, increased drain cur-rent and higher off-currents. For modern technologies withboron doped polysilicon gates for surface channel pMOS-FETs (dual workfunction) the p-channel devices show a con-trary behavior. In this case the damage is dominated byhole trapping. In general the degradation is comparable to

Adv. Radio Sci., 7, 201–211, 2009 www.adv-radio-sci.net/7/201/2009/

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C. Schlunder: Device reliability challenges for modern semiconductor circuit design 203

the transistor into strong inversion, and the drain-source-voltage forms the lateral field. In a classic model lucky electrons can collect enough energy within the drift zone beyond the pinch off point to create impact ionization. The injected carriers can damage gate- and spacer-oxide at the drain side of the transistor. Therefore the device is damaged inhomogenously, the device is no longer symmetrical. Beside the drain-source voltage also the gate-source voltage has an effect on the degradation. VGS affects the amount of carriers within the channel and also the energy which carriers can collect. These effects lead to a specific VGS for maximal damage.

DD

SS

GG

VV ggss

VV ddssDD

SS

GG

VV ggss

VV ddss

Fig. 3: Schematic Hot carrier stress condition

At lower VGS the amount of carriers within the inversion layer is

decreased. For higher gate-voltage the drift zone will be reduced and correspondingly the carriers can collect less energy. The worst case gate-source voltage for a given drain-source voltage can be determined by set of a measurements. The gate current of p-MOS devices is a measure for the amount electron hole pair generation under hot carrier stress conditions. For n-channel device the injected gate current is hard to measure (especially for thicker oxides) since the injected electrons slow down in the electric field between gate and drain node. The substrate current is measured alternatively. While the measured current highlights only the quantity of potentially injected carrier and not their energy, the worst case condition for HCS damages is at slightly lower gate voltages. Since the maximum of the substrate current curve is reasonably flat, the error is negligible.

Furthermore, HCS shows temperature dependence. At lower temperature the mean free path for the carrier is longer. They can collect higher energies. Accordingly, the worst case for HCS is at the lowest (product-) temperature. The injected carriers impact the electrical parameters of stressed devices, especially the threshold voltage and the carrier mobility (gm). For n-MOSFETs the HCS degradation leads to an increase of the threshold voltage of and to a reduction of the carrier mobility. The drive current capability of n-MOSFETs degrades.

For the degradation of pMOSFETs we have to consider the technology node, especially the gate length and the work function formed by the material for the gate electrode. A classic buried channel p-MOS device degrades in the opposite direction to n-MOS devices. Electron trapping leads to lower threshold voltages, increased drain current and higher off-currents. For modern technologies with boron doped polysilicon gates for surface channel pMOSFETs (dual workfunction) the p-channel devices show a contrary behavior. In this case the damage is dominated by hole trapping. In general the degradation is comparable to n-channel transistors. The threshold voltage increases and the drain current decreases. At modern dual work function technologies HCS leads to a reduction of drive current capability of the transistor independently of channel type.

Also the worst case condition for HCS differs with different technology nodes. In modern technologies (below quarter micron) the

mean free path plays no longer the dominant part for the p-MOS degradation. The energy of the hot carriers and therefore, the degradation has its maximum at higher temperatures. The worst case operation point shifts to VDS = VGS. For the latest technology nodes (below 65nm node), the worst case condition is at VDS = VGS and higher temperature even for n-channel devices. For a lifetime assessment it has to be considered that the operation point VDS = VGS = VDD is very untypical within circuit function. Only the charge/discharge of very large capacitances can lead to operation points close to VDS = VGS = VDD.

NEGATIVE BIAS TEMPERATURE INSTABILITY NBTI for pMOSFETs describes the parameter degradation under a

static stress mode at elevated temperature [11-13, 6]. A high gate-source voltage drives the device in inversion. The carrier channel is formed, but since the drain-source voltage equals zero, no current flows in the channel region. Fig. 4 illustrates the schematic for the NBTI stress condition. Due to the missing lateral field in contrast to HCS, a homogenous damage of the whole active region can be obtained. Therefore, NBTI shows only weak dependence on the geometry, based on oxide edge effects.

DD

SS

GG

VVggss

Fig. 4: Schematic NBTI stress condition

The high electrical field across the gate oxide in combination with

an elevated temperature leads to an electrochemical reaction in the region of the interface between silicon and gate oxide. Fig. 5 shows a schematic of this interface. Due to slightly different lattice structures of monocrystaline silicion and the amorphous oxide, an interface region is formed during and after gate oxide processing, which consists of only a few atomic layers and many dangling blonds. The open dangling bonds act as interface states. They can catch (channel-) carriers, trap them for a certain time and emit them back into channel. Filled interface states shift the threshold voltage and can reduce the channel carrier mobility.

During high temperature steps after gate oxide process these dangling bonds were passivated typically by hydrogen. Additional anneals under hydrogen atmosphere support this process. Such saturated bonds are no longer electrical active and do not disturb the transistor function. During negative bias temperature stress these passivated bonds break open within an electrochemical reaction.

The bonds ‘dangle’ again and act as interface states. Filled donor type interface states counteract the charge on the gate electrode. For each trapped hole in an interface state one electron of the charge on the gate electrode is missing for controlling the channel. In other words one carrier is missing in the channel. As a result the absolute value of the threshold value increases. Additionally holes can be trapped within the oxide bulk with the same effect.

Fig. 4. Schematic NBTI stress condition.

n-channel transistors. The threshold voltage increases andthe drain current decreases. At modern dual work functiontechnologies HCS leads to a reduction of drive current capa-bility of the transistor independently of channel type.

Also the worst case condition for HCS differs with differ-ent technology nodes. In modern technologies (below quar-ter micron) the mean free path plays no longer the domi-nant part for the p-MOS degradation. The energy of the hotcarriers and therefore, the degradation has its maximum athigher temperatures. The worst case operation point shiftsto VDS=VGS . For the latest technology nodes (below 65 nmnode), the worst case condition is atVDS=VGS and highertemperature even for n-channel devices. For a lifetime as-sessment it has to be considered that the operation pointVDS=VGS=VDD is very untypical within circuit function.Only the charge/discharge of very large capacitances can leadto operation points close toVDS=VGS=VDD.

3 Negative bias temperature instability

NBTI for pMOSFETs describes the parameter degradationunder a static stress mode at elevated temperature (Jeppsonand Svensson, 1977; Schlunder et al., 1999; Krishnan et al.,2003; LaRosa et al., 1997). A high gate-source voltage drivesthe device in inversion. The carrier channel is formed, butsince the drain-source voltage equals zero, no current flowsin the channel region. Figure 4 illustrates the schematic forthe NBTI stress condition. Due to the missing lateral field incontrast to HCS, a homogenous damage of the whole activeregion can be obtained. Therefore, NBTI shows only weakdependence on the geometry, based on oxide edge effects.

The high electrical field across the gate oxide in combi-nation with an elevated temperature leads to an electrochem-ical reaction in the region of the interface between siliconand gate oxide. Figure 5 shows a schematic of this inter-face. Due to slightly different lattice structures of monocrys-taline silicion and the amorphous oxide, an interface regionis formed during and after gate oxide processing, which con-sists of only a few atomic layers and many dangling blonds.The open dangling bonds act as interface states. They can

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oxide imperfection

Fig. 5: Schematic of the interface region of MOSFETs. Slightly different lattice structures leads to dangling bonds satured by hydrogen. Under NBTI stress the bonds break and the dangling bonds act as interface states

Furthermore the charged interface can reduce the carrier mobility. Fig. 6 illustrates a simplified cross-section of a NBTI stressed p-MOS device. Positive oxide charges and filled donor-type interfaces are symbolized with circles and rectangles. NBTI has a pronounced process impact up to the passivation layer. The process for gate oxide growing and the hydrogen inventory of the entire process influence the NBTI behavior. SiON gate oxides show enhanced NBTI, but the nitrogen fraction is necessary as a diffusion barrier in the gate oxide of surface channel p-MOSFETs. The barrier prevents boron penetration from the p+ doped poly-silicon into the channel.

np+p+

+ + + + + + ++ +++++ +

negatives Potenzialnegative potential

np+p+

+ + + + + + ++ +++++ +

negatives Potenzialnegative potential

Fig. 6: Simplified cross-section of a NBTI stressed p-MOS device. Positive oxide charges and filled donor type interface states are symbolized with circles and rectangles. Trapped holes impact the electrical behavior of the device.

The n-channel transistor of standard CMOS-technologies with SiO2

or SiON gate oxide is almost not affected by bias temperature stress. There is no comparable electrochemical reaction between the interface and electron channel. For future CMOS technologies offering transistors with an High-K gate stack also ‘Positive Bias Temperature Instability’ (PBTI) becomes a severe device reliability concern.

NBTI RECOVERY Beside the strong parameter degradation another phenomenon of NBTI challenges reliability assessments. The stress induced parameter degradation recovers very fast after end of stress [14-21]. The parameter values drift back to the values before the stress. This effect has to be considered for correct parameter extraction during stress experiments. The flow-chart on the right hand side describes the problem: Due to delays of the used measurement equipment and time

demands of Vth extraction routines, the device is already recovered at the point-of-time of the characterization. The threshold voltage is already recovered.

In contrast to experimental measurement conditions, transistors within product circuits do not have long recovery times between stress and next operation (determined by clock frequency).

Vth extraction methods have to consider this effect. Several different methods have been introduced in the literature, each with different advantages and draw-backs [19, 20]. A very fast method is introduced in [15] and [17]. The threshold voltage can be extracted directly within 0.5µs after end of stress. It has to be mentioned that this cannot be achieved with today’s available parameter analyzers. We recorded the data with a self-developed measurement card. Fig. 7 shows recovery curves a different stress time. The threshold is measured continuously after end of stress. for 11 decades of time (black symbols). ). A Vth measurement sequence without stress was done for verification (red line).After end of stress the electrical parameter moves backwards very fast to the values before NBTI stress.

0

-5

-10

-15

-20

-25

-30

10-6 10-4 10-2 1 102 104 106

V T @

delay

=1s

after 1s

after 100s

after 10s

VStress= -2.8VT=125°C

V T @

del

ay=1

µs

finalrelaxationcurve

50% of VT-shift"lost" until startof conventionalmeasurement

VT w/o stress

V T-s

hift

( m

V )

stresstime & measuring delay ( s ) Fig. 7: Ultra fast Vth measurement as a function of stress- and recovery time. After 100s stress the degraded threshold voltage recovers by 50% in the timeframe between 1µs and 1s after end of stress

After 100s stress the degraded threshold voltage recovers by 50%

in the timeframe between 1µs and 1s after end of stress (blue symbols). Neglecting the NBTI recovery phenomenon leads to falsified measurement value and inaccurate lifetime estimations. Nowadays NBTI is the most serious device degradation mechanism and a limiting factor for technology development. It is not completely understood and measures like metal gates will lead to higher electric field even at fixed gate oxide thicknesses. With PBTI an additional severe device degradation of n-MOSFETs with Hi-K gate stacks grows up.

End of device stress

Characterization

Delay due to equipment and measurement

routinescriti

cal t

ime!

End of device stress

Characterization

Delay due to equipment and measurement

routines

End of device stress

Characterization

Delay due to equipment and measurement

routines

Delay due to equipment and measurement

routinescriti

cal t

ime!

criti

cal t

ime!

Fig. 5. Schematic of the interface region of MOSFETs. Slightlydifferent lattice structures leads to dangling bonds satured by hy-drogen. Under NBTI stress the bonds break and the dangling bondsact as interface states.

O

O

O

SiOO

O

O

SiO

Si

Si

Si

SiSi

Si

Si Si

Si

Si

Si Si

SiSi

SiSi

SiSi

SiSi

SiSiSiSi

SiSi

SiSi SiSi

SiSi

SiSi

SiSi SiSi

SiSiSiSi

amorphesSiO2

monokristalinesSilizium

Grenzfläche

Si

unterschiedlicheGitterstrukturen

Fehlstelle im Oxid

Interface

mono-crystalline silicon

amorphous silicon oxide

different lattice structures

oxide imperfection

O

O

O

SiOO

O

O

SiO

Si

Si

Si

SiSi

Si

Si Si

Si

Si

Si Si

SiSi

SiSi

SiSi

SiSi

SiSiSiSi

SiSi

SiSi SiSi

SiSi

SiSi

SiSi SiSi

SiSiSiSi

amorphesSiO2

monokristalinesSilizium

Grenzfläche

Si

unterschiedlicheGitterstrukturen

Fehlstelle im Oxid

Interface

mono-crystalline silicon

amorphous silicon oxide

different lattice structures

oxide imperfection

Fig. 5: Schematic of the interface region of MOSFETs. Slightly different lattice structures leads to dangling bonds satured by hydrogen. Under NBTI stress the bonds break and the dangling bonds act as interface states

Furthermore the charged interface can reduce the carrier mobility. Fig. 6 illustrates a simplified cross-section of a NBTI stressed p-MOS device. Positive oxide charges and filled donor-type interfaces are symbolized with circles and rectangles. NBTI has a pronounced process impact up to the passivation layer. The process for gate oxide growing and the hydrogen inventory of the entire process influence the NBTI behavior. SiON gate oxides show enhanced NBTI, but the nitrogen fraction is necessary as a diffusion barrier in the gate oxide of surface channel p-MOSFETs. The barrier prevents boron penetration from the p+ doped poly-silicon into the channel.

np+p+

+ + + + + + ++ +++++ +

negatives Potenzialnegative potential

np+p+

+ + + + + + ++ +++++ +

negatives Potenzialnegative potential

Fig. 6: Simplified cross-section of a NBTI stressed p-MOS device. Positive oxide charges and filled donor type interface states are symbolized with circles and rectangles. Trapped holes impact the electrical behavior of the device.

The n-channel transistor of standard CMOS-technologies with SiO2

or SiON gate oxide is almost not affected by bias temperature stress. There is no comparable electrochemical reaction between the interface and electron channel. For future CMOS technologies offering transistors with an High-K gate stack also ‘Positive Bias Temperature Instability’ (PBTI) becomes a severe device reliability concern.

NBTI RECOVERY Beside the strong parameter degradation another phenomenon of NBTI challenges reliability assessments. The stress induced parameter degradation recovers very fast after end of stress [14-21]. The parameter values drift back to the values before the stress. This effect has to be considered for correct parameter extraction during stress experiments. The flow-chart on the right hand side describes the problem: Due to delays of the used measurement equipment and time

demands of Vth extraction routines, the device is already recovered at the point-of-time of the characterization. The threshold voltage is already recovered.

In contrast to experimental measurement conditions, transistors within product circuits do not have long recovery times between stress and next operation (determined by clock frequency).

Vth extraction methods have to consider this effect. Several different methods have been introduced in the literature, each with different advantages and draw-backs [19, 20]. A very fast method is introduced in [15] and [17]. The threshold voltage can be extracted directly within 0.5µs after end of stress. It has to be mentioned that this cannot be achieved with today’s available parameter analyzers. We recorded the data with a self-developed measurement card. Fig. 7 shows recovery curves a different stress time. The threshold is measured continuously after end of stress. for 11 decades of time (black symbols). ). A Vth measurement sequence without stress was done for verification (red line).After end of stress the electrical parameter moves backwards very fast to the values before NBTI stress.

0

-5

-10

-15

-20

-25

-30

10-6 10-4 10-2 1 102 104 106

V T @

delay

=1s

after 1s

after 100s

after 10s

VStress= -2.8VT=125°C

V T @

del

ay=1

µs

finalrelaxationcurve

50% of VT-shift"lost" until startof conventionalmeasurement

VT w/o stress

V T-s

hift

( m

V )

stresstime & measuring delay ( s ) Fig. 7: Ultra fast Vth measurement as a function of stress- and recovery time. After 100s stress the degraded threshold voltage recovers by 50% in the timeframe between 1µs and 1s after end of stress

After 100s stress the degraded threshold voltage recovers by 50%

in the timeframe between 1µs and 1s after end of stress (blue symbols). Neglecting the NBTI recovery phenomenon leads to falsified measurement value and inaccurate lifetime estimations. Nowadays NBTI is the most serious device degradation mechanism and a limiting factor for technology development. It is not completely understood and measures like metal gates will lead to higher electric field even at fixed gate oxide thicknesses. With PBTI an additional severe device degradation of n-MOSFETs with Hi-K gate stacks grows up.

End of device stress

Characterization

Delay due to equipment and measurement

routinescriti

cal t

ime!

End of device stress

Characterization

Delay due to equipment and measurement

routines

End of device stress

Characterization

Delay due to equipment and measurement

routines

Delay due to equipment and measurement

routinescriti

cal t

ime!

criti

cal t

ime!

Fig. 6. Simplified cross-section of a NBTI stressed p-MOS device.Positive oxide charges and filled donor type interface states are sym-bolized with circles and rectangles. Trapped holes impact the elec-trical behavior of the device.

catch (channel-) carriers, trap them for a certain time andemit them back into channel. Filled interface states shift thethreshold voltage and can reduce the channel carrier mobil-ity.

During high temperature steps after gate oxide processthese dangling bonds were passivated typically by hydrogen.Additional anneals under hydrogen atmosphere support thisprocess. Such saturated bonds are no longer electrical activeand do not disturb the transistor function. During negativebias temperature stress these passivated bonds break openwithin an electrochemical reaction.

The bonds “dangle” again and act as interface states.Filled donor type interface states counteract the charge onthe gate electrode. For each trapped hole in an interface stateone electron of the charge on the gate electrode is missing forcontrolling the channel. In other words one carrier is missingin the channel. As a result the absolute value of the thresholdvalue increases. Additionally holes can be trapped within theoxide bulk with the same effect.

Furthermore the charged interface can reduce the carriermobility. Figure 6 illustrates a simplified cross-section of aNBTI stressed p-MOS device. Positive oxide charges andfilled donor-type interfaces are symbolized with circles and

www.adv-radio-sci.net/7/201/2009/ Adv. Radio Sci., 7, 201–211, 2009

Page 4: Device reliability challenges for modern semiconductor circuit … · 2020. 6. 9. · the Creative Commons Attribution 3.0 License. Advances in Radio Science Device reliability challenges

204 C. Schlunder: Device reliability challenges for modern semiconductor circuit design

O

O

O

SiOO

O

O

SiO

Si

Si

Si

SiSi

Si

Si Si

Si

Si

Si Si

SiSi

SiSi

SiSi

SiSi

SiSiSiSi

SiSi

SiSi SiSi

SiSi

SiSi

SiSi SiSi

SiSiSiSi

amorphesSiO2

monokristalinesSilizium

Grenzfläche

Si

unterschiedlicheGitterstrukturen

Fehlstelle im Oxid

Interface

mono-crystalline silicon

amorphous silicon oxide

different lattice structures

oxide imperfection

O

O

O

SiOO

O

O

SiO

Si

Si

Si

SiSi

Si

Si Si

Si

Si

Si Si

SiSi

SiSi

SiSi

SiSi

SiSiSiSi

SiSi

SiSi SiSi

SiSi

SiSi

SiSi SiSi

SiSiSiSi

amorphesSiO2

monokristalinesSilizium

Grenzfläche

Si

unterschiedlicheGitterstrukturen

Fehlstelle im Oxid

Interface

mono-crystalline silicon

amorphous silicon oxide

different lattice structures

oxide imperfection

Fig. 5: Schematic of the interface region of MOSFETs. Slightly different lattice structures leads to dangling bonds satured by hydrogen. Under NBTI stress the bonds break and the dangling bonds act as interface states

Furthermore the charged interface can reduce the carrier mobility. Fig. 6 illustrates a simplified cross-section of a NBTI stressed p-MOS device. Positive oxide charges and filled donor-type interfaces are symbolized with circles and rectangles. NBTI has a pronounced process impact up to the passivation layer. The process for gate oxide growing and the hydrogen inventory of the entire process influence the NBTI behavior. SiON gate oxides show enhanced NBTI, but the nitrogen fraction is necessary as a diffusion barrier in the gate oxide of surface channel p-MOSFETs. The barrier prevents boron penetration from the p+ doped poly-silicon into the channel.

np+p+

+ + + + + + ++ +++++ +

negatives Potenzialnegative potential

np+p+

+ + + + + + ++ +++++ +

negatives Potenzialnegative potential

Fig. 6: Simplified cross-section of a NBTI stressed p-MOS device. Positive oxide charges and filled donor type interface states are symbolized with circles and rectangles. Trapped holes impact the electrical behavior of the device.

The n-channel transistor of standard CMOS-technologies with SiO2

or SiON gate oxide is almost not affected by bias temperature stress. There is no comparable electrochemical reaction between the interface and electron channel. For future CMOS technologies offering transistors with an High-K gate stack also ‘Positive Bias Temperature Instability’ (PBTI) becomes a severe device reliability concern.

NBTI RECOVERY Beside the strong parameter degradation another phenomenon of NBTI challenges reliability assessments. The stress induced parameter degradation recovers very fast after end of stress [14-21]. The parameter values drift back to the values before the stress. This effect has to be considered for correct parameter extraction during stress experiments. The flow-chart on the right hand side describes the problem: Due to delays of the used measurement equipment and time

demands of Vth extraction routines, the device is already recovered at the point-of-time of the characterization. The threshold voltage is already recovered.

In contrast to experimental measurement conditions, transistors within product circuits do not have long recovery times between stress and next operation (determined by clock frequency).

Vth extraction methods have to consider this effect. Several different methods have been introduced in the literature, each with different advantages and draw-backs [19, 20]. A very fast method is introduced in [15] and [17]. The threshold voltage can be extracted directly within 0.5µs after end of stress. It has to be mentioned that this cannot be achieved with today’s available parameter analyzers. We recorded the data with a self-developed measurement card. Fig. 7 shows recovery curves a different stress time. The threshold is measured continuously after end of stress. for 11 decades of time (black symbols). ). A Vth measurement sequence without stress was done for verification (red line).After end of stress the electrical parameter moves backwards very fast to the values before NBTI stress.

0

-5

-10

-15

-20

-25

-30

10-6 10-4 10-2 1 102 104 106

V T @

delay

=1s

after 1s

after 100s

after 10s

VStress= -2.8VT=125°C

V T @

del

ay=1

µs

finalrelaxationcurve

50% of VT-shift"lost" until startof conventionalmeasurement

VT w/o stress

V T-s

hift

( m

V )

stresstime & measuring delay ( s ) Fig. 7: Ultra fast Vth measurement as a function of stress- and recovery time. After 100s stress the degraded threshold voltage recovers by 50% in the timeframe between 1µs and 1s after end of stress

After 100s stress the degraded threshold voltage recovers by 50%

in the timeframe between 1µs and 1s after end of stress (blue symbols). Neglecting the NBTI recovery phenomenon leads to falsified measurement value and inaccurate lifetime estimations. Nowadays NBTI is the most serious device degradation mechanism and a limiting factor for technology development. It is not completely understood and measures like metal gates will lead to higher electric field even at fixed gate oxide thicknesses. With PBTI an additional severe device degradation of n-MOSFETs with Hi-K gate stacks grows up.

End of device stress

Characterization

Delay due to equipment and measurement

routinescriti

cal t

ime!

End of device stress

Characterization

Delay due to equipment and measurement

routines

End of device stress

Characterization

Delay due to equipment and measurement

routines

Delay due to equipment and measurement

routinescriti

cal t

ime!

criti

cal t

ime!

Fig. 7. Flow-chart illustrating the critical time delay between endof stress and characterization of the test-device. The NBTI degra-dation recovers very fast.

rectangles. NBTI has a pronounced process impact up to thepassivation layer. The process for gate oxide growing and thehydrogen inventory of the entire process influence the NBTIbehavior. SiON gate oxides show enhanced NBTI, but thenitrogen fraction is necessary as a diffusion barrier in the gateoxide of surface channel p-MOSFETs. The barrier preventsboron penetration from the p+ doped poly-silicon into thechannel.

The n-channel transistor of standard CMOS-technologieswith SiO2 or SiON gate oxide is almost not affected by biastemperature stress. There is no comparable electrochemicalreaction between the interface and electron channel. For fu-ture CMOS technologies offering transistors with an High-K gate stack also “Positive Bias Temperature Instability”(PBTI) becomes a severe device reliability concern.

4 NBTI recovery

Beside the strong parameter degradation another phe-nomenon of NBTI challenges reliability assessments. Thestress induced parameter degradation recovers very fast af-ter end of stress (Rangan et al., 2003; Reisinger et al., 2006;Campbell et al., 2006; Reisinger et al., 2007a; Grasser et al.,2007; Reisinger et al., 2007b; Schlunder et al., 2007; Grasseret al., 2008). The parameter values drift back to the valuesbefore the stress. This effect has to be considered for correctparameter extraction during stress experiments. The flow-chart in Fig. 7 describes the problem: due to delays of theused measurement equipment and time demands ofVth ex-traction routines, the device is already recovered at the point-of-time of the characterization. The threshold voltage is al-ready recovered.

O

O

O

SiOO

O

O

SiO

Si

Si

Si

SiSi

Si

Si Si

Si

Si

Si Si

SiSi

SiSi

SiSi

SiSi

SiSiSiSi

SiSi

SiSi SiSi

SiSi

SiSi

SiSi SiSi

SiSiSiSi

amorphesSiO2

monokristalinesSilizium

Grenzfläche

Si

unterschiedlicheGitterstrukturen

Fehlstelle im Oxid

Interface

mono-crystalline silicon

amorphous silicon oxide

different lattice structures

oxide imperfection

O

O

O

SiOO

O

O

SiO

Si

Si

Si

SiSi

Si

Si Si

Si

Si

Si Si

SiSi

SiSi

SiSi

SiSi

SiSiSiSi

SiSi

SiSi SiSi

SiSi

SiSi

SiSi SiSi

SiSiSiSi

amorphesSiO2

monokristalinesSilizium

Grenzfläche

Si

unterschiedlicheGitterstrukturen

Fehlstelle im Oxid

Interface

mono-crystalline silicon

amorphous silicon oxide

different lattice structures

oxide imperfection

Fig. 5: Schematic of the interface region of MOSFETs. Slightly different lattice structures leads to dangling bonds satured by hydrogen. Under NBTI stress the bonds break and the dangling bonds act as interface states

Furthermore the charged interface can reduce the carrier mobility. Fig. 6 illustrates a simplified cross-section of a NBTI stressed p-MOS device. Positive oxide charges and filled donor-type interfaces are symbolized with circles and rectangles. NBTI has a pronounced process impact up to the passivation layer. The process for gate oxide growing and the hydrogen inventory of the entire process influence the NBTI behavior. SiON gate oxides show enhanced NBTI, but the nitrogen fraction is necessary as a diffusion barrier in the gate oxide of surface channel p-MOSFETs. The barrier prevents boron penetration from the p+ doped poly-silicon into the channel.

np+p+

+ + + + + + ++ +++++ +

negatives Potenzialnegative potential

np+p+

+ + + + + + ++ +++++ +

negatives Potenzialnegative potential

Fig. 6: Simplified cross-section of a NBTI stressed p-MOS device. Positive oxide charges and filled donor type interface states are symbolized with circles and rectangles. Trapped holes impact the electrical behavior of the device.

The n-channel transistor of standard CMOS-technologies with SiO2

or SiON gate oxide is almost not affected by bias temperature stress. There is no comparable electrochemical reaction between the interface and electron channel. For future CMOS technologies offering transistors with an High-K gate stack also ‘Positive Bias Temperature Instability’ (PBTI) becomes a severe device reliability concern.

NBTI RECOVERY Beside the strong parameter degradation another phenomenon of NBTI challenges reliability assessments. The stress induced parameter degradation recovers very fast after end of stress [14-21]. The parameter values drift back to the values before the stress. This effect has to be considered for correct parameter extraction during stress experiments. The flow-chart on the right hand side describes the problem: Due to delays of the used measurement equipment and time

demands of Vth extraction routines, the device is already recovered at the point-of-time of the characterization. The threshold voltage is already recovered.

In contrast to experimental measurement conditions, transistors within product circuits do not have long recovery times between stress and next operation (determined by clock frequency).

Vth extraction methods have to consider this effect. Several different methods have been introduced in the literature, each with different advantages and draw-backs [19, 20]. A very fast method is introduced in [15] and [17]. The threshold voltage can be extracted directly within 0.5µs after end of stress. It has to be mentioned that this cannot be achieved with today’s available parameter analyzers. We recorded the data with a self-developed measurement card. Fig. 7 shows recovery curves a different stress time. The threshold is measured continuously after end of stress. for 11 decades of time (black symbols). ). A Vth measurement sequence without stress was done for verification (red line).After end of stress the electrical parameter moves backwards very fast to the values before NBTI stress.

0

-5

-10

-15

-20

-25

-30

10-6 10-4 10-2 1 102 104 106

V T @

delay

=1s

after 1s

after 100s

after 10s

VStress= -2.8VT=125°C

V T @

del

ay=1

µs

finalrelaxationcurve

50% of VT-shift"lost" until startof conventionalmeasurement

VT w/o stress

V T-s

hift

( m

V )

stresstime & measuring delay ( s ) Fig. 7: Ultra fast Vth measurement as a function of stress- and recovery time. After 100s stress the degraded threshold voltage recovers by 50% in the timeframe between 1µs and 1s after end of stress

After 100s stress the degraded threshold voltage recovers by 50%

in the timeframe between 1µs and 1s after end of stress (blue symbols). Neglecting the NBTI recovery phenomenon leads to falsified measurement value and inaccurate lifetime estimations. Nowadays NBTI is the most serious device degradation mechanism and a limiting factor for technology development. It is not completely understood and measures like metal gates will lead to higher electric field even at fixed gate oxide thicknesses. With PBTI an additional severe device degradation of n-MOSFETs with Hi-K gate stacks grows up.

End of device stress

Characterization

Delay due to equipment and measurement

routinescriti

cal t

ime!

End of device stress

Characterization

Delay due to equipment and measurement

routines

End of device stress

Characterization

Delay due to equipment and measurement

routines

Delay due to equipment and measurement

routinescriti

cal t

ime!

criti

cal t

ime!

Fig. 8. Ultra fastVth measurement as a function of stress- and re-covery time. After 100 s stress the degraded threshold voltage re-covers by 50% in the timeframe between 1µs and 1 s after end ofstress.

In contrast to experimental measurement conditions, tran-sistors within product circuits do not have long recoverytimes between stress and next operation (determined by clockfrequency).

Vth extraction methods have to consider this effect. Sev-eral different methods have been introduced in the literature,each with different advantages and draw-backs (Reisingeret al., 2007b; Schlunder et al., 2007). A very fast methodis introduced inReisinger et al.(2006) andReisinger et al.(2007a). The threshold voltage can be extracted directlywithin 0.5µs after end of stress. It has to be mentioned thatthis cannot be achieved with today’s available parameter ana-lyzers. We recorded the data with a self-developed measure-ment card. Figure 8 shows recovery curves at different stresstime. The threshold is measured continuously after end ofstress for 11 decades of time (black symbols). A Vth mea-surement sequence without stress was done for verification(red line). After end of stress the electrical parameter movesbackwards very fast to the values before NBTI stress.

After 100 s stress the degraded threshold voltage recoversby 50% in the timeframe between 1µs and 1 s after end ofstress (blue symbols). Neglecting the NBTI recovery phe-nomenon leads to falsified measurement value and inaccu-rate lifetime estimations. Nowadays NBTI is the most seri-ous device degradation mechanism and a limiting factor fortechnology development. It is not completely understood andmeasures like metal gates will lead to higher electric fieldeven at fixed gate oxide thicknesses. With PBTI an addi-tional severe device degradation of n-MOSFETs with Hi-Kgate stacks grows up.

Adv. Radio Sci., 7, 201–211, 2009 www.adv-radio-sci.net/7/201/2009/

Page 5: Device reliability challenges for modern semiconductor circuit … · 2020. 6. 9. · the Creative Commons Attribution 3.0 License. Advances in Radio Science Device reliability challenges

C. Schlunder: Device reliability challenges for modern semiconductor circuit design 205

IMPACT ON CIRCUIT FUNCTION Device degradation after HCS or NBTI has an impact on circuit

function. If the electrical parameter of one device leaves a specific window, a correct circuit function can not be guaranteed any more. The transistors are not necessarily destroyed (e.g. gate oxide breakdown), the degradation of the electrical behavior can lead to IC failures. In the following examples for typical analogue and digital application will be given. Furthermore a possible impact of ‘Low power techniques’ will be introduced.

The impact of degraded electrical device parameters on digital circuits can be easily explained at an inverter as a simple basic block of digital applications.

Vin V outV in V out

Fig. 8: CMOS inverter as a simple example for the degradation impact on circuit fnction. The capacitance at the output symbolizes a following stage. The inverter has to charge or discharge the gate capacitance of the next stage.

Fig. 8 shows a schematic diagram of a CMOS inverter. The

capacitance at the output symbolizes a following stage. The inverter has to charge or discharge the gate capacitance of the next stage. Fig. 9 plots an exemplary chronological sequence of an input- and corresponding output-signal of the CMOS inverter. Four different regions are marked with numbers describing different static and dynamic stress conditions. In region 1) the inverter has to discharge the next stage, the output signal has to be driven down to zero (better: low level). For that mainly the n-MOS device has to drive the necessary current to discharge the (gate-) capacitance of the next stage.

V in

V out

time

time

V in

V out

time

time

Fig. 9: Example for a chronological sequence of an input- and corresponding output-signal of an CMOS inverter (Fig. 8). Four different regions are marked with numbers describing different static and dynamic stress conditions.

In this region mainly Hot Carrier Stress for this n-MOS device occurs. After finishing this job the circuit is in a static mode (region 2).

In this region no current but leakage current flows within the inverter. The n-channel device is under PBTI condition. The input signal and therefore the gate of the n-MOS is on high level, the drain-, source- and substrate contact is on low level. n-MOSFETs with SiO2 or SiON gate oxides are almost not affected, a high-K n-channel device would degrade under these PBTI conditions. Entering regions 3) the capacitance of the next stage has to be charged up to high level. For this task mainly the p-MOSFETs is required. The device has to conduct the current from VDD to the capacitance. In this region mainly HCS for this p-MOS transistor occurs.

Region 4) defines again a static stress mode. In this case the p-MOSFET of the inverter is loaded by NBTI stress. The gate electrode is on low level, all other terminals are on high level (VDD). An elevated temperature accelerating NBTI can originate from the environment or from the circuits itself.

The induced degradations of the electrical device parameter impact the function of the inverter. First of all a reduction of the current drive capability of this stage occurs. Furthermore the switching thresholds of the inverter shifts and duty cycle (high level to low level ratio) changes [22]. This changed behavior of one circuit block influences the entire circuit.

On the right hand side a part of a logic path is pictured. The degradation of the different elements leads to longer signal rise times. As a result the time delay for loading the next stage (propagation delay) is increased. The set-up and hold time of flip-flops changes. Furthermore the degradation impacts the speed and noise immunity. This is critical especially at supply voltages less than nominal (low power applications).

A SRAM cell is another typical basic block of digital circuits and can be used as another good example for circuit degradation. Fig. 10 shows the schematic diagram for a typical 6 transistor SRAM cell.

WL

BL BLQ

A B

Fig. 10: Schematic diagram of a typical 6 transistor SRAM cell. The stress conditions for the different devices and the corresponding impact on the cell function

CLKRegister

Register CLK

CLKRegisterRegister

Register CLKRegister CLK

Fig. 9. CMOS inverter as a simple example for the degradation im-pact on circuit function. The capacitance at the output symbolizesa following stage. The inverter has to charge or discharge the gatecapacitance of the next stage.

5 Impact on circuit function

Device degradation after HCS or NBTI has an impact oncircuit function. If the electrical parameter of one deviceleaves a specific window, a correct circuit function can notbe guaranteed any more. The transistors are not necessarilydestroyed (e.g. gate oxide breakdown), the degradation of theelectrical behavior can lead to IC failures. In the followingexamples for typical analogue and digital application will begiven. Furthermore a possible impact of “Low power tech-niques” will be introduced.

The impact of degraded electrical device parameters ondigital circuits can be easily explained at an inverter as a sim-ple basic block of digital applications.

Figure 9 shows a schematic diagram of a CMOS inverter.The capacitance at the output symbolizes a following stage.The inverter has to charge or discharge the gate capacitanceof the next stage. Figure 10 plots an exemplary chronologi-cal sequence of an input- and corresponding output-signal ofthe CMOS inverter. Four different regions are marked withnumbers describing different static and dynamic stress con-ditions. In region (1) the inverter has to discharge the nextstage, the output signal has to be driven down to zero (better:low level). For that mainly the n-MOS device has to drivethe necessary current to discharge the (gate-) capacitance ofthe next stage.

In this region mainly Hot Carrier Stress for this n-MOSdevice occurs. After finishing this job the circuit is in a staticmode (region 2).

In this region no current but leakage current flows withinthe inverter. The n-channel device is under PBTI condition.

IMPACT ON CIRCUIT FUNCTION Device degradation after HCS or NBTI has an impact on circuit

function. If the electrical parameter of one device leaves a specific window, a correct circuit function can not be guaranteed any more. The transistors are not necessarily destroyed (e.g. gate oxide breakdown), the degradation of the electrical behavior can lead to IC failures. In the following examples for typical analogue and digital application will be given. Furthermore a possible impact of ‘Low power techniques’ will be introduced.

The impact of degraded electrical device parameters on digital circuits can be easily explained at an inverter as a simple basic block of digital applications.

Vin V outV in V out

Fig. 8: CMOS inverter as a simple example for the degradation impact on circuit fnction. The capacitance at the output symbolizes a following stage. The inverter has to charge or discharge the gate capacitance of the next stage.

Fig. 8 shows a schematic diagram of a CMOS inverter. The

capacitance at the output symbolizes a following stage. The inverter has to charge or discharge the gate capacitance of the next stage. Fig. 9 plots an exemplary chronological sequence of an input- and corresponding output-signal of the CMOS inverter. Four different regions are marked with numbers describing different static and dynamic stress conditions. In region 1) the inverter has to discharge the next stage, the output signal has to be driven down to zero (better: low level). For that mainly the n-MOS device has to drive the necessary current to discharge the (gate-) capacitance of the next stage.

V in

V out

time

time

V in

V out

time

time

Fig. 9: Example for a chronological sequence of an input- and corresponding output-signal of an CMOS inverter (Fig. 8). Four different regions are marked with numbers describing different static and dynamic stress conditions.

In this region mainly Hot Carrier Stress for this n-MOS device occurs. After finishing this job the circuit is in a static mode (region 2).

In this region no current but leakage current flows within the inverter. The n-channel device is under PBTI condition. The input signal and therefore the gate of the n-MOS is on high level, the drain-, source- and substrate contact is on low level. n-MOSFETs with SiO2 or SiON gate oxides are almost not affected, a high-K n-channel device would degrade under these PBTI conditions. Entering regions 3) the capacitance of the next stage has to be charged up to high level. For this task mainly the p-MOSFETs is required. The device has to conduct the current from VDD to the capacitance. In this region mainly HCS for this p-MOS transistor occurs.

Region 4) defines again a static stress mode. In this case the p-MOSFET of the inverter is loaded by NBTI stress. The gate electrode is on low level, all other terminals are on high level (VDD). An elevated temperature accelerating NBTI can originate from the environment or from the circuits itself.

The induced degradations of the electrical device parameter impact the function of the inverter. First of all a reduction of the current drive capability of this stage occurs. Furthermore the switching thresholds of the inverter shifts and duty cycle (high level to low level ratio) changes [22]. This changed behavior of one circuit block influences the entire circuit.

On the right hand side a part of a logic path is pictured. The degradation of the different elements leads to longer signal rise times. As a result the time delay for loading the next stage (propagation delay) is increased. The set-up and hold time of flip-flops changes. Furthermore the degradation impacts the speed and noise immunity. This is critical especially at supply voltages less than nominal (low power applications).

A SRAM cell is another typical basic block of digital circuits and can be used as another good example for circuit degradation. Fig. 10 shows the schematic diagram for a typical 6 transistor SRAM cell.

WL

BL BLQ

A B

Fig. 10: Schematic diagram of a typical 6 transistor SRAM cell. The stress conditions for the different devices and the corresponding impact on the cell function

CLKRegister

Register CLK

CLKRegisterRegister

Register CLKRegister CLK

Fig. 10.Example for a chronological sequence of an input- and cor-responding output-signal of an CMOS inverter (Fig. 9). Four differ-ent regions are marked with numbers describing different static anddynamic stress conditions.

IMPACT ON CIRCUIT FUNCTION Device degradation after HCS or NBTI has an impact on circuit

function. If the electrical parameter of one device leaves a specific window, a correct circuit function can not be guaranteed any more. The transistors are not necessarily destroyed (e.g. gate oxide breakdown), the degradation of the electrical behavior can lead to IC failures. In the following examples for typical analogue and digital application will be given. Furthermore a possible impact of ‘Low power techniques’ will be introduced.

The impact of degraded electrical device parameters on digital circuits can be easily explained at an inverter as a simple basic block of digital applications.

Vin V outV in V out

Fig. 8: CMOS inverter as a simple example for the degradation impact on circuit fnction. The capacitance at the output symbolizes a following stage. The inverter has to charge or discharge the gate capacitance of the next stage.

Fig. 8 shows a schematic diagram of a CMOS inverter. The

capacitance at the output symbolizes a following stage. The inverter has to charge or discharge the gate capacitance of the next stage. Fig. 9 plots an exemplary chronological sequence of an input- and corresponding output-signal of the CMOS inverter. Four different regions are marked with numbers describing different static and dynamic stress conditions. In region 1) the inverter has to discharge the next stage, the output signal has to be driven down to zero (better: low level). For that mainly the n-MOS device has to drive the necessary current to discharge the (gate-) capacitance of the next stage.

V in

V out

time

time

V in

V out

time

time

Fig. 9: Example for a chronological sequence of an input- and corresponding output-signal of an CMOS inverter (Fig. 8). Four different regions are marked with numbers describing different static and dynamic stress conditions.

In this region mainly Hot Carrier Stress for this n-MOS device occurs. After finishing this job the circuit is in a static mode (region 2).

In this region no current but leakage current flows within the inverter. The n-channel device is under PBTI condition. The input signal and therefore the gate of the n-MOS is on high level, the drain-, source- and substrate contact is on low level. n-MOSFETs with SiO2 or SiON gate oxides are almost not affected, a high-K n-channel device would degrade under these PBTI conditions. Entering regions 3) the capacitance of the next stage has to be charged up to high level. For this task mainly the p-MOSFETs is required. The device has to conduct the current from VDD to the capacitance. In this region mainly HCS for this p-MOS transistor occurs.

Region 4) defines again a static stress mode. In this case the p-MOSFET of the inverter is loaded by NBTI stress. The gate electrode is on low level, all other terminals are on high level (VDD). An elevated temperature accelerating NBTI can originate from the environment or from the circuits itself.

The induced degradations of the electrical device parameter impact the function of the inverter. First of all a reduction of the current drive capability of this stage occurs. Furthermore the switching thresholds of the inverter shifts and duty cycle (high level to low level ratio) changes [22]. This changed behavior of one circuit block influences the entire circuit.

On the right hand side a part of a logic path is pictured. The degradation of the different elements leads to longer signal rise times. As a result the time delay for loading the next stage (propagation delay) is increased. The set-up and hold time of flip-flops changes. Furthermore the degradation impacts the speed and noise immunity. This is critical especially at supply voltages less than nominal (low power applications).

A SRAM cell is another typical basic block of digital circuits and can be used as another good example for circuit degradation. Fig. 10 shows the schematic diagram for a typical 6 transistor SRAM cell.

WL

BL BLQ

A B

Fig. 10: Schematic diagram of a typical 6 transistor SRAM cell. The stress conditions for the different devices and the corresponding impact on the cell function

CLKRegister

Register CLK

CLKRegisterRegister

Register CLKRegister CLK

Fig. 11.Example for a logic circuit path. Due to device degradationthe set up and hold time of flip-flops can change. IC-failures canoccur, especially in low power application with supply voltages lessthan nominal.

The input signal and therefore the gate of the n-MOS is onhigh level, the drain-, source- and substrate contact is on lowlevel. n-MOSFETs with SiO2 or SiON gate oxides are al-most not affected, a high-K n-channel device would degradeunder these PBTI conditions. Entering regions (3) the capac-itance of the next stage has to be charged up to high level.For this task mainly the p-MOSFETs is required. The devicehas to conduct the current fromVDD to the capacitance. Inthis region mainly HCS for this p-MOS transistor occurs.

www.adv-radio-sci.net/7/201/2009/ Adv. Radio Sci., 7, 201–211, 2009

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206 C. Schlunder: Device reliability challenges for modern semiconductor circuit design

IMPACT ON CIRCUIT FUNCTION Device degradation after HCS or NBTI has an impact on circuit

function. If the electrical parameter of one device leaves a specific window, a correct circuit function can not be guaranteed any more. The transistors are not necessarily destroyed (e.g. gate oxide breakdown), the degradation of the electrical behavior can lead to IC failures. In the following examples for typical analogue and digital application will be given. Furthermore a possible impact of ‘Low power techniques’ will be introduced.

The impact of degraded electrical device parameters on digital circuits can be easily explained at an inverter as a simple basic block of digital applications.

Vin V outV in V out

Fig. 8: CMOS inverter as a simple example for the degradation impact on circuit fnction. The capacitance at the output symbolizes a following stage. The inverter has to charge or discharge the gate capacitance of the next stage.

Fig. 8 shows a schematic diagram of a CMOS inverter. The

capacitance at the output symbolizes a following stage. The inverter has to charge or discharge the gate capacitance of the next stage. Fig. 9 plots an exemplary chronological sequence of an input- and corresponding output-signal of the CMOS inverter. Four different regions are marked with numbers describing different static and dynamic stress conditions. In region 1) the inverter has to discharge the next stage, the output signal has to be driven down to zero (better: low level). For that mainly the n-MOS device has to drive the necessary current to discharge the (gate-) capacitance of the next stage.

V in

V out

time

time

V in

V out

time

time

Fig. 9: Example for a chronological sequence of an input- and corresponding output-signal of an CMOS inverter (Fig. 8). Four different regions are marked with numbers describing different static and dynamic stress conditions.

In this region mainly Hot Carrier Stress for this n-MOS device occurs. After finishing this job the circuit is in a static mode (region 2).

In this region no current but leakage current flows within the inverter. The n-channel device is under PBTI condition. The input signal and therefore the gate of the n-MOS is on high level, the drain-, source- and substrate contact is on low level. n-MOSFETs with SiO2 or SiON gate oxides are almost not affected, a high-K n-channel device would degrade under these PBTI conditions. Entering regions 3) the capacitance of the next stage has to be charged up to high level. For this task mainly the p-MOSFETs is required. The device has to conduct the current from VDD to the capacitance. In this region mainly HCS for this p-MOS transistor occurs.

Region 4) defines again a static stress mode. In this case the p-MOSFET of the inverter is loaded by NBTI stress. The gate electrode is on low level, all other terminals are on high level (VDD). An elevated temperature accelerating NBTI can originate from the environment or from the circuits itself.

The induced degradations of the electrical device parameter impact the function of the inverter. First of all a reduction of the current drive capability of this stage occurs. Furthermore the switching thresholds of the inverter shifts and duty cycle (high level to low level ratio) changes [22]. This changed behavior of one circuit block influences the entire circuit.

On the right hand side a part of a logic path is pictured. The degradation of the different elements leads to longer signal rise times. As a result the time delay for loading the next stage (propagation delay) is increased. The set-up and hold time of flip-flops changes. Furthermore the degradation impacts the speed and noise immunity. This is critical especially at supply voltages less than nominal (low power applications).

A SRAM cell is another typical basic block of digital circuits and can be used as another good example for circuit degradation. Fig. 10 shows the schematic diagram for a typical 6 transistor SRAM cell.

WL

BL BLQ

A B

Fig. 10: Schematic diagram of a typical 6 transistor SRAM cell. The stress conditions for the different devices and the corresponding impact on the cell function

CLKRegister

Register CLK

CLKRegisterRegister

Register CLKRegister CLK

Fig. 12. Schematic diagram of a typical 6 transistor SRAM cell.The stress conditions and the impact of degradation can be trans-ferred from a single inverter.

Region (4) defines again a static stress mode. In this casethe p-MOSFET of the inverter is loaded by NBTI stress. Thegate electrode is on low level, all other terminals are on highlevel (VDD). An elevated temperature accelerating NBTI canoriginate from the environment or from the circuits itself.

The induced degradations of the electrical device parame-ter impact the function of the inverter. First of all a reductionof the current drive capability of this stage occurs. Further-more the switching thresholds of the inverter shifts and theduty cycle (high level to low level ratio) changes (Reddy etal., 2002). This changed behavior of one circuit block influ-ences the entire circuit.

In Fig. 11, a part of a logic path is pictured. The degra-dation of the different elements leads to longer signal risetimes. As a result the time delay for loading the next stage(propagation delay) is increased. The set-up and hold timeof flip-flops changes. Furthermore the degradation impactsthe speed and noise immunity. This is critical especially atsupply voltages less than nominal (low power applications).

A SRAM cell is another typical basic block of digital cir-cuits and can be used as another good example for circuitdegradation. Figure 12 shows the schematic diagram for atypical 6 transistor SRAM cell.

Since the function is based on two cross-coupled invert-ers, both the stress conditions of the device and the impactof degradation on the circuit can be transferred from a sin-gle inverter. Read and write operations are dynamic modesand lead accordingly to HCS. All the remaining period theSRAM cell is in static mode, corresponding in NBTI (andPBTI).

Dependent of the data the cell has to store (1 or 0), thep-MOS transistor of the left or of the right inverter is un-der NBTI stress. Since this static mode typically occurs forbiggest part of the lifetime, it becomes clear that degradation

Since the function is based on two cross-coupled inverters, both the stress conditions of the device and the impact of degradation on the circuit can be transferred from a single inverter. Read and write operations are dynamic modes and lead accordingly to HCS. All the remaining period the SRAM cell is in static mode, corresponding in NBTI (and PBTI).

Dependent of the data the cell has to store (1 or 0), the p-MOS transistor of the left or of the right inverter is under NBTI stress. Since this static mode typically occurs for biggest part of the lifetime, it becomes clear that degradation in static mode and accordingly NBTI is the most severe reliability concern. The NBTI degradation of the p-channel devices within SRAM cells leads mainly to a decrease of the stability of the cell [23].

VB

VA

VB

VA

Fig. 11: Butterfly-diagram of a SRAM cell. The two inverter curves determine the form. The area of the turquoise square is a measure of the cell stability.

Fig. 11 shows a ‘Butterfly-diagram’ of a 6T-SRAM cell. The two

inverter curves determine the form. These diagrams are used to describe the stability of the cell. The area of the turquoise square is a measure for this parameter. A degradation of the two inverters has an impact on ß- and n-/p-MOS ratio of the SRAM-cell. The static noise margin and dynamic read stability decrease. The cell shows an increased sensitivity against Soft Error Rate (SER), supply voltage drops, noise, etc. Furthermore an increase of access time is possible.

TRANSISTOR RELIABILITY UNDER ANALOGUE OPERATION

Reliability evaluation of MOS transistors under analog operation requires a specifically adapted approach. The operating points and thus the stress conditions significantly differ. Different device parameters must be considered in the circuit design process [24-29].

Fig. 12 illustrates the background for the different impact of device degradation on analogue and mixed signal applications. The diagram plots the relative degradation of the input characteristic of a MOSFET as a function of operation gate voltage and stress time. Typical NBTI degradation behavior can be obtained with strongest drift close to the threshold voltage and weaker drift with increasing gate voltages.

Since for many analog applications the effective gate-to-source voltage is in the order of a few 100mV, the impact of device degradation is much stronger for circuits of analogue or mixed signal applications. In those circuits the operation point relies on the accurate matching of paired transistors.

|VG| [V]0.5 1.0 1.5 2.0

I D/I

D[%]

-30

-25

-20

-15

-10

-5

0

Characterization with |VD| = 1.25 V , T=125°C

tstress

Charakterisierung mit

tBelastung

∆ID/I D

[%]

tstress

characterization with

|VG| [V]0.5 1.0 1.5 2.0

I D/I

D[%]

-30

-25

-20

-15

-10

-5

0

Characterization with |VD| = 1.25 V , T=125°C

tstress

Charakterisierung mit

tBelastung

∆ID/I D

[%]

tstress

characterization with

Fig. 12: Relative degradation of the input characteristic of a MOSFET as a function of operation gate voltage and stress time. Strong degradation for operation points with small gate voltages and a weaker impact on operation with high gate voltages can be obtained.

Fig. 13 shows the schematic diagram for a two stage operational

amplifier/comparator. Here the correct circuit function relies on the accurate matching of the input devices (M4 and M5). In the power-down mode, the bias current is switched off to avoid power consumption of the inactive circuit, but the supply voltages are not driven down in order to allow fast reactivation of the circuit without switching of the supply lines. The potentials of the internal nodes of the circuit are then determined by the subthreshold characteristics of the devices, leakage paths, and by the signals applied to the inputs. In our example, the connection between drain and gate of M3 and between drain and gate of M6 leads to low gate-to-bulk/well voltages of the transistors connected to the gates of M3 and M6 (M1, M2, M3, M6, and M7), so that these devices are not prone to high oxide fields.

Fig. 13: Two stage operational amplifier/comparator. The switch drives the circuit in active or power down mode. During active mode HCS and inhomogenous NBTI can occur. However the worst case is the power down mode, where the input devices are exposed to NBTI with full VDD.

Fig. 13. Buttefly-diagram of a SRAM cell. The two inverter curvesdetermine the form. The area of the turquoise square is a measurefo the cell stability.

in static mode and accordingly NBTI is the most severe re-liability concern. The NBTI degradation of the p-channeldevices within SRAM cells leads mainly to a decrease of thestability of the cell (LaRosa et al., 2006).

Figure 13 shows a “Butterfly-diagram” of a 6T-SRAMcell. The two inverter curves determine its shape. Thesediagrams are used to describe the stability of the cell. Thearea of the turquoise square is a measure for this parame-ter. A degradation of the two inverters has an impact onβ-and n-/p-MOS ratio of the SRAM-cell. The static noise mar-gin and dynamic read stability decrease. The cell shows anincreased sensitivity against Soft Error Rate (SER), supplyvoltage drops, noise, etc. Furthermore an increase of accesstime is possible.

6 Transistor reliability under analogue operation

Reliability evaluation of MOS transistors under analog oper-ation requires a specifically adapted approach. The operatingpoints and thus the stress conditions significantly differ. Dif-ferent device parameters must be considered in the circuit de-sign process (Chung et al., 1990; Thewes et al., 1999, 2001;Schlunder et al., 2003; Chaparala et al., 2003; Schlunder etal., 2005).

Figure 14 illustrates the background for the different im-pact of device degradation on analogue and mixed signal ap-plications. The diagram plots the relative degradation of theinput characteristic of a MOSFET as a function of operationgate voltage and stress time. Typical NBTI degradation be-havior can be obtained with strongest drift close to the thresh-old voltage and weaker drift with increasing gate voltages.

Adv. Radio Sci., 7, 201–211, 2009 www.adv-radio-sci.net/7/201/2009/

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C. Schlunder: Device reliability challenges for modern semiconductor circuit design 207

Since the function is based on two cross-coupled inverters, both the stress conditions of the device and the impact of degradation on the circuit can be transferred from a single inverter. Read and write operations are dynamic modes and lead accordingly to HCS. All the remaining period the SRAM cell is in static mode, corresponding in NBTI (and PBTI).

Dependent of the data the cell has to store (1 or 0), the p-MOS transistor of the left or of the right inverter is under NBTI stress. Since this static mode typically occurs for biggest part of the lifetime, it becomes clear that degradation in static mode and accordingly NBTI is the most severe reliability concern. The NBTI degradation of the p-channel devices within SRAM cells leads mainly to a decrease of the stability of the cell [23].

VB

VA

VB

VA

Fig. 11: Butterfly-diagram of a SRAM cell. The two inverter curves determine the form. The area of the turquoise square is a measure of the cell stability.

Fig. 11 shows a ‘Butterfly-diagram’ of a 6T-SRAM cell. The two

inverter curves determine the form. These diagrams are used to describe the stability of the cell. The area of the turquoise square is a measure for this parameter. A degradation of the two inverters has an impact on ß- and n-/p-MOS ratio of the SRAM-cell. The static noise margin and dynamic read stability decrease. The cell shows an increased sensitivity against Soft Error Rate (SER), supply voltage drops, noise, etc. Furthermore an increase of access time is possible.

TRANSISTOR RELIABILITY UNDER ANALOGUE OPERATION

Reliability evaluation of MOS transistors under analog operation requires a specifically adapted approach. The operating points and thus the stress conditions significantly differ. Different device parameters must be considered in the circuit design process [24-29].

Fig. 12 illustrates the background for the different impact of device degradation on analogue and mixed signal applications. The diagram plots the relative degradation of the input characteristic of a MOSFET as a function of operation gate voltage and stress time. Typical NBTI degradation behavior can be obtained with strongest drift close to the threshold voltage and weaker drift with increasing gate voltages.

Since for many analog applications the effective gate-to-source voltage is in the order of a few 100mV, the impact of device degradation is much stronger for circuits of analogue or mixed signal applications. In those circuits the operation point relies on the accurate matching of paired transistors.

|VG| [V]0.5 1.0 1.5 2.0

I D/I

D[%]

-30

-25

-20

-15

-10

-5

0

Characterization with |VD| = 1.25 V , T=125°C

tstress

Charakterisierung mit

tBelastung

∆ID/I D

[%]

tstress

characterization with

|VG| [V]0.5 1.0 1.5 2.0

I D/I

D[%]

-30

-25

-20

-15

-10

-5

0

Characterization with |VD| = 1.25 V , T=125°C

tstress

Charakterisierung mit

tBelastung

∆ID/I D

[%]

tstress

characterization with

Fig. 12: Relative degradation of the input characteristic of a MOSFET as a function of operation gate voltage and stress time. Strong degradation for operation points with small gate voltages and a weaker impact on operation with high gate voltages can be obtained.

Fig. 13 shows the schematic diagram for a two stage operational

amplifier/comparator. Here the correct circuit function relies on the accurate matching of the input devices (M4 and M5). In the power-down mode, the bias current is switched off to avoid power consumption of the inactive circuit, but the supply voltages are not driven down in order to allow fast reactivation of the circuit without switching of the supply lines. The potentials of the internal nodes of the circuit are then determined by the subthreshold characteristics of the devices, leakage paths, and by the signals applied to the inputs. In our example, the connection between drain and gate of M3 and between drain and gate of M6 leads to low gate-to-bulk/well voltages of the transistors connected to the gates of M3 and M6 (M1, M2, M3, M6, and M7), so that these devices are not prone to high oxide fields.

Fig. 13: Two stage operational amplifier/comparator. The switch drives the circuit in active or power down mode. During active mode HCS and inhomogenous NBTI can occur. However the worst case is the power down mode, where the input devices are exposed to NBTI with full VDD.

Fig. 14. Relative degradation of the input characteristic of a MOS-FET as a function of operation gate voltage and stress time. Strongdegradation for operation points with small gate voltages and aweaker impact on operation with high gate voltages can be obtained.

Since for many analog applications the effective gate-to-source voltage is in the order of a few 100 mV, the impact ofdevice degradation is much stronger for circuits of analogueor mixed signal applications. In those circuits the operationpoint relies on the accurate matching of paired transistors.

Figure 15 shows the schematic diagram for a two stageoperational amplifier/comparator. Here the correct circuitfunction relies on the accurate matching of the input devices(M4 and M5). In the power-down mode, the bias currentis switched off to avoid power consumption of the inactivecircuit, but the supply voltages are not driven down in orderto allow fast reactivation of the circuit without switching ofthe supply lines. The potentials of the internal nodes of thecircuit are then determined by the subthreshold characteris-tics of the devices, leakage paths, and by the signals appliedto the inputs. In our example, the connection between drainand gate of M3 and between drain and gate of M6 leads tolow gate-to-bulk/well voltages of the transistors connected tothe gates of M3 and M6 (M1, M2, M3, M6, and M7), so thatthese devices are not prone to high oxide fields.

However, high values of gate-to-channel or gate-to-bulk/well voltage can occur in the case of M4, M5, and M8according to the values of the subthreshold currents of M1,M6, and M7 and possible further leakage paths. If in addi-tion high temperature is applied to the circuit (e.g. providedby the environment) NBTI conditions can occur. To evaluatethe effect of NBTI applied to the input devices M4 and M5under active mode operation conditions, we must considerthat a defined (fixed) current is forced through these transis-tors by current source transistor M1.

Since the function is based on two cross-coupled inverters, both the stress conditions of the device and the impact of degradation on the circuit can be transferred from a single inverter. Read and write operations are dynamic modes and lead accordingly to HCS. All the remaining period the SRAM cell is in static mode, corresponding in NBTI (and PBTI).

Dependent of the data the cell has to store (1 or 0), the p-MOS transistor of the left or of the right inverter is under NBTI stress. Since this static mode typically occurs for biggest part of the lifetime, it becomes clear that degradation in static mode and accordingly NBTI is the most severe reliability concern. The NBTI degradation of the p-channel devices within SRAM cells leads mainly to a decrease of the stability of the cell [23].

VB

VA

VB

VA

Fig. 11: Butterfly-diagram of a SRAM cell. The two inverter curves determine the form. The area of the turquoise square is a measure of the cell stability.

Fig. 11 shows a ‘Butterfly-diagram’ of a 6T-SRAM cell. The two

inverter curves determine the form. These diagrams are used to describe the stability of the cell. The area of the turquoise square is a measure for this parameter. A degradation of the two inverters has an impact on ß- and n-/p-MOS ratio of the SRAM-cell. The static noise margin and dynamic read stability decrease. The cell shows an increased sensitivity against Soft Error Rate (SER), supply voltage drops, noise, etc. Furthermore an increase of access time is possible.

TRANSISTOR RELIABILITY UNDER ANALOGUE OPERATION

Reliability evaluation of MOS transistors under analog operation requires a specifically adapted approach. The operating points and thus the stress conditions significantly differ. Different device parameters must be considered in the circuit design process [24-29].

Fig. 12 illustrates the background for the different impact of device degradation on analogue and mixed signal applications. The diagram plots the relative degradation of the input characteristic of a MOSFET as a function of operation gate voltage and stress time. Typical NBTI degradation behavior can be obtained with strongest drift close to the threshold voltage and weaker drift with increasing gate voltages.

Since for many analog applications the effective gate-to-source voltage is in the order of a few 100mV, the impact of device degradation is much stronger for circuits of analogue or mixed signal applications. In those circuits the operation point relies on the accurate matching of paired transistors.

|VG| [V]0.5 1.0 1.5 2.0

I D/I

D[%]

-30

-25

-20

-15

-10

-5

0

Characterization with |VD| = 1.25 V , T=125°C

tstress

Charakterisierung mit

tBelastung

∆ID/I D

[%]

tstress

characterization with

|VG| [V]0.5 1.0 1.5 2.0

I D/I

D[%]

-30

-25

-20

-15

-10

-5

0

Characterization with |VD| = 1.25 V , T=125°C

tstress

Charakterisierung mit

tBelastung

∆ID/I D

[%]

tstress

characterization with

Fig. 12: Relative degradation of the input characteristic of a MOSFET as a function of operation gate voltage and stress time. Strong degradation for operation points with small gate voltages and a weaker impact on operation with high gate voltages can be obtained.

Fig. 13 shows the schematic diagram for a two stage operational

amplifier/comparator. Here the correct circuit function relies on the accurate matching of the input devices (M4 and M5). In the power-down mode, the bias current is switched off to avoid power consumption of the inactive circuit, but the supply voltages are not driven down in order to allow fast reactivation of the circuit without switching of the supply lines. The potentials of the internal nodes of the circuit are then determined by the subthreshold characteristics of the devices, leakage paths, and by the signals applied to the inputs. In our example, the connection between drain and gate of M3 and between drain and gate of M6 leads to low gate-to-bulk/well voltages of the transistors connected to the gates of M3 and M6 (M1, M2, M3, M6, and M7), so that these devices are not prone to high oxide fields.

Fig. 13: Two stage operational amplifier/comparator. The switch drives the circuit in active or power down mode. During active mode HCS and inhomogenous NBTI can occur. However the worst case is the power down mode, where the input devices are exposed to NBTI with full VDD.

Fig. 15. Two stage operational amplifier/comparator. The switchdrives the circuit in active or power down mode. During activemode HCS and inhomogenous NBTI can occur. However the worstcase is the power down mode, where the input devices are exposedto NBTI with full V DD .

Therefore, M4 and M5 are operated with approximatelythe same drain current before and after stress. Thus the de-vice degradation must be compensated by an increase of theabsolute value of the gate-to-source voltage. Asymmetric op-eration of the input branches of the circuit in Fig. 15 or asym-metric degradation of the input devices under symmetricalstress conditions thus leads to a stress-induced offset volt-age of the circuit which equals the difference of the stress-induced threshold voltage degradations of the input devices.

7 Low Power Techniques

In the following Low Power Techniques and their possibleimpact on device reliability is discussed. LP techniques areused in circuits for modern portable applications like PDAs,mobile phones, etc. to increase the standby time with ac-cumulators. Furthermore Low Power is also used in highperformance application to reduce power dissipation and ac-cordlingly the demand for cooling (CPUs/GPUs)

Low power systems/circuit designs can affect the reliabil-ity of the integrated circuits. One typical example for thesetechniques are systems with “Sleep Transistors”. Figure 16helps to understand this approach. The schematic shows ablock diagram of a test chip with several Low Power Tech-niques assembled together to evaluate the behavior of the dif-ferent techniques. We focus here on the “Sleep Transistor”approach which is based on leakage power control.

A p-MOS connects the external VCC to supply rails (Vir-tual VCC), or an nMOS connects the external ground VSSto the ground rail (Virtual VSS). These sleep transistors aredistributed throughout the layout. The area overhead is about

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208 C. Schlunder: Device reliability challenges for modern semiconductor circuit design

However, high values of gate-to-channel or gate-to-bulk/well voltage can occur in the case of M4, M5, and M8 according to the values of the subthreshold currents of M1, M6, and M7 and possible further leakage paths. If in addition high temperature is applied to the circuit (e.g. provided by the environment) NBTI conditions can occur. To evaluate the effect of NBTI applied to the input devices M4 and M5 under active mode operation conditions, we must consider that a defined (fixed) current is forced through these transistors by current source transistor M1.

Therefore, M4 and M5 are operated with approximately the same drain current before and after stress. Thus the device degradation must be compensated by an increase of the absolute value of the gate-to-source voltage. Asymmetric operation of the input branches of the circuit in Fig. 13 or asymmetric degradation of the input devices under symmetrical stress conditions thus leads to a stress-induced offset voltage of the circuit which equals the difference of the stress-induced threshold voltage degradations of the input devices.

LOW POWER TECHNIQUES In the following Low Power Techniques and their possible impact

on device reliability is discussed. LP techniques are used in circuits for modern portable applications like PDAs, mobile phones, etc. to increase to standby time with accumulators. Furthermore Low Power is also used in high performance application to reduce power dissipation and accordlingly the demand for cooling (CPUs/GPUs)

Low power systems/circuit designs can affect the reliability of the integrated circuits. One typical example for these techniques are systems with ‘Sleep Transistors’. Fig. 14 helps to understand this approach. The schematic shows a block diagram of a test chip with several Low Power Techniques assembled together to evaluate the behavior of the different techniques. We focus here on the ‘Sleep Transistor’ approach which is based on leakage power control.

Fig. 14 Block diagram of a test chip for different Low Power Techniques. We focus the sleep transistor approach, which reduces power consumption by switching off complete circuit blocks from power supply. But Low Power techniques can also impact the circuit reliability.

A p-MOS connects the external VCC to supply rails (Virtual VCC), or an nMOS connects the external ground VSS to the ground rail (Virtual VSS). These sleep transistors are distributed throughout the layout. The area overhead is about 3%-6%. A control block switches the sleep transistors and watches clock.

When idle mode is entered the sleep transistors turned off and VCC are no longer connected to external VCC. Whereas idle blocks dissipate no power other circuit blocks are still working without restrictions. This can impact the circuit reliability of whole system. The Operation times of different blocks varies, this leads to various stages of parameter degradation. The propagation delay within the different can vary, due to different operation (stress) time. This can have an impact on timing between the different circuit blocks. On the other hand degraded circuit blocks get the opportunity for parameter recovery already discussed in the NBTI recovery chapter.

Block Block Block

A B C

VCC

VSS

Block Block Block

A B C

VCC

VSS

Fig. 15: Sketched block diagram of the Sleep Transistor Low Power Technique. When idle mode is entered the sleep transistors turned off and VCC are no longer connected to external VCC. Whereas idle blocks dissipate no power other circuit blocks are still working without restrictions.

APPROACHES FOR DESIGN FOR RELIABILITY In the following the function of Aging Simulators will be briefly

introduced. The typical flow of circuit simulation will be discussed and a simple example for circuit design optimization will be given. Furthermore constraints for semi-custom design will be evaluated.

Since process evolution will lead to higher device stress and reliability safety margins decrease in modern technologies, circuit reliability is not longer a task only for technology development but also for circuit designers.

fresh 10y1y

200 ps

Fig. 16: Example for a output signal of a example circuit by an aging simulator. The output signal can be plotted and compared before and after given operation times.

Fig. 16. Block diagram of a test chip for different Low PowerTechniques. We focus the sleep transistor approach, which reducespower consumption by switching off complete circuit blocks frompower supply. But Low Power techniques can also impact the cir-cuit reliability.

However, high values of gate-to-channel or gate-to-bulk/well voltage can occur in the case of M4, M5, and M8 according to the values of the subthreshold currents of M1, M6, and M7 and possible further leakage paths. If in addition high temperature is applied to the circuit (e.g. provided by the environment) NBTI conditions can occur. To evaluate the effect of NBTI applied to the input devices M4 and M5 under active mode operation conditions, we must consider that a defined (fixed) current is forced through these transistors by current source transistor M1.

Therefore, M4 and M5 are operated with approximately the same drain current before and after stress. Thus the device degradation must be compensated by an increase of the absolute value of the gate-to-source voltage. Asymmetric operation of the input branches of the circuit in Fig. 13 or asymmetric degradation of the input devices under symmetrical stress conditions thus leads to a stress-induced offset voltage of the circuit which equals the difference of the stress-induced threshold voltage degradations of the input devices.

LOW POWER TECHNIQUES In the following Low Power Techniques and their possible impact

on device reliability is discussed. LP techniques are used in circuits for modern portable applications like PDAs, mobile phones, etc. to increase to standby time with accumulators. Furthermore Low Power is also used in high performance application to reduce power dissipation and accordlingly the demand for cooling (CPUs/GPUs)

Low power systems/circuit designs can affect the reliability of the integrated circuits. One typical example for these techniques are systems with ‘Sleep Transistors’. Fig. 14 helps to understand this approach. The schematic shows a block diagram of a test chip with several Low Power Techniques assembled together to evaluate the behavior of the different techniques. We focus here on the ‘Sleep Transistor’ approach which is based on leakage power control.

Fig. 14 Block diagram of a test chip for different Low Power Techniques. We focus the sleep transistor approach, which reduces power consumption by switching off complete circuit blocks from power supply. But Low Power techniques can also impact the circuit reliability.

A p-MOS connects the external VCC to supply rails (Virtual VCC), or an nMOS connects the external ground VSS to the ground rail (Virtual VSS). These sleep transistors are distributed throughout the layout. The area overhead is about 3%-6%. A control block switches the sleep transistors and watches clock.

When idle mode is entered the sleep transistors turned off and VCC are no longer connected to external VCC. Whereas idle blocks dissipate no power other circuit blocks are still working without restrictions. This can impact the circuit reliability of whole system. The Operation times of different blocks varies, this leads to various stages of parameter degradation. The propagation delay within the different can vary, due to different operation (stress) time. This can have an impact on timing between the different circuit blocks. On the other hand degraded circuit blocks get the opportunity for parameter recovery already discussed in the NBTI recovery chapter.

Block Block Block

A B C

VCC

VSS

Block Block Block

A B C

VCC

VSS

Fig. 15: Sketched block diagram of the Sleep Transistor Low Power Technique. When idle mode is entered the sleep transistors turned off and VCC are no longer connected to external VCC. Whereas idle blocks dissipate no power other circuit blocks are still working without restrictions.

APPROACHES FOR DESIGN FOR RELIABILITY In the following the function of Aging Simulators will be briefly

introduced. The typical flow of circuit simulation will be discussed and a simple example for circuit design optimization will be given. Furthermore constraints for semi-custom design will be evaluated.

Since process evolution will lead to higher device stress and reliability safety margins decrease in modern technologies, circuit reliability is not longer a task only for technology development but also for circuit designers.

fresh 10y1y

200 ps

Fig. 16: Example for a output signal of a example circuit by an aging simulator. The output signal can be plotted and compared before and after given operation times.

Fig. 17.Sketched block diagram of the Sleep Transistor Low PowerTechnique. When idle mode is entered the sleep transistors turnedoff and VCC are no longer connected to external VCC. Whereasidle blocks dissipate no power other circuit blocks are still workingwithout restrictions.

3%–6%. A control block switches the sleep transistors andwatches clock.

When idle mode is entered the sleep transistors turned offand VCC are no longer connected to external VCC. Whereasidle blocks dissipate no power other circuit blocks are stillworking without restrictions. This can impact the circuit re-liability of whole system. The operation times of differentblocks varies, this leads to various stages of parameter degra-dation. The propagation delay within the different can vary,due to different operation (stress) time. This can have an im-pact on timing between the different circuit blocks. On the

However, high values of gate-to-channel or gate-to-bulk/well voltage can occur in the case of M4, M5, and M8 according to the values of the subthreshold currents of M1, M6, and M7 and possible further leakage paths. If in addition high temperature is applied to the circuit (e.g. provided by the environment) NBTI conditions can occur. To evaluate the effect of NBTI applied to the input devices M4 and M5 under active mode operation conditions, we must consider that a defined (fixed) current is forced through these transistors by current source transistor M1.

Therefore, M4 and M5 are operated with approximately the same drain current before and after stress. Thus the device degradation must be compensated by an increase of the absolute value of the gate-to-source voltage. Asymmetric operation of the input branches of the circuit in Fig. 13 or asymmetric degradation of the input devices under symmetrical stress conditions thus leads to a stress-induced offset voltage of the circuit which equals the difference of the stress-induced threshold voltage degradations of the input devices.

LOW POWER TECHNIQUES In the following Low Power Techniques and their possible impact

on device reliability is discussed. LP techniques are used in circuits for modern portable applications like PDAs, mobile phones, etc. to increase to standby time with accumulators. Furthermore Low Power is also used in high performance application to reduce power dissipation and accordlingly the demand for cooling (CPUs/GPUs)

Low power systems/circuit designs can affect the reliability of the integrated circuits. One typical example for these techniques are systems with ‘Sleep Transistors’. Fig. 14 helps to understand this approach. The schematic shows a block diagram of a test chip with several Low Power Techniques assembled together to evaluate the behavior of the different techniques. We focus here on the ‘Sleep Transistor’ approach which is based on leakage power control.

Fig. 14 Block diagram of a test chip for different Low Power Techniques. We focus the sleep transistor approach, which reduces power consumption by switching off complete circuit blocks from power supply. But Low Power techniques can also impact the circuit reliability.

A p-MOS connects the external VCC to supply rails (Virtual VCC), or an nMOS connects the external ground VSS to the ground rail (Virtual VSS). These sleep transistors are distributed throughout the layout. The area overhead is about 3%-6%. A control block switches the sleep transistors and watches clock.

When idle mode is entered the sleep transistors turned off and VCC are no longer connected to external VCC. Whereas idle blocks dissipate no power other circuit blocks are still working without restrictions. This can impact the circuit reliability of whole system. The Operation times of different blocks varies, this leads to various stages of parameter degradation. The propagation delay within the different can vary, due to different operation (stress) time. This can have an impact on timing between the different circuit blocks. On the other hand degraded circuit blocks get the opportunity for parameter recovery already discussed in the NBTI recovery chapter.

Block Block Block

A B C

VCC

VSS

Block Block Block

A B C

VCC

VSS

Fig. 15: Sketched block diagram of the Sleep Transistor Low Power Technique. When idle mode is entered the sleep transistors turned off and VCC are no longer connected to external VCC. Whereas idle blocks dissipate no power other circuit blocks are still working without restrictions.

APPROACHES FOR DESIGN FOR RELIABILITY In the following the function of Aging Simulators will be briefly

introduced. The typical flow of circuit simulation will be discussed and a simple example for circuit design optimization will be given. Furthermore constraints for semi-custom design will be evaluated.

Since process evolution will lead to higher device stress and reliability safety margins decrease in modern technologies, circuit reliability is not longer a task only for technology development but also for circuit designers.

fresh 10y1y

200 ps

Fig. 16: Example for a output signal of a example circuit by an aging simulator. The output signal can be plotted and compared before and after given operation times.

Fig. 18. Example for a output signal of a example circuit by anaging simulator. The output signal can be plotted and comparedbefore and after given operation times.

other hand degraded circuit blocks get the opportunity for pa-rameter recovery as already discussed in the NBTI recoverychapter.

8 Approaches for design for reliability

In the following the function of Aging Simulators will bebriefly introduced. The typical flow of circuit simulation willbe discussed and a simple example for circuit design opti-mization will be given. Furthermore constraints for semi-custom design will be evaluated.

Since process evolution will lead to higher device stressand reliability safety margins decrease in modern technolo-gies, circuit reliability is not longer a task only for technologydevelopment but also for circuit designers.

For this work the designers have to be supported by smartsoftware tools with built-in reliability know how. Alreadyavailable are aging simulators for full-custom design. Thesetools are reasonable for relatively low numbers of transistors(analog/RF circuits). The circuit simulators with built-in re-liability can simulate entire circuit blocks. The parameterdegradation can be calculated individually for each device.The circuit designer can adjust the characteristic of each de-vice (e.g. geometry, type).

Afterwards the circuit can be simulated again and in itera-tion reliable solutions can be found. Figure 18 shows an ex-ample for a circuit simulation with an aging circuit softwaretool. The output signal can be plotted after a given operationtime. The designer can check whether the results achieve therequirements.

The goal of circuit aging simulators is to describe thechange of the transistor model (e.g. BSIM) due to de-vice degradation as a function of age. The information ofthe deviation of a parameter as function of age is required[1BSIM-Par=f(age)]. Different degradation effects have to

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C. Schlunder: Device reliability challenges for modern semiconductor circuit design 209

Vd

Id

Vd

Id

Fig. 17: Output characteristic of a MOS transistor before and after stress. An aging simulator simulate this degradation for every device in a circuit

For this work the designers have to be supported by smart software

tools with built-in reliability know how. Already available are aging simulators for full-custom design. These tools are reasonable for relatively low numbers of transistors (analog / RF circuits). The circuit simulators with built-in reliability can simulate entire circuit blocks. The parameter degradation can be calculated individually for each device. The circuit designer can adjust the characteristic of each device (e.g. geometry, type).

Fig. 18: Circuit simulation flow. The reliability simulation has to be integrated in the design flow

Afterwards the circuit can be simulated again and in iteration reliable solutions can be found. Fig. 16 shows an example for a circuit simulation with an aging circuit software tool. The output signal can be plotted after a given operation time. The designer can check whether the results achieve the requirements.

The goal of circuit aging simulators is to describe the change of the transistor model (e.g. BSIM) due to device degradation as a function of age. The information of the deviation of a parameter as function of age is required [∆BSIM-Par = f(age)]. Different degradation effects have to be taken into account (typically HCS and NBTI). In Fig. 17 an output characteristic of a virgin device is compared with simulated degraded device.

Fig. 18 shows the sketched simulation flow. The reliability simulation has to be integrated in the design flow. Based on a large number of stress experiments with various stress- and characterization operation points degradation models can be fitted to the real degradation behavior of the device of the used technology.

The virgin circuit can be simulated based on standard device parameters (e.g. BSIM). Besides the simulation of the circuit function without stress, the tool extracts the duty cycle for each device within the circuit. A suitable input pattern stimulates the circuit function and all different operation points during operation are integrated by the simulator. In this manner the tool collects the aging of each device. Based on the fitted degradation model the aging simulator creates a new model card for each device. After this step a new flat netlist with individual degraded model cards or subcircuit substituions is available.

This netlist describes the circuit after stress. A new simulation of this aged circuit can be done and can be compared with the first simulation of the fresh circuits. The designer can check if the result achieve the requirement and can improve the circuit if necessary.

Fig. 19 shows an example for Design for Reliability [26]. The gates of the critical input devices M4/M5 of the already discussed operational amplifier are connected to VDD via additional transistors M14/M15. The gate and all other terminals are pulled to the same potential. Thus high electrical gate oxide fields during power down mode are avoided. No NBTI stress occurs, the device parameters do not degrade. The necessary enable signal is already available to select the power down ode. Since the additional devices have to balance only leakage currents, the devices lead to an only small additional area demand.

IN -

IN +

M1

M4

M5

M6 M7

M15M14ENABLE

active mode power-down mode

VDD

VSS

ENABLE SIGNAL :

Fig. 19: Example for Design for reliability: The critical input transistors M4 and M5 are protected against NBTI stress during the ‘Power Down Mode’.

Fig. 19. Output characteristic of a MOS transistor before and af-ter stress. An aging simulator simulate this degradation for everydevice in a circuit.

be taken into account (typically HCS and NBTI). In Fig. 19an output characteristic of a virgin device is compared withsimulated degraded device.

Figure 20 shows the sketched simulation flow. The re-liability simulation has to be integrated in the design flow.Based on a large number of stress experiments with vari-ous stress- and characterization operation points degradationmodels can be fitted to the real degradation behavior of thedevice of the used technology.

The virgin circuit can be simulated based on standard de-vice parameters (e.g. BSIM). Besides the simulation of thecircuit function without stress, the tool extracts the duty cy-cle for each device within the circuit. A suitable input pat-tern stimulates the circuit function and all different operationpoints during operation are integrated by the simulator. Inthis manner the tool collects the aging of each device. Basedon the fitted degradation model the aging simulator createsa new model card for each device. After this step a newflat netlist with individual degraded model cards or subcir-cuit substituions is available.

This netlist describes the circuit after stress. A new simu-lation of this aged circuit can be done and can be comparedwith the first simulation of the fresh circuits. The designercan check if the result achieve the requirement and can im-prove the circuit if necessary.

Figure 21 shows an example for Design for Reliability(Thewes et al., 2001). The gates of the critical input de-vices M4/M5 of the already discussed operational amplifier(chapter 6) are connected toVDD via additional transistorsM14/M15. The gate and all other terminals are pulled to thesame potential. Thus high electrical gate oxide fields duringpower down mode are avoided. No NBTI stress occurs, thedevice parameters do not degrade. The necessary enable sig-nal is already available to select the power down mode. Sincethe additional devices have to balance only leakage currents,the inserted devices lead to an only small additional area de-mand.

Vd

Id

Vd

Id

Fig. 17: Output characteristic of a MOS transistor before and after stress. An aging simulator simulate this degradation for every device in a circuit

For this work the designers have to be supported by smart software

tools with built-in reliability know how. Already available are aging simulators for full-custom design. These tools are reasonable for relatively low numbers of transistors (analog / RF circuits). The circuit simulators with built-in reliability can simulate entire circuit blocks. The parameter degradation can be calculated individually for each device. The circuit designer can adjust the characteristic of each device (e.g. geometry, type).

Fig. 18: Circuit simulation flow. The reliability simulation has to be integrated in the design flow

Afterwards the circuit can be simulated again and in iteration reliable solutions can be found. Fig. 16 shows an example for a circuit simulation with an aging circuit software tool. The output signal can be plotted after a given operation time. The designer can check whether the results achieve the requirements.

The goal of circuit aging simulators is to describe the change of the transistor model (e.g. BSIM) due to device degradation as a function of age. The information of the deviation of a parameter as function of age is required [∆BSIM-Par = f(age)]. Different degradation effects have to be taken into account (typically HCS and NBTI). In Fig. 17 an output characteristic of a virgin device is compared with simulated degraded device.

Fig. 18 shows the sketched simulation flow. The reliability simulation has to be integrated in the design flow. Based on a large number of stress experiments with various stress- and characterization operation points degradation models can be fitted to the real degradation behavior of the device of the used technology.

The virgin circuit can be simulated based on standard device parameters (e.g. BSIM). Besides the simulation of the circuit function without stress, the tool extracts the duty cycle for each device within the circuit. A suitable input pattern stimulates the circuit function and all different operation points during operation are integrated by the simulator. In this manner the tool collects the aging of each device. Based on the fitted degradation model the aging simulator creates a new model card for each device. After this step a new flat netlist with individual degraded model cards or subcircuit substituions is available.

This netlist describes the circuit after stress. A new simulation of this aged circuit can be done and can be compared with the first simulation of the fresh circuits. The designer can check if the result achieve the requirement and can improve the circuit if necessary.

Fig. 19 shows an example for Design for Reliability [26]. The gates of the critical input devices M4/M5 of the already discussed operational amplifier are connected to VDD via additional transistors M14/M15. The gate and all other terminals are pulled to the same potential. Thus high electrical gate oxide fields during power down mode are avoided. No NBTI stress occurs, the device parameters do not degrade. The necessary enable signal is already available to select the power down ode. Since the additional devices have to balance only leakage currents, the devices lead to an only small additional area demand.

IN -

IN +

M1

M4

M5

M6 M7

M15M14ENABLE

active mode power-down mode

VDD

VSS

ENABLE SIGNAL :

Fig. 19: Example for Design for reliability: The critical input transistors M4 and M5 are protected against NBTI stress during the ‘Power Down Mode’.

Fig. 20. Circuit simulation flow. The reliability simulation has tobe integrated in the design flow.

Vd

Id

Vd

Id

Fig. 17: Output characteristic of a MOS transistor before and after stress. An aging simulator simulate this degradation for every device in a circuit

For this work the designers have to be supported by smart software

tools with built-in reliability know how. Already available are aging simulators for full-custom design. These tools are reasonable for relatively low numbers of transistors (analog / RF circuits). The circuit simulators with built-in reliability can simulate entire circuit blocks. The parameter degradation can be calculated individually for each device. The circuit designer can adjust the characteristic of each device (e.g. geometry, type).

Fig. 18: Circuit simulation flow. The reliability simulation has to be integrated in the design flow

Afterwards the circuit can be simulated again and in iteration reliable solutions can be found. Fig. 16 shows an example for a circuit simulation with an aging circuit software tool. The output signal can be plotted after a given operation time. The designer can check whether the results achieve the requirements.

The goal of circuit aging simulators is to describe the change of the transistor model (e.g. BSIM) due to device degradation as a function of age. The information of the deviation of a parameter as function of age is required [∆BSIM-Par = f(age)]. Different degradation effects have to be taken into account (typically HCS and NBTI). In Fig. 17 an output characteristic of a virgin device is compared with simulated degraded device.

Fig. 18 shows the sketched simulation flow. The reliability simulation has to be integrated in the design flow. Based on a large number of stress experiments with various stress- and characterization operation points degradation models can be fitted to the real degradation behavior of the device of the used technology.

The virgin circuit can be simulated based on standard device parameters (e.g. BSIM). Besides the simulation of the circuit function without stress, the tool extracts the duty cycle for each device within the circuit. A suitable input pattern stimulates the circuit function and all different operation points during operation are integrated by the simulator. In this manner the tool collects the aging of each device. Based on the fitted degradation model the aging simulator creates a new model card for each device. After this step a new flat netlist with individual degraded model cards or subcircuit substituions is available.

This netlist describes the circuit after stress. A new simulation of this aged circuit can be done and can be compared with the first simulation of the fresh circuits. The designer can check if the result achieve the requirement and can improve the circuit if necessary.

Fig. 19 shows an example for Design for Reliability [26]. The gates of the critical input devices M4/M5 of the already discussed operational amplifier are connected to VDD via additional transistors M14/M15. The gate and all other terminals are pulled to the same potential. Thus high electrical gate oxide fields during power down mode are avoided. No NBTI stress occurs, the device parameters do not degrade. The necessary enable signal is already available to select the power down ode. Since the additional devices have to balance only leakage currents, the devices lead to an only small additional area demand.

IN -

IN +

M1

M4

M5

M6 M7

M15M14ENABLE

active mode power-down mode

VDD

VSS

ENABLE SIGNAL :

Fig. 19: Example for Design for reliability: The critical input transistors M4 and M5 are protected against NBTI stress during the ‘Power Down Mode’.

Fig. 21. Example for Design for Reliability: the critical input tran-sistors M4 and M5 are protected against NBTI stress during the“Power Down Mode”.

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210 C. Schlunder: Device reliability challenges for modern semiconductor circuit design

CONSTRAINTS FOR SEMI-CUSTOM DESIGN For digital application a more automated design approach is used.

The library elements are placed automatically by the design tool. The designers do not know in advance where a single element is placed. They have no direct access to the single devices. Therefore automated design environments make it difficult to manually determine reasonable operation conditions for single library elements.

A single library element is used in many different subcircuits, and within, exposed to a lot of different applications/operation conditions. For all of these combinations a delay-calculation would be necessary, since digital design is delay driven. Therefore, in semi-custom design a completely different approach is necessary. A possible consideration of reliability in semi-custom designs is the calculation of parameter degradation as a part of on-chip-variations. Stress induced parameter variation can be transformed in propagation-delays [30].

Fig. 20: Critical time path of a semi-custom design (e.g. base band chip). Since the designers do not have a direct access to single devices within the design tool, a smart approach is necessary to implement reliability checks into the design flow.

Smart software tools can check time paths within the product. In

the case of time conflicts, gates can be replaced by faster ones. On the other hand the tools have to take area demand and power consumption into account.

The tool can select one of several different versions of gates with the same function (e.g. XOR). The tool decision for substitution is based on

• Performance requirements • Stability against process variations • Stability against degradation • Area demand • Power consumption

The different demands have to be weighted. This is very difficult

for the tool and therefore a key factor of the software tool. After replacement of gates the simulator checks the critical time paths. If necessary further gate will be replaced until every degradation induced time conflict is solved.

SUMMARY This paper gives an overview of device degradation challenges of

semiconductor circuit design. The most critical device degradation mechanisms NBTI and HCS were described. Furthermore critical device stress conditions in circuits of digital / mixed signal applications and low power techniques were highlighted

Since process evolution will lead to higher device stress and reliability safety margins decrease in modern technologies, circuit reliability is not longer a task only for technology development but also for circuit designers. It is a common challenge. Aging/reliability simulators can help to optimize the circuits and save costs. The designer can consider reliability aspects early in the design phase and can develop reliable and competitive products.

The different requirements and constraints of “Design for Reliability” for full custom and semi-custom design were pointed out. For full-custom design capable aging simulators are already available. The function and integration into the design were briefly discussed. For semi-custom design a different approach is required. By transferring device degradation into a shift of the propagation delay of basic gate elements ‘Design for Reliability’ can be integrated into semi-custom design flows. Smart software tools can check time critical paths after simulated aging and ensures the circuit function for the entire required lifetime.

REFERENCES

[1] C. Schlünder, Tutorial, IRPS 2005 [2] C. Schlünder, Tutorial, IRPS 2007 [3] A. Martin, JVST B 2009 [4] A. Martin et al., Micr. Rel. 2004. [5] Hu et al., J. of S.S. Circ. 1985 [6] G. LaRosa et al., IRPS 1997 [7] R. Thewes et al, IRPS 1999 [8] Y.Y.Chen et al., VLSI 1999 [9] M.F. Lu et al., IRPS 2004 [10] A. Bravaix et al., IRPS 2009 [11] Jeppson et al., J.Appl.Phys.1977 [12] C. Schlünder et al. ESREF 1999 [13] A.T. Krishnan et al., IEDM 2003 [14] S. Rangan et al., IEDM 2003 [15] H. Reisinger et al., IRPS 2006 [16] J.P.Campbell et al. IRPS 2006 [17] H. Reisinger et al., TDMR 2007 [18] T. Grasser et al., IRSP 2007 [19] H. Reisinger et al., TDMR 2007 II [20] C. Schlünder et al. IRPS 2008 [21] T. Grasser et al., IRW 2008 [22] V. Reddy et al., IRPS 2002 [23] G. LaRosa et al., IRPS 2006 [24] J. Chung et al., IEDM 1990 [25] R. Thewes et al. IEDM 1999 [26] R. Thewes et al. ESDERC 2001 [27] C. Schlünder et al., IRPS 2003 [28] P. Chaparala et al., P2ID 2003 [29] C. Schlünder et al. Micro. Rel. 2005 [30] T. Pompl et al., DAC 2006

Fig. 22. Critical time path of a semi-custom design (e.g. base bandchip). Since the designers do not have a direct access to single de-vices within the design tool, a smart approach is necessary to im-plement reliability checks into the design flow.

9 Constraints for semi-custom design

For digital application a more automated design approach isused. The library elements are placed automatically by thedesign tool. The designers do not know in advance where asingle element is placed. They have no direct access to thesingle devices. Therefore automated design environmentsmake it difficult to manually determine reasonable operationconditions for single library elements.

A single library element is used in many different sub-circuits, and within, exposed to a lot of different applica-tions/operation conditions. For all of these combinations adelay-calculation would be necessary, since digital designis delay driven. Therefore, in semi-custom design a com-pletely different approach is necessary. A possible consid-eration of reliability in semi-custom designs is the calcula-tion of parameter degradation as a part of on-chip-variations.Stress induced parameter variation can be transformed inpropagation-delays (Pompl et al., 2006).

Smart software tools can check time paths within the prod-uct. In the case of time conflicts, gates can be replaced byfaster ones. On the other hand the tools have to take areademand and power consumption into account.

The tool can select one of several different versions ofgates with the same function (e.g. XOR). The tool decisionfor substitution is based on

– performance requirements

– stability against process variations

– stability against degradation

– area demand

– power consumption

The different demands have to be weighted. This is verydifficult for the tool and therefore a key factor of the soft-ware tool. After replacement of gates the simulator checks

the critical time paths again. If necessary further gate willbe replaced until every degradation induced time conflict issolved.

10 Summary

This paper gives an overview of device degradation chal-lenges of semiconductor circuit design. The most criticaldevice degradation mechanisms NBTI and HCS were de-scribed. Furthermore critical device stress conditions in cir-cuits of digital/mixed signal applications and low power tech-niques were highlighted.

Since process evolution will lead to higher device stressand reliability safety margins decrease in modern technolo-gies, circuit reliability is not longer a task only for technologydevelopment but also for circuit designers. It is a commonchallenge. Aging/reliability simulators can help to optimizethe circuits and save costs. The designer can consider re-liability aspects early in the design phase and can developreliable and competitive products.

The different requirements and constraints of “Design forReliability” for full custom and semi-custom design werepointed out. For full-custom design capable aging simula-tors are already available. The function and integration intothe design were briefly discussed. For semi-custom design adifferent approach is required. By transferring device degra-dation into a shift of the propagation delay of basic gate el-ements “Design for Reliability” can be integrated into semi-custom design flows. Smart software tools can check timecritical paths after simulated aging and ensures the circuitfunction for the entire required lifetime.

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