DEVICE MODELLING OF ARCHIMEDEAN SPIRAL GRAPHENE

NANOSCROLL FIELD-EFFECT-TRANSISTOR

MUHAMMAD AFIQ NURUDIN BIN HAMZAH

A thesis submitted in fulfilment of the

requirements for the award of the degree of

Master of Engineering (Electrical)

Faculty of Electrical Engineering

Universiti Teknologi Malaysia

MARCH 2014

iii

DEDICATION

To my family, near and far

iv

ACKNOWLEDGEMENT

I would like to express my deepest appreciation to all of those who has given

me the support in completing this thesis. A special gratitude I give to my supervisor

Prof. Dr. Razali Ismail for providing all the conveniences and support. Not to forget

to my former supervisor and mentor, Dr. Mohammad Taghi Ahmadi for whom has

given with all the technical support and tutelage in managing my work.

Nonetheless, I would also like to acknowledge with much gratitude the

crucial role of Dr. Michael Loong Peng Tan for all his valuable advice and idea that

has inevitably improved my work. This as well goes to Zaharah Johari, Aziziah Md.

Amin, Fatimah Abdul Hamid and all members of CoNE group for all their support in

completing this dissertation.

Million thanks for my family, especially to my parents, for all their

understandings and emotional supports for giving me the encouragement to go forth

in my career and life.

Last but not least, many thanks go to the Ministry of Higher Education

(MOHE) for their financial support and Research Management Centre (RMC) of

Universiti Teknologi Malaysia (UTM) for the research grant and the opportunity for

being here.

v

ABSTRACT

For the past decades, researchers indicate that persistent scaling of

conventional silicon Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

reaching its physical limit at 10nm, resulted in its performance degradation as the

search continues for a low-power and high speed, density and reliability devices. The

frailty due to the Short Channel Effects (SCE) has limited the device scaling. In

addition, the emergence of Carbon Nanotube (CNT) in the past two decades has

been a remarkable breakthrough in solving for transistor SCE; but there has also

been a problem in controlling its band gap energy. Graphene Nanoscroll (GNS) is

one of the carbon-based materials that inherit most likely similar electrical properties

as CNT. But GNS possesses an advantage to modulate its properties by varying its

carbon layer overlapping region owing to the open edge spiral, resulting in band gap

variations. This study is to investigate the GNS carrier statistic against its geometry

variation and its performance as a MOSFET. The carrier statistic such as the energy

band gap, density of states, carrier density and intrinsic velocity were modeled and

the results show strong relation to the overlapping region of GNS. The energy band

gap exhibits an inverse relation to the overlapping region and metallic properties was

restored when the overlap has reached certain limit. The carrier density also

increases with the overlapping region as a sign of gap narrowing. Moreover, the

intrinsic velocity increases with overlap region and remains constant as it reaches

graphene Fermi velocity, signifying ballistic transport near Fermi point. The charge

distribution in GNSFET was characterized based on the Landauer Buttiker’s

formalism. The output current shows good agreement with the experimental results

at constant conductance and GNS structural parameters. Furthermore, the GNSFET

demonstrated comparable performance to the CNTFET within ballistic limit. The

GNSFET was also benchmarked with the latest 22nm MOSFET technology, which

indicates faster switching capability due to enhancement in Subthreshold Swing (SS)

and Drain Induced Barrier Lowering (DIBL).

vi

ABSTRAK

Sejak beberapa dekad yang lalu, para pengkaji menyatakan pengecilan skala

bagi peranti Logam-Oksida-Semikonduktor Transistor Medan Elektrik (MOSFET)

secara berterusan hingga kepada had keupayaan fizikal panjang pengalir 10nm akan

menyebabkan kebolehupayaannya merosot akibat daripada Kesan Pengalir Pendek

(SCE). Kelangsungan kajian bagi menghasilkan peranti dengan penggunaan kuasa

yang rendah dan berkelajuan tinggi dilaksanakan. Kemunculan Carbon Nanotube

(CNT) dua dekad lalu didapati berupaya bagi menangani permasalahan ini; akan

tetapi, ia mempunyai kesukaran dalam mengawal lebar jalur tenaganya. Graphene

Nanoscroll (GNS) merupakan salah satu bahan berasaskan karbon yang mempunyai

ciri-ciri elektrik yang hampir sama seperti CNT dengan kebolehan untuk mengawal

jurang tenaganya melalui lapisan karbon yang bertindih, disebabkan oleh hujungnya

yang terbuka pada bahagian sebelah tepi. Tujuan kajian ini dijalankan adalah untuk

menyelidik statistik-pembawa GNS terhadap perubahan geometrinya dan

kebolehupayaan sebagai MOSFET. Model matematik diterbitkan bagi ciri-ciri

statistik cas pembawa seperti jurang tenaga, kadar ketumpatan keadaan kuantum,

ketumpatan cas pembawa dan halaju intrinsik cas pembawa yang dipengaruhi oleh

kawasan lapisan karbon yang bertindih. Kajian mendapati jurang tenaga berkadar

songsang dengan lapisan bertindih karbon dalam GNS dan bersifat konduktor

apabila penambahan lapisan bertindih mencapai had tertentu. Selain itu, halaju

intrinsik meningkat dengan lapisan bertindih dan menjadi tepu pada halaju Fermi

Graphene, menandakan pengangkutan balistik berhampiran titik Fermi. Pengagihan

cas dalam GNS dihitung berdasarkan Landauer Buttiker’s Formalism. Arus keluaran

yang dikira menunjukkan perbandingan yang baik dengan hasil eksperimen dan

prestasinya mampu menyaingi CNTFET dalam had balistik. Silikon MOSFET 22nm

digunakan sebagai penanda aras, di mana GNSFET mempunyai daya penukaran suis

lebih pantas serta meningkatkan Kecerunan Bawah-Ambang (SS) dan bagi

Halangan-Merendah Longkang-Teraruh (DIBL).

vii

TABLE OF CONTENTS

CHAPTER TITLE PAGE

DECLARATION ii

DEDICATION iii

ACKNOWLEDGEMENT iv

ABSTRACT v

ABSTRAK vi

TABLE OF CONTENTS vii

LIST OF TABLES x

LIST OF FIGURES xi

LIST OF ABBREVIATION xviii

LIST OF SYMBOLS xx

LIST OF APPENDICES xxiii

1 INTRODUCTION 1

1.1 Introduction 1

1.2 Problem Statement 4

1.3 Research Objectives 6

1.4 Research Scopes 7

1.5 Research Contributions 7

1.6 Thesis Outline 8

2 LITERATURE REVIEW 10

2.1 Introduction 10

2.2 Carbon-Based Technology 10

viii

2.2.1 Overview of Graphene and Carbon Nanotube

Physical Structure and Electronic Properties 11

2.2.2 Physical Structure and Electronic Properties of

Graphene Nanoscroll (GNS) 19

2.2.3 GNS Fabrication Synthesis 28

2.3 Graphene Nanoscroll Field-Effect-Transistor (GNSFET) 33

2.3.1 Schottky-Barrier (SB) CNTFET 33

2.3.2 Gate-All-Around (GAA) CNTFET 36

2.4 CNTFET Modelling 37

2.5 Summary 39

3 RESEARCH METHODOLOGY 41

3.1 Research Activities and Flowchart 41

3.2 Simulation and Comparison with Published Data 43

3.3 Benchmarking 46

3.4 Analysis 46

4 MODELLING OF THE GNSFET

4.1 Introduction 47

4.2 Basic Concepts 47

4.2.1 Fermi Distribution Function 48

4.2.2 Infinite Potential Square Well 50

4.2.3 Quantum Confinement 52

4.3 Graphene Nanoscroll (GNS) Energy Band Structure and

Density of States (DOS) Modelling 55

4.4 GNS Carrier Density 63

4.5 Electrostatic Capacitance 69

4.6 Quantum Capacitance 70

4.7 Device Modelling Approach 72

ix

4.7.1 Top-of-the-Barrier Model 72

4.7.2 Scaling of Resistance 80

4.8 Models Comparison 82

4.9 Device Benchmarking 88

4.10 Summary 95

5 CONCLUSION AND FUTURE WORKS 96

5.1 Summary and Conclusions 96

5.2 Contributions 98

5.3 Recommendations for Future Works 99

REFERENCES 101

Appendices A-C 108-113

x

LIST OF TABLES

TABLE NO. TITLE PAGE

1.1 ITRS 2011 guideline for long-term device scaling 3

2.1 Parameters list for CNT (Adapted from Saito et al., (1998)) 16

2.2 Structural parameters for initial and optimized GNS. is the

overlapping region length and in this table is the inner

diameter (adapted from Chen et al., (2007))

24

2.3 Highlighted some of the significance theoretical work of

numerical simulation on GNS physical structure.

27

2.4 Summarize the GNS synthesis with the advantages and

disadvantages.

32

2.5 Summarize the CNTFETs modelling. 38

4.1 Sub-band calculation for both ZGNS and ZCNT. Both value

of fitting parameter computed the same sub-band number

for ZGNS.

58

4.2 Intrinsic carrier density at T=300 K and inner radius,

by varying GNS diameter compared to ZCNT.

68

4.3 Comparison of the GNS and CNT MOSFET at ballistic limit

( )

86

4.4 Benchmarking with 22nm technology node PTM MOSFET

model.

90

xi

LIST OF FIGURES

FIGURE NO. TITLE PAGE

2.1 Shows some of the carbon-based structure which are (a)

graphene, (b) bucky-ball fullerene, (c) carbon nanotube

(CNT), (d) multi-walled carbon nanotube (MWNT) and

(e) carbon nanoscroll (CNS)

11

2.2 The 2D hexagonal graphene lattice in real space with

basis vector and . The unit cell consists of two

neighbouring carbon atom with carbon-carbon distance

is .

12

2.3 (a) Brillouin zone of a graphene sheet and (b) Wave

vectors at six corresponding Fermi points within the

Brillouin zone.

13

2.4 Illustration of the formation of CNT from a single

graphene sheet. The indicated the chirality vector,

which is the circumferential direction at CNT diameter

while is the translational vector along the cylindrical

tube. is the rolling angle of the CNT from the y-axis.

15

2.5 The formation of SWNT for each topology that signifies

by its chirality, and translational, vector

respectively.

16

2.6 (a) For semiconducting CNT, the defining parallel lines

do not pass through any of the Fermi points in the

graphene Brillouin zone while (b) Metallic CNT, the

17

xii

lines pass through the Fermi points (adapted from

Supriyo Datta (2005)).

2.7 The Archimedean-Type spiral of GNS. is the

number of turn, is the overlapping region, is the

inner radius and is the interlayer

distances that are experimentally obtained (Roy et al.,

2008). The inset expresses the 1D density of states

(DOS) that exhibited by GNS (adapted from Li et al.,

(2011)).

19

2.8 The net energy (y-axis) between elastic bending energy

and van der Waals interaction with the corresponding

sequence of GNS formation from 1 to 12 (adapted from

Braga et al., (2004)).

20

2.9 The absorption of methane molecule (red dot) by the

carbon atom of nanoscroll (blue dot) increases from (a)

to (c); where (a) interlayer distances, ,

(b) and (c) . (adapted

from Peng et al., (2010))

21

2.10 MDS results on (a) The energy band structure of ZGNS

from the left is (15,0) and (16,0) respectively. (b) The

energy band structure for AGNS from the left is (10,10)

and (11,11) respectively. (adapted from Chen et al.,

(2007))

22

2.11 The relation of band gap against its chirality. Both

fittings are able to predict for small band gap at (16,0)

and (19,0) as the MDS does. Fitting-I is 1.9242 and

Fitting-II is 2.2641. (adapted from Chen et al., (2007))

23

2.12 (a) The GNS back-gated transistor structure showing

that the current flows through the entire GNS layers

despite only the outer layer of CNT. (b) The I-V curve

25

xiii

for GNS back-gated device (adapted from Xie et al.,

(2009)).

2.13 The electrical conductance of GNS including the spin

degeneracy of 2 against the electrochemical potential

( ). (adapted from Li et al., (2012))

26

2.14 The chemical route process that exfoliate the graphite

sheet using the solution of potassium metal with ethanol

and sonication by applying high energy electrode on

samples to roll the exfoliate graphene. (adapted from

Viculis et al., (2003))

29

2.15 (a) The GNS is rolled due to strain endured by the

monolayer graphene after mechanical exfoliation. (b)

The image of GNS captured by transmission electron

microscopy (TEM) showing the interlayer spacing of

0.35nm.

29

2.16 Current transport comparison of an in situ growth (a)

nested MWNT and (b) GNS for inner diameters in the

range of 15 to 30nm and outer diameter between 30 to

65nm. The GNS capable of sustaining higher current

than the MWNT to about one order of magnitude.

(adapted from Schaper et al., (2011))

31

2.17 The CNTFETs structure table for SWNT. 33

2.18 Metal contact of SB-CNTFET (adapted from Xu et al.

(2013)).

34

2.19 Ambipolar transport condition in SB-CNTFET (adapted

from Lundstrom & Guo (2006)).

34

2.20 The n-type CNTFET with Potassium doping (adapted

from Javey et al., (2005)).

35

xiv

2.21 The fully self-aligned n-type CNTFET fabrication step.

(adapted from Franklin et al., (2012))

37

3.1 Research flowchart for GNSFET modelling and

analysis.

42

3.2 MATLAB simulation algorithm for computing

GNSFET current characteristic.

45

4.1 The Fermi-Dirac distribution as a function of energy at

different temperature.

48

4.2 The energy band diagram of a degenerate and non-

degenerate regime of a semiconductor.

50

4.3 The infinite potential well consisting of the wave

function, indicating the probability function of

Region II is one whereas Region I and III is zero.

50

4.4 The panicle of potential well. (a) Four lowest discrete

energy levels in an infinite potential well. (b)

Corresponding wave function till forth harmonic and (c)

Corresponding probability functions.

52

4.5 The confined silicon structures comparing their axes

length to the silicon De-Broglie’s wavelength,

(Lundstrom & Guo, 2006).

53

4.6 The DOS at different semiconductor dimension (adapted

from Kushwaha (2001)).

54

4.7 The energy band gap fits perfectly well with Chen et al.,

(2007) NNTB results for fitting 1, . and fitting

2, .

56

4.8 Energy band gap for both ZCNT and ZGNS against

chirality (n,0) with increment step of 1.

57

xv

4.9 The band gap energy of ZGNS against the spiral length

for both fitting, and the energy gap for ZCNT in

correspond to its circumference length. The black and

pink square notation indicates the band gap energy

against its chirality from (11,0) to (23,0) for each ZGNS

and ZCNT respectively.

60

4.10 The energy band gap against ZGNS overlapping region

for each from 0.2 to 0.8 with 0.2 step

increment. The pink line shows the direct dependency of

the band gap against .

61

4.11 Comparison of DOS for both semiconducting (16,0)

ZCNT and semi-metallic (16,0) ZGNS.

63

4.12 Carrier densities for ZGNS and the approximation at

degenerate and non-degenerate regime.

65

4.13 The intrinsic carrier density against temperature for

different . The inner radius, and the

is increased from 1.1 to 2 with 0.3 steps of

increment.

67

4.14 The intrinsic carrier density of GNS indicated higher

exponential increment compared to the CNT and the

inset showed their corresponding band gap energy.

69

4.15 The quantum capacitance as a function of Fermi energy

shows significant reduction of the first sub-band optical

excitation peak by the increment of . (

)

71

4.16 The basic concept for the ballistic nanotransistor which

was proposed by (Rahman, Jing, Datta, & Lundstrom,

2003). The self-consistent potential, is the charge

in the channel controlled by electrostatic potential at

72

xvi

four terminal (gate, drain, source and substrate).

4.17 The MOSFET-like structure of the GNSFET. 73

4.18 (a) The carrier population (blue dot) in k-states at

equilibrium ( ). (b) The carrier population in non-

equilibrium ( ).

74

4.19 The intrinsic velocity as a function of carrier density for

from 1 to 5 turns with 2 steps increment.

78

4.20 The schematic model of a GNSFET with channel

resistance, and contact resistance,

(consisting of quantum resistance, and non-

transparent resistance, ).

81

4.21 Comparison between simulated GNSFET at

and the experimental results at (Schaper et

al., 2011) for , and . Inset

shows simulation result tends to saturate.

83

4.22 The output characteristic for both CNTFET (red dashed

line) and GNSFET (blue dashed line) at a ballistic limit

with perfect contact ( ) in which the is varied

from 0 to 1 V with 0.1 V increment. Inset shows the

output current against at .

85

4.23 The total gate capacitance of the CNTFET is slightly

higher than the GNSFET at for HfO2

insulator. The inset indicated direct relation ( )

of the electrostatic capacitance, of GNSFET against

the outermost radius using HfO2.

87

4.24 The I-V characteristic of the GNSFET and the Si

MOSFET (inset) in delivering the same current strength

of . The diamond line is experimental CNTFET

(Javey et al., 2005).

89

xvii

4.25 (a) The gate capacitance and (b) injection velocity,

of the n-type GNSFET at different dielectric constant

and as the usage of the HfO2 increases both

parameters.

91

4.26 The ratio, DIBL and SS against as the

number of radius is increased. (a) The and (b)

DIBL are barely improved as the is increased. (c)

The SS indicates a slight improvement with increased

.

94

xviii

LIST OF ABBREVIATION

ACNT - Armchair carbon nanotube

AGNS - Armchair graphene nanoscroll

ALD - Atomic Layer Deposition

BTBT - Band-to-Band-Tunnelling

CVD - Chemical Vapour Deposition

CNT - Carbon nanotube

CNS - Carbon nanoscroll

CNTFET - Carbon nanotube Field-Effect-Transistor

DOS - Density of States

DIBL - Drain Induced Barrier Lowering

EBL - Electron-beam Lithography

GNSFET - Graphene nanoscroll Field-Effect-Transistor

GNR - Graphene nanoribbon

GAA - Gate-All-Around

gcd - Greatest common divisor

IPA - Isopropyl Alcohol

IBM - International Bussiness Machine

ITRS - International Technology Roadmap for Semiconductor

IC - Integrated Circuit

MOSFET - Metal-Oxide-Semiconductor Field-Effect-Transistor

MFP - Mean free path

MDS - Molecular Dynamic Simulation

MWNT - Multi-walled carbon nanotube

NNTB - Nearest Neighbour Tight Binding

NEGF - Non-equilibrium Green’s Function

xix

PTM - Predictive Technology Model

SB - Schottky-Barrier

SOI - Silicon-on-Insulator

SiP - System-in-Package

SS - Sub-threshold Swing

SWNT - Single-walled carbon nanotube

TEM - Thermionic Emission Microscope

VDW - Van der Waals interaction

ZCNT - Zig-zag carbon nanotube

ZGNS - Zig-zag graphene nanoscroll

1D - One-dimensional

2D - Two-dimensional

3D - Three-dimensional

xx

LIST OF SYMBOLS

- On-current

- Conduction band

- Valence band

- Fermi level

, - Carbon lattice basis vector

- Carbon-carbon bond distances

- Carbon-carbon bonding energy

- Chirality vector

- Translational vector

- Rolling angle

- CNT circumferential length

- Diameter

- Number of hexagons in the nanotube unit cell

- Momentum k-space quantized vector

, - Defining parallel line

- Number of Sub-bands

- GNS number of turns

- GNS inner radius

- GNS interlayer distance

- GNS radius

- GNS spiral length

- Inner diameter

- Overlapping region

- Conductance

xxi

- Numbers of contributing channel

- Transmission probability

- , Quantum conductance

- Planck’s constant

- C, Electron charge

- Fermi’s distribution function

- , Boltzmann’s

constant

- , Modified Planck’s constant

- Effective mass

- De-Broglie wavelength

- Potential energy

- Confining energy

- GNS band gap energy

- Carrier density

- GNS Effective density of states

- Intrinsic Fermi level

- Intrinsic carrier density

- Electrostatic capacitance

- Quantum capacitance

- Gate capacitance

- , Vacuum

permittivity

- Dielectric constant

- Substrate capacitance

- Self-consistent potential

- Drain capacitance

- Source capacitance

- Gate fitting parameter

- Drain fitting parameter

- Fermi-Dirac Integral

xxii

- Intrinsic velocity

- , Fermi velocity

- ON-conductance

- Contact resistance

- Channel resistance

- Non-transparent resistance

- Quantum resistance

- On-resistance

- , electron mass

- Transconductance

- Injection velocity

- Off-current

xxiii

LIST OF APPENDICES

APPENDIX TITLE PAGE

A Graphene Nanoscroll Carrier Statistic 108

B Gamma Function 111

C Publications List 112

CHAPTER 1

INTRODUCTION

1.1 Introduction

It is well-known that transistor has become the most essential portion in the

growth of such advanced technology nowadays, owing to its extensive usage during

the 80s. The Moore’s Law has been the guideline in device scaling for decades,

which indicates that the density of the transistor is doubly increased in one and a half

years and the size of a transistor is doubly decreased within 3 years. The

International Business Machine (IBM) corporation has set the standard in device

scaling that has constant electric field by a scaling factor of or the so called

Dennard’s scaling law for a conventional planar Metal-Oxide-Semiconductor Field-

Effect-Transistor (MOSFET), which has led to a high processing compact system

(Dennard et al., 2007).

However, in 2001, the classical scaling law based on a constant-filed scaling

has come to a limit where it failed to scale certain parameter such as the threshold

voltage, power consumption and sub-threshold current due to increase of electric

fields as device dimension shrunk and put the Moore’s Postulate into halt (Kuhn,

2009). This scaling limit has been underlined by the International Technology

Roadmap for Semiconductor (ITRS) as the horizon of the classical Dennard’s

Scaling Law of the planar MOSFET (Kuhn, 2009).

2

Throughout the years, scientist and researchers have enhanced transistor

capability to substantiate the continuation of Moore’s Law and today they are able to

adapt and downscale the transistor dimension beyond 130nm technology node that is

known as the horizon of Dennard’s classical scaling. In other words, we have entered

the age of “post-CMOS classical scaling law” (ITRS, 0 ). In this perspective, we

had witnessed the employment of nanoscale technology instead of microelectronic

for a high processing device. Subsequently, within the next decade, the possibility of

manufacturing technology of less than 10nm node can be succeeded. Due to fast

advancing technology, the industry is demanding more efficient device with smaller

dimension, low power consumption and reduced leakage current of an integrated

circuit (IC). Therefore, device diversification has been applied to compensate the

size of the circuitry and have multiple functions within a System-in-Package (SiP).

Device miniaturization is also one of the methods, by increasing the density of the

transistor within a single IC, which is commonly utilized to realize the Moore’s Law.

Table 1.1 is the guideline from ITRS in achieving device miniaturization for

higher device performance in the near future. It is the key challenge in device scaling

over the next 14 years listed by ITRS. ITRS has been very crucial in keeping the

long-term reliability of a device. Based on this table, one of the concerns has been

the reliability of novel devices, structures, and materials. Such material, for example

carbon-based material (carbon nanotube, graphene, carbon nanoscroll) has been

introduced for future applications. In order to understand the mechanism of these

novel materials, experimental and theoretical efforts have been done to investigate

their behaviour.

3

Table 1.1 : ITRS 2011 guideline for long-term device scaling.

Long-Term

2019-2026 Summary of Issues

Implementing of

advanced multi-

gate structures

Fabrication of advanced non-planar multi-gate MOSFET to

below 10nm gate length

Control of short-Channel effects

source/drain engineering to control parasitic resistance

Strain enhanced thermal velocity and quasi-ballistic

transport

Identification

and

implementation

of new memory

structure

Scaling storage capacitor for DRAM

DRAM and SRAM replacement solutions

Cost effective installation of high density 3-D NAND (512

Gb – 4 Tb)

Implementing non-charge-storage type of NVM cost

effectively

Low-cost, high-density, low-power, fast-latency memory

for large systems

Reliability of

novel devices,

structures, and

materials

Understand and control the failure mechanisms associated

with new materials and structures for both transistor and

interconnect

Shift to system level reliability perspective with unreliable

devices

Power scaling Vdd scaling

Controlling sub-threshold current or/and sub-threshold

slope

Margin issues for low Vdd

Integration for

functional

diversification

Integration of multiple functions onto Si CMOS platform

3-D integration

Due to the limitation of conventional silicon MOSFET, a new material which

is more reliable in replacing silicon as a semiconductor for sub-micron channel has

emerged. The carbon nanotube (CNT) has been eminently spoken of within the past

two decades. Even now, numerous researches on CNT application is still on-going,

owing to its remarkable electronic and mechanical properties. CNT was first

discovered in 1991 by Sumio Iijima at the NEC Fundamental Research Laboratory

in Tsukuba, Japan, and by Donald Bethune at IBM’s Almaden Research Centre in

California. Unfortunately, the fabrication process for a high-quality CNT with

controllable diameter to dictate the energy band gap is very difficult (ITRS, 2011).

4

On the contrary, in 2003, a group of scientist has come out with a novel

structure of graphene which is less expensive to produce (Braga et al., 2004). It is

called a carbon nanoscroll (CNS) (Viculis et al., 2003). CNS is a multilayer long

tubular structure much like CNT, however CNS has an open edge along the

translational axis. It is also described as the Archimedean type-spiral graphene due to

its novel spiral structure. By considering the quantum confinement effect, CNS that

has its diameter shrunk to a one dimensional (1D) structure is known as a graphene

nanoscroll (GNS). Thus, GNS can be suitable for nanoscale application such as

nanotransistor, and bio-sensoring devices. There have been very few researches

regarding GNS, especially in terms of their application. Furthermore, it is expected

that GNS inherits similar fundamental properties as CNT and graphene such as

ballistic transport properties due to its symmetrical band structure (Zhou et al., 2011)

long mean-free-path (MFP), and high mobility (Zheng et al., 2011). On the other

hand, the electronic transport of GNS is affected by the interlayer interaction

between inner and outer layer compared to the single-walled CNT; thereby, it is

expected that GNS will exhibit higher on-current, than the single-walled CNT for

the same diameter (Schaper et al., 2011).

In order to investigate the carrier statistic and the output performances of the

GNS, device modelling plays an important role in assessing those features.

Modelling provides an early approximation as to what the device performance would

deliver so that it can fit with the industrial demand. Therefore, accurate model with

necessary considerations is required to provide a close estimation with the real

device output.

1.2 Problem Statement

Further downscaling of the conventional planar MOSFET is not possible

when it comes to control the short channel effects. The high channel doping

MOSFET in obtaining an acceptable range of threshold voltage has resulted in band-

to-band tunnelling (BTBT) making it vulnerable to high current leakage, mobility

degradation, and severe threshold voltage roll-off due to high drain-induced barrier

5

lowering (DIBL), which is impractical for high performance application. Thus, the

conventional device modelling is no longer accurate due to the quantum effects in a

nanoscale device. In order to counter this problem, ITRS has introduced with the

reliability of novel devices, structures and materials as previously shown in Table

1.1.

CNTFET is one of the reliable novel devices that is capable of replacing the

conventional MOSFETs. Furthermore, the researches regarding CNT-based devices

have been widely conducted theoretically and experimentally. It has been the focus

for more than two decades, to bridge the knowledge gap between MOSFET

technologies into nanoscale carbon-based devices. Many researches, particularly in

CNTFET performance within the nanoscale regime are still on-going until today.

Even so, the limitations of the CNT have restricted its capability to certain extent as

highlighted by the ITRS 2011 in Emerging Research Materials report, which are:

1. The ability to control band gap energy.

2. Positioning of the nanotubes in required locations and directions.

3. Control of the number of nanotube walls.

4. Control of charge carrier type and concentration.

5. Deposition of a gate dielectric.

6. Formation of low resistance electrical contacts.

All of these constraints have been widely discussed in the previous

researches (Franklin et al., 2012; Chen et al., 2008; Zhang et al., 2007; Javey et al.,

2005), while GNS could offer another way in resolving some of these constraints as

to rectify the device performance and production, owing to its similarity in carrier

transport with CNT and less complex fabrication process compared to a high-quality

single-walled CNT. By using GNS, the overlapping region between the inner and the

outer layer can be tuned over a broad range of size and the number of walls can be

controlled; instead of closed tubular structure of CNT that limits its permeability

compared to the GNS. Therefore, GNS could provide a better control range of the

energy gap compared to its CNT counterpart due to the tuneable core size, which can

possibly be the key for constraint (1) and (3). The energy gap of the CNT is very

6

much influenced by its diameter and the problem would be to obtain a particular

diameter size for an acceptable range of energy gap. On the other hand, GNS offers a

better way in controlling the energy gap by tuning the overlapping regions of the

spiral structure.

The 1D GNS is expected to exhibit both CNT and graphene characteristics.

Besides its tuneable structure, GNS also exhibits some features that are related to its

precursor (CNT and graphene) such as the symmetrical band structure, high mobility

and ballistic transport, which will be thoroughly discussed in Chapter 2. Therefore, it

is expected that the GNS is capable to compete with CNTFET as future MOSFET

and to investigate the GNS potential as a nanotransistor within ballistic limit would

be worthwhile. Since GNS is a confined 1D structure, quantum mechanical effects

such as the quantum capacitance need to be considered in the modelling part due to

its significant effects when subject to bias voltage.

With regards to the limitation in MOSFET and CNT, and considering to the

performance expectation on GNS, the research problems can be summarized as

follows:

1. The constraint in nanoscale conventional silicon MOSFET and CNTFET.

2. The GNS geometry effects on its carrier statistic and electronic properties.

3. The 1D GNS Field–Effect-Transistor (GNSFET) device performances

compared to the CNTFET and the conventional silicon MOSFET.

1.3 Research Objectives

The followings are the objectives of this project:

1. To analytically model and investigate the 1D Archimedean type-spiral GNS

carrier statistics and electronic properties.

7

2. To assessed the performance between GNSFET and CNTFET devices for

high speed application.

3. To benchmark the GNSFET with the 22nm conventional silicon MOSFET.

1.4 Research Scopes

The scopes of this research cover the modelling of the carrier statistics and

the carrier transport for 1D GNS, including device performance analysis. A literature

review was performed to understand the physical overview of the 1D GNS referring

to its Archimedean spiral structure and the effect on its electronic properties.

Subsequently, by understanding these features, the dispersion relation to that

includes the concept of sub-band and the Archimedean spiral parameters is

modelled. This will become the contributing factors to other carrier statistic

parameters. As a sequence to these carrier statistics, ballistic carrier transport was

modelled by using the Landauer Buttiker’s expression. In this carrier transport

model, the non-ideality effect such as the non-ohmic contact was included to obtain

better comparison with experimental data and the phonon scattering effects were

excluded since very little attention has been given on GNS scattering. The GNSFET

was compared with the experimental data at high conductance and its performance

against CNTFET at a quantum conductance limit is assessed. Benchmarking was

also performed against the 22nm node technology MOSFET.

1.5 Research Contributions

CNTFET has been providing the scaling opportunity within the nanoscale

regime for MOSFET application. However, the emergence of GNS that offers more

flexibility in terms of energy band control and material production can contribute to

much better device scaling and fabrication.

8

In this research, the developed analytical model is based on the 1D quantum

confinement effect of the Fermi-Dirac distribution in computing the GNS carrier

statistics. The Archimedean type-spiral parameter was included in these models to

understand the geometry effects on its carrier statistic that associated with the mobile

charge; in order to provide the insight on its mobile charge carrier transport and its

performance through changing its spiral parameter. Comparison was made with the

experimental or published data to validate the modelling work that will help to

characterize and predict the charge behaviour in GNSFET.

Moreover, the preliminary analysis in this research could provide the

understanding of its ballistic carrier transport between both CNTFET and GNSFET.

In this context, the distinction between both structures that influence their device

performance was determined and further enhancement for GNSFET is discussed

based from previous researches in terms of the device structure. In addition, this

research also discussed the performance between GNSFET with the recent 22nm

MOSFET technology. The 22nm MOSFET technology has been made as the

standard benchmark for GNSFET, to justify the relevance of using GNSFET as the

nanotransistor. The performances and device enhancement for GNSFET are also

included in this discussion. Although this research only emphasizes on device level

analysis, it may still contribute by offering insight on the performance of GNSFET.

1.6 Thesis Outline

The introduction of this work is discussed in Chapter 1. It also includes the

guideline of the research which consists of the problem statement, the research

objective, the scope of the work, and the contributions of the research. Chapter 2 is a

broad overview about GNS that discusses the band structure of the GNS as the initial

step to understand the device properties through the application of the nearest

neighbour tight binding (NNTB) graphene model. Also, some description of the

GNS fabrication process and its electronic properties; and the modelling of the

carrier transport are briefly discussed. The methodology of this work is summarized

within Chapter 3, which explains the sequences of this work that also include the

9

simulation step. All the analysis and discussion regarding the performance of the

GNS are discussed in Chapter 4. Chapter 5 is the summarization of the research on

the capability of GNS as a future semiconductor channel and future recommendation

for research enhancement.

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