GUIDED BY: PREPARED BY:

Prof. R.G.PATEL Vijay Yadav (140403111014)

Ravi chaudhri(140403111016)

Sankalchand Patel collage of engineering

Subject: Embedded Systems Subject code:2171005

Device Drivers and interrupt service mechanism

Content

Interrupt.

ISR concept.

interrupt source.

interrupt servicing (handling )mechanism.

multiple interrupt.

Interrupt

Interrupt

An interrupt is a signal (an “interrupt request”) generated by some event external to the CPU

Causes CPU to stop currently executing code and jump to separate piece of code to deal with the event

Sometimes things will happen in a system when the processor is simply not ready. In fact, sometimes things change that require immediate attention.

Can you imagine, sitting at your PC, that you were to hit buttons on the keyboard, and nothing happens on your computer?

Maybe the processor was busy, and it just didnt check to see if you were hitting any buttons at that time

Types Of Interrupts

There are two types of interrupts.

Hardware

Software

Software interrupts :

are called from software, using a specified command.

Hardware interrupts:

are triggered by peripheral devices outside the microcontroller.

your embedded system may contain a timer that sends a pulse to the controller

every second.

Your microcontroller would wait until this pulse is received, and when the pulse

comes, an interrupt would be triggered that would handle the signal.

Interrupt handling code often called an ISR (“Interrupt Service Routine”)

When ISR is finished, execution returns to code running prior to interrupt.

Interrupt Service Routines (ISR) are the portions of the program code that

handle the interrupt requests.

When an Interrupt is triggered (either a hardware or software interrupt), the

processor breaks away from the current task, moves the instruction pointer

to the ISR, and then continues operation.

When the ISR has completed, the processor returns execution to the

previous location.

Interrupt Service Routine:

Many embedded systems are called interrupt driven systems, because most of

the processing occurs in ISRs, and the embedded system spends most of its time

in a low-power mode.

ISR into two parts:

top-half (fast interrupt handler, First-Level Interrupt Handler

(FLIH))

bottom-half (slow interrupt handler, Second-Level Interrupt

Handlers (SLIH)).

Top-half is a faster part of ISR which should quickly store minimal information

about interrupt and schedule slower bottom-half at a later time

Interrupt Sources

Hardware Interrupts

▫Commonly used to interact with external devices or peripherals

▫Microcontroller may have peripherals on chip

Software Interrupts

▫Triggered by software commands, usually for special operating system tasks]

• i.e. switching between user and kernel space, handling exceptions

Common hardware interrupt sources

▫Input pin change

▫Hardware timer overflow or compare-match

▫Peripherals for serial communication

UART, SPI, I2C – Rx data ready, tx ready, tx complete.

Watchdog timer timeout.

ADC conversion complete.

Multiple interrupt

Multiple interrupt-calls

Interrupt-service calls

There can be interrupt-service calls in case a number of higher

priority interrupt sources activates in succession.

• A return from any of the ISR is to the lower priority pending ISR

Processor interrupt service mechanisms.

Certain processors permit in-between routine diversion to higher

priority interrupts unless all interrupts or interrupts of priority

greater than the presently running routine are masked or ISR

executed DI instruction

These processors provide in order to prevent diversion in between

the running ISR completely by provisioning for masking all

interrupts by primary level bit and or Instruction

Hardware Assignment of priorities.

ARM7 provides two types of the interrupt sources (requests) ─ IRQs

(interrupt requests) and FIQs (fast interrupt requests).

Interrupts in 80x86 assigned interrupt-types and interrupt of type 0 has

highest priority and 255 as lowest priority

Multiple sources of interrupts

Multiple devices

Processor hardware assigns a priority phw to each source (including traps

or exceptions) or sourcegroupa pre-assumed priority (or level or type).

phw represents the hardware presumed priority for the source (or

group)Assume number be among 0, 1, 2, ..., k, ..., m-1.

Reference

www.google.com

www.wikipedia.com

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