Device description Applications System architecture€¦ · FMP v1.0 BAS v1.0 QTIL's ... mm pitch...
Transcript of Device description Applications System architecture€¦ · FMP v1.0 BAS v1.0 QTIL's ... mm pitch...
Device description■ QCC3003 stereo flash programmable solution
■ 1-mic Qualcomm® cVc™ headset noise reduction andecho cancellation technology
■ Fully qualified single-chip dual mode Bluetooth® v5.0system
Applications■ Stereo headsets
■ Wired stereo headsets and headphones
Features■ Radio includes integrated balun
with RF performance of 9 dBm(typ) transmit power and-89 dBm (typ) basic ratereceiver sensitivity
■ 80 MHz RISC CPU and80 MHz Qualcomm® Kalimba™
DSP■ On-chip ROM, RAM, and
external QSPI flash memory■ Link Layer and Dual Mode
Topologies■ Over the air updates of external
Flash partitions■ Wideband speech support■ Stereo Codec■ Stereo line input■ SBC and AAC audio codecs
support
■ 1-mic cVc headset NR/EC■ Bluetooth HID remote camera
control■ Audio interfaces: I²S and PCM,
analog and digital microphone■ Fully configurable EQ: 6 banks
for music enhancement; 1 bankfor speaker
■ Serial interfaces: UART, USB2.0, and I²C
■ Integrated dual switch-moderegulators, linear regulators,and battery charger
■ 52-lead QFN 6 × 6 × 0.6 mm0.4 mm pitch
■ Green (RoHS compliant and noantinomy or halogenated flameretardants)
System architecture
2.4 GHz Radio
+Balun
I/OBT_RF
RAM
Baseband
MCU
Kalimba DSP
ROMXTALSerial Flash
UART / USB
Audio In / Out
Debug SPI
PIO
SQIF
I2S
Confidential and Proprietary – Qualcomm Technologies International, Ltd.
NO PUBLIC DISCLOSURE PERMITTED: Please report postings of this document on public servers or websites to [email protected].
Restricted Distribution: Not to be distributed to anyone who is not an employee of either Qualcomm Technologies International, Ltd. or its affiliated companieswithout the express approval of Qualcomm Configuration Management.
Not to be used, copied, reproduced, or modified in whole or in part, nor its contents revealed in any manner to others without the express written permission ofQualcomm Technologies International, Ltd.
All Qualcomm products mentioned herein are products of Qualcomm Technologies, Inc. and/or its subsidiaries.
Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. Kalimba is a trademark of Qualcomm TechnologiesInternational, Ltd. cVc and meloD are trademarks of Qualcomm Technologies International, Ltd., registered in the United States and other countries. Other productand brand names may be trademarks or registered trademarks of their respective owners.
This technical data may be subject to U.S. and international export, re-export, or transfer ("export") laws. Diversion contrary to U.S. and international law is strictlyprohibited.
Qualcomm Technologies International, Ltd. (formerly known as Cambridge Silicon Radio Limited) is a company registered in England and Wales with a registeredoffice at: Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom.
Registered Number: 3665875 | VAT number: GB787433096
© 2017, 2018 Qualcomm Technologies Inc. and/or its subsidiaries. All rights reserved.
QCC3003 QFNProduction Information Data Sheet
80-CE950-1 Rev. ADApril 17, 2018
General description
The QCC3003 QFN is a single-chip flash programmable dual mode Bluetooth v5.0 device with integrated applicationprocessor, low-power audio DSP, on-chip ROM and RAM, stereo codec, battery charger, switch-mode and linearregulators, and LED drivers.The QCC3003 QFN on-chip ROM includes Bluetooth HCI lower and upper stack, and the audio DSP application withthe end product application and user interface in external flash programmable memory.The QCC3003 QFN device, the 1-mic stereo headset application (binary image and source code), IDE, andconfiguration tools provide a flexible and powerful platform for developing Bluetooth audio products with fast time tomarket.
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Device details
Dual mode Bluetooth radio■ On-chip balun (50 Ω impedance)■ No production trimming of external components■ Bluetooth v5.0 specification compliant
Bluetooth transmitter■ 9 dBm (typ) RF transmit power
Bluetooth receiver■ -91.0 dBm (typ) π/4 DQPSK receiver sensitivity and -81.0 dBm
(typ) 8DPSK receiver sensitivity■ Integrated channel filters■ Digital demodulator for improved sensitivity and cochannel
rejection■ Real-time digitized RSSI available to application■ Fast AGC for enhanced dynamic range■ Channel classification for AFH
Bluetooth synthesizer■ Fully integrated synthesizer requires no external VCO, varactor
diode, resonator, or loop filter■ Compatible with crystals 16 MHz to 32 MHz
Kalimba DSP■ Enhanced Kalimba DSP coprocessor, 80 MHz, 24‑bit fixed-point
core■ 2 single-cycle MACs: 24 × 24‑bit multiply and 56‑bit accumulator■ 32‑bit instruction word, dual 24‑bit data memory■ 6 K × 32‑bit program RAM including 1 K instruction cache for
executing out of internal ROM■ 16 K × 24‑bit + 16 K × 24‑bit 2-bank data RAM
Audio interfaces■ I²S output■ PCM/I²S input■ USB audio■ Stereo audio ADC with line input, stereo audio DAC■ Supported sample rates of 8, 11.025, 16, 22.05, 32, 44.1, and
48 kHz
Auxiliary features■ Crystal oscillator with built-in digital trimming
Physical interfaces■ UART interface■ USB 2.0 (full-speed) interface, including USB charger detection■ 4‑bit SPI flash memory interface■ SPI interface for debug and programming■ I²C master support■ Up to 10 general-purpose PIOs■ 3 LED drivers with PWM flasher independent of MCU
Integrated power control regulation■ 2 high-efficiency switch-mode regulators with 1.8 V and 1.35 V
outputs direct from battery supply■ 3.3 V linear regulator for USB supply■ Low-voltage linear regulator for internal digital circuits■ Low-voltage linear regulator for internal analog circuits■ Power-on-reset detects low supply voltage■ Power management for ultralow power modes
Battery charger■ Lithium ion / Lithium polymer battery charger■ Charger supports 4.20 V and 4.35 V cells■ Instant-on function automatically selects the power supply
between battery and USB, which enables operation even if thebattery is fully discharged
■ Fast charging support
□ Up to 200 mA with no external components■ Supports USB charger detection■ Support for thermistor protection of battery pack■ Support to enable end product design to PSE law:
□ Design to JIS-C 8712/8714 (batteries)□ Testing based on IEEE 1725
Baseband software■ Fully qualified under HCI and upper layer stack in on-chip ROM
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QCC3003 stereo flash solution details
Bluetooth features■ Bluetooth v5.0 specification support■ Qualcomm® Bluetooth® Low Energy secure connection■ A2DP v1.3.1■ AVRCP v1.6■ HFP v1.7■ HSP v1.2■ SPP v1.2■ DID v1.3■ HID v1.1■ PXP v1.0.1■ FMP v1.0■ BAS v1.0■ QTIL's proximity pairing and QTIL's proximity connection
Audio features■ SBC and AAC audio codecs■ Qualcomm ShareMe, which allows the sharing of audio
from QCC3003 to another Bluetooth A2DP sink device■ Configurable Signal Detection to trigger events■ 1 bank of up to 10-stage Speaker Parametric EQ■ 6 banks of up to 5-stage User Parametric EQ for music
enhancement■ Qualcomm® meloD™ Expansion audio processing: 3D
stereo widening■ Compander to compress or expand the dynamic range of
the audio■ Post Mastering to improve DAC fidelity■ I²S input/output
ADK configuration toolConfigures the QCC3003 stereo flash solution softwarefeatures:■ Bluetooth features■ Audio features■ Reconnection policies■ Button events■ LED indications■ Indication tones and audio prompts■ Battery divider ratios and thresholds■ Advanced Multipoint settings
QCC300x ADK software development kit■ Includes application source code■ Allows development and debug of customer application
QCC3003 development kit■ Example QCC3003 QFN module design■ Carrier board■ Headphone amplifier board■ Interface adapters and cables
Additional functionality■ Support for multi-language programmable audio prompts■ Multipoint support for A2DP connection to 2 A2DP sources
for music playback■ Talk-time extension, which automatically reduces
processor functions to extend use when a low batterycondition is detected
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QCC3003 QFN functional diagram
G-T
W-0
0168
74.2
.2
MemoryManagement
Unit
Bluetooth Modem
Kalimba DSP
I2CMasterSPI
(Debug)UART
4 Mbps
SystemRAM
Serial FlashInterface
DMA ports
DM
Apo
rts
I2S1
ROM
Debug SPI Serial FlashI2C
LINE/MIC_AN
UART
MCU
SPKR_LN
AudioInterface
MIC_BIAS
USB v2.0Full-speed
USB
3.3 V
MIC Bias
VM Accelerator(MPU)
PMUInterface
andBIST
Engine
LED PWMControl and
Output
PM
DM1
DM2
R G B
DigitalA
udio
1.35 VSwitch-mode
Regulator
BypassLDO
LXL_1V
8
Li-ionCharger
VCHG
1.8 VSwitch-mode
Regulator
LX_1V
35
VO
UT_3V
3
Voltage / TemperatureMonitor
BT_RF
ClockGeneration AUX ADC
XTAL AIO[0]
LINE/MIC_AP
SPKR_LP
SPKR_RNSPKR_RP
SENSE
BluetoothBaseband
Bluetooth Radioand Balun
TX
RX
High-quality ADC
High-quality DAC
High-quality DAC
1.35 VLow-voltageVDD_AUX
LinearRegulator
1.35 VLow-voltageVDD_ANA
LinearRegulator
0.85 V to1.25 V
Low-voltageVDD_DIG
LinearRegulator
DM
Apo
rts
VD
D_A
UX
SENSE
VD
D_A
NA
_RA
DIO
SENSE
VD
D_D
IG
SENSE
Switch
SM
PS
_1V35_S
EN
SE
SENSE
VBAT
VD
D_A
UX
_1V8_P
AD
S1
VR
EG
IN_D
IG
PIO Port
PIO
PIO Port
VDD_AUDIO
VDD_AUDIO_DRV_PADS2
SENSE
LINE_BNLINE_BP
High-quality ADC
Digital M
icrophone
DigitalMicrophone
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Ordering information
DevicePackage
Order numberType Size Shipment method
QCC3003 QFN QFN 52-lead(Pb free)
6 × 6 × 0.6 mm 0.4mm pitch Tape and reel QCC3003-0-52MQFN-TR-00-0
NOTE Minimum order quantity is 2 kpcs.Supply chain: QTIL's manufacturing policy is to multisource volume products. For further details,contact your local sales account manager or representative.
QCC3003 Development Kit ordering information
Description Order number
QCC3003 Development Kit DK-QCC3003-6x6QFN-CE690-1A
QCC3003 20-CE690 development board module DB-QCC3003-6x6QFN-CE690-1A
ROM variantQCC3003 QFN product code has the form QCC300x A14. Axx is the specific variant, A14 is the ROM-variant forQCC3003 stereo flash solution.
QTIL contacts
General information www.qualcomm.com
Information on this product [email protected]
Customer support for this product www.csrsupport.com
createpoint.qti.qualcomm.com
Details of compliance and standards [email protected]
Help with this document [email protected]
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Revision history
Revision Date Change reason
AA July 2017 Original publication of this document.Alternative document number CS-00404548-DS.
AB August 2017 Added Development Kit ordering information.Changed status to Production Information.
AC Spetember 2017 Updated VBAT_SENSE to VBAT in Section 10 Battery charger.Removed the external charge mode in Section 12.3.4 Battery charger.
AD April 2018 Updated ordering information.
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Status information
QTIL Product Data Sheets progress according to the following formats: Advance Information, Engineering Sample,Pre-production Information, and Production Information. The status of this document is Production Information.
Advance Information
Information for designers concerning QTIL product in development. All values specified are the target values of thedesign. Minimum and maximum values specified are only given as guidance to the final specification limits and mustnot be considered as the final values.
Engineering Sample
Information about initial devices. Devices are untested or partially tested prototypes, their status is described in anEngineering Sample Release Note. All values specified are the target values of the design. Minimum and maximumvalues specified are only given as guidance to the final specification limits and must not be considered as the finalvalues.
All detailed specifications including pinouts and electrical specifications may be changed by QTIL without notice.
Pre-production Information
Pinout and mechanical dimension specifications finalized. All values specified are the target values of the design.Minimum and maximum values specified are only given as guidance to the final specification limits and must not beconsidered as the final values.
All electrical specifications may be changed by QTIL without notice.
Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
Device implementationAs the feature-set of the QCC3003 QFN is firmware build-specific, see the relevant software release note for theexact implementation of features on the QCC3003 QFN.
Life support policy and use in safety-critical applicationsQTIL products are not authorized for use in life-support or safety-critical applications. Use in such applications isdone at the sole discretion of the customer. QTIL will not warrant the use of its devices in such applications.
QTIL environmental and RoHS complianceQCC3003 QFN devices meet the requirements of Directive 2011/65/EU of the European Parliament and of theCouncil on the Restriction of Hazardous Substance (RoHS).QCC3003 QFN devices are free from halogenated or antimony trioxide-based flame retardants and other hazardouschemicals. For more information, see QTIL Environmental declaration statement for QTIL semiconductor products.
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Contents
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Device details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
QCC3003 stereo flash solution details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
QCC3003 QFN functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6QCC3003 Development Kit ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ROM variant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6QTIL contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Device implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Life support policy and use in safety-critical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8QTIL environmental and RoHS compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171.2 Device terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181.3 Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221.4 PCB design and assembly considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231.5 Typical solder reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2 Bluetooth modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.1 RF ports (BT_RF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.2 RF receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.1 Low noise amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.2.2 RSSI analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 RF transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.3.1 I/Q modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.3.2 Power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 Bluetooth radio synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.5 Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.1 Negative resistance model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.1.2 Crystal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.1.3 Crystal calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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4 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.1 Bluetooth stack microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.2 Kalimba DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Memory interface and management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305.1 Memory management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305.2 System RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305.3 Kalimba DSP RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305.4 Internal ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305.5 Serial quad I/O flash interface (SQIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.1 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.2 UART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.3 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.1 Multi-slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.4 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.1 Programmable I/O ports (PIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.2 Analog I/O ports (AIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.3 LED drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8 Audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378.1 Audio input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378.2 Audio codec interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2.1 Audio codec block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388.2.2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388.2.3 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.2.4 Microphone bias generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428.2.5 Line input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438.2.6 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448.2.7 Mono operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448.2.8 Sidetone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458.2.9 Integrated digital IIR filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.3 I²S1 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9 Power control and regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509.1 Switch-mode regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1.1 1.8 V switch-mode regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529.1.2 1.35 V switch-mode regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539.1.3 Inductor choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.2 LDO linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559.2.1 Bypass LDO linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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9.2.2 Low-voltage VDD_DIG linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559.2.3 Low-voltage VDD_AUX linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559.2.4 Low-voltage VDD_ANA linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.3 Voltage regulator enable pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569.4 External regulators and power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.5.1 Digital pin states on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579.6 Automatic reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10 Battery charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5810.1 Battery charger hardware operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.1.1 Disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5910.1.2 Trickle charge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5910.1.3 Fast charge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5910.1.4 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5910.1.5 Error mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2 Battery charger trimming and calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5910.3 On-chip application battery charger control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5910.4 Battery charger firmware and PS Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11 Example application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6412.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6412.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6412.3 Input/Output terminal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.3.1 Regulators available for external use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6512.3.2 Regulators for internal use only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6612.3.3 Regulator enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6712.3.4 Battery charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6712.3.5 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6812.3.6 Stereo codec: analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6812.3.7 Stereo codec: digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6912.3.8 Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7012.3.9 LED driver pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7012.3.10 Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.4 Microphone bias generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7112.5 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7414.1 QCC3003 application software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7414.2 8th generation 1-mic cVc ENR technology for headset and audio enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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14.2.1 Acoustic echo cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7514.2.2 Noise suppression with wind noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7514.2.3 Nonlinear processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7614.2.4 Howling control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7614.2.5 Comfort noise generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7614.2.6 Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7614.2.7 Automatic gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7614.2.8 Packet loss concealment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7714.2.9 Adaptive equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7714.2.10 Auxiliary stream mix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7814.2.11 Clipper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7814.2.12 Noise dependent volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7814.2.13 Input/output gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14.3 Audio features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7814.3.1 Audio codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7814.3.2 Configurable EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7914.3.3 Stereo widening (S3D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7914.3.4 Volume boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
14.4 QCC3003 development kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
15 Environmental declaration statement for QTIL semiconductor products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
16 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8316.1 Tape orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8316.2 Tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8316.3 Reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8416.4 Moisture sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Document references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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Tables
Table 1-1: Package dimensions table....................................................................................................................................... 23
Table 3-1: Typical on-chip capacitance values..........................................................................................................................26
Table 3-2: Transconductance and on-chip parasitic capacitance............................................................................................. 27
Table 3-3: Specification for an external crystal........................................................................................................................ 27
Table 6-1: PS Keys for UART/PIO multiplexing......................................................................................................................... 32
Table 6-2: Possible UART settings.............................................................................................................................................33
Table 6-3: Standard baud rates................................................................................................................................................ 33
Table 7-1: Alternative PIO functions........................................................................................................................................ 35
Table 8-1: ADC audio input gain selection................................................................................................................................40
Table 8-2: DAC digital gain selection........................................................................................................................................ 41
Table 8-3: DAC analog gain selection....................................................................................................................................... 41
Table 8-4: Sidetone gain........................................................................................................................................................... 45
Table 8-5: Digital audio interface slave timing......................................................................................................................... 47
Table 8-6: I²S slave mode timing.............................................................................................................................................. 48
Table 8-7: Digital audio interface master timing...................................................................................................................... 48
Table 8-8: I²S master mode timing parameters, WS and SCK as outputs................................................................................. 48
Table 9-1: Recommended configurations for power control and regulation........................................................................... 50
Table 9-2: Inductor choice, QTIL's testing and characterization...............................................................................................54
Table 9-3: Pin states on reset................................................................................................................................................... 57
Table 10-1: Battery charger operating modes determined by battery voltage and charger current....................................... 58
Table 12-1: Microphone bias generator................................................................................................................................... 71
Table 12-2: ESD handling ratings.............................................................................................................................................. 71
Table 15-1: Restricted substances present in QTIL products....................................................................................................82
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Figures
Figure 1-1: QCC3003 QFN pinout diagram............................................................................................................................... 17
Figure 1-2: Package dimensions diagram................................................................................................................................. 22
Figure 2-1: Simplified circuit BT_RF..........................................................................................................................................24
Figure 3-1: Crystal oscillator overview..................................................................................................................................... 26
Figure 5-1: Typical connection between the QCC3003 QFN and a serial flash IC.................................................................... 30
Figure 6-1: Universal asynchronous receiver........................................................................................................................... 33
Figure 7-1: LED equivalent circuit............................................................................................................................................ 36
Figure 8-1: QCC3003 QFN audio interface............................................................................................................................... 37
Figure 8-2: Audio codec input and output stages.................................................................................................................... 38
Figure 8-3: Audio input gain..................................................................................................................................................... 39
Figure 8-4: Microphone biasing............................................................................................................................................... 42
Figure 8-5: Differential input.................................................................................................................................................... 43
Figure 8-6: Single-ended input................................................................................................................................................. 43
Figure 8-7: Speaker output...................................................................................................................................................... 44
Figure 8-8: Sidetone................................................................................................................................................................. 45
Figure 8-9: Digital audio interface modes................................................................................................................................ 47
Figure 8-10: Digital audio interface slave timing...................................................................................................................... 48
Figure 8-11: Digital audio interface master timing...................................................................................................................49
Figure 9-1: 1.8 V and 1.35 V dual-supply switch-mode system configuration......................................................................... 51
Figure 9-2: 1.8 V switch-mode regulator output configuration............................................................................................... 52
Figure 9-3: 1.35 V switch-mode regulator output configuration............................................................................................. 53
Figure 10-1: Battery charger mode-to-mode transition diagram.............................................................................................58
Figure 11-1: QCC3003 QFN example application schematic.................................................................................................... 61
Figure 11-2: Single 1.8 V only supply, with no USB or SMPSs.................................................................................................. 62
Figure 11-3: Single 3.3 V only supply, with USB and dual SMPSs............................................................................................. 63
Figure 14-1: 1-mic cVc headset block diagram.........................................................................................................................75
Figure 14-2: Configurable EQ GUI with drag points................................................................................................................. 79
Figure 14-3: Volume boost GUI with drag points..................................................................................................................... 80
Figure 16-1: QCC3003 QFN tape orientation........................................................................................................................... 83
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Figure 16-2: QCC3003 QFN tape dimensions diagram............................................................................................................. 83
Figure 16-3: Reel dimensions................................................................................................................................................... 84
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Equations
Equation 3-1: Negative resistance............................................................................................................................................27
Equation 3-2: Crystal calibration using PSKEY_ANA_FTRIM_OFFSET.......................................................................................28
Equation 7-1: LED current........................................................................................................................................................ 36
Equation 8-1: IIR filter transfer function, H(z).......................................................................................................................... 46
Equation 8-2: IIR filter plus DC blocking transfer function, HDC(z)........................................................................................... 46
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1 Package information
QCC3003 QFN is available in a 6 × 6 × 0.6 mm 52-lead QFN package.
1.1 Pinout diagram
G-T
W-0
0159
38.1
.3
1
13
2
7
8
3
4
5
6
9
10
11
12
14 15 20 2116 17 18 19 22 24 2523 26
38
37
32
31
36
35
34
33
30
29
28
27
52 51 50 45 4449 48 47 46 43 41 4042 39
Orientation from Top of Device
Figure 1-1 QCC3003 QFN pinout diagram
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1.2 Device terminal functions
Radio Lead Pad type Supply domain Description
BT_RF 9 RF VDD_ANA_RADIO Bluetooth 50 Ω transmitteroutput/receiver input
Oscillator Lead Pad type Supply domain Description
XTAL_IN 14 Analog VDD_AUX Input from crystal
XTAL_OUT 13 Analog VDD_AUX Drive for crystal
USB Lead Pad type Supply domain Description
USB_DP 41 Bidirectional VOUT_3V3 USB data plus with selectableinternal 1.5 kΩ pull-up resistor
USB_DN 40 Bidirectional VOUT_3V3 USB data minus
SPI/I²S Interface Lead Pad type Supply domain Description
SPI_PCM# 23 Input with weak pull-down VDD_AUX_1V8_PADS1
SPI/I²S select input:■ 0 = I²S/PIO interface■ 1 = SPI
NOTE Debug SPI and I²S1 interfaces are mapped as alternative functions on the PIO port.
SQIF Lead Pad type Supply domain Description
QSPI_FLASH_CLK 20 Bidirectional withstrong pull-down VDD_AUX_1V8_PADS1 SPI flash clock
QSPI_FLASH_CS# 17 Bidirectional withstrong pull-up VDD_AUX_1V8_PADS1 SPI flash chip select
QSPI_IO[3] 16 Bidirectional withstrong pull-up VDD_AUX_1V8_PADS1 SPI flash data bit 3
QSPI_IO[2] 18 Bidirectional withstrong pull-up VDD_AUX_1V8_PADS1 SPI flash data bit 2
QSPI_IO[1] 25 Bidirectional withstrong pull-down VDD_AUX_1V8_PADS1 SPI flash data bit 1
QSPI_IO[0] 21 Bidirectional withstrong pull-down VDD_AUX_1V8_PADS1 SPI flash data bit 0
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PIO port Lead Pad type Supply domain Description
PIO[9] 43 Bidirectional withstrong pull-down VDD_AUDIO_DRV_PADS2
Programmable input/output line9.Alternative function:■ UART_CTS: UART clear to
send, active low
PIO[8] 46 Bidirectional withstrong pull-up VDD_AUDIO_DRV_PADS2
Programmable input/output line8.Alternative function:■ UART_RTS: UART request
to send, active low
PIO[7] 42 Bidirectional withstrong pull-down VDD_AUDIO_DRV_PADS2 Programmable input/output line
7.
PIO[6] 47 Bidirectional withstrong pull-down VDD_AUDIO_DRV_PADS2 Programmable input/output line
6.
PIO[5] 26
Bidirectional with weakpull-down
VDD_AUX_1V8_PADS1
Programmable input/output line5.Alternative function:■ SPI_CLK: Debug SPI clock■ I2S1_SCK: I²S1
synchronous data clock
PIO[4] 19 Bidirectional with weakpull-down VDD_AUX_1V8_PADS1
Programmable input/output line4.Alternative function:■ SPI_CS#: chip select for
Debug SPI, active low■ I2S1_WS: I²S1 word select
PIO[3] 22 Bidirectional with weakpull-down VDD_AUX_1V8_PADS1
Programmable input/output line3.Alternative function:■ SPI_MISO: Debug SPI data
output■ I2S1_SD_OUT: I²S1
synchronous data output
PIO[2] 24 Bidirectional with weakpull-down VDD_AUX_1V8_PADS1
Programmable input/output line2.Alternative function:■ I2S1_SD_IN: I²S1
synchronous data input■ SPI_MOSI: Debug SPI data
input
PIO[1] 45 Bidirectional withstrong pull-up VDD_AUDIO_DRV_PADS2
Programmable input/output line1.Alternative function:■ UART_TX: UART data
output
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PIO port Lead Pad type Supply domain Description
PIO[0] 44 Bidirectional withstrong pull-up VDD_AUDIO_DRV_PADS2
Programmable input/output line0.Alternative function:■ UART_RX: UART data input
AIO[0] 15 Bidirectional VDD_AUX Analog programmable inputline 0.
Codec Lead Pad type Supply domain Description
MIC_BIAS 52 Analog out VBAT/VOUT_3V3 Microphone bias
AU_REF 51 Analog in VDD_AUDIO Decoupling of audio reference(for high-quality audio)
SPKR_RN 4 Analog out VDD_AUDIO_DRV_PADS2 Speaker output negative, right
SPKR_RP 5 Analog out VDD_AUDIO_DRV_PADS2 Speaker output positive, right
SPKR_LN 7 Analog out VDD_AUDIO_DRV_PADS2 Speaker output negative, left
SPKR_LP 8 Analog out VDD_AUDIO_DRV_PADS2 Speaker output positive, left
LINE/MIC_AN 50 Analog in VDD_AUDIO Line or microphone inputnegative, channel A
LINE/MIC_AP 49 Analog in VDD_AUDIO Line or microphone inputpositive, channel A
LINE_BN 2 Analog in VDD_AUDIO Microphone input negative,channel B
LINE_BP 3 Analog in VDD_AUDIO Microphone input positive,channel B
LED drivers Lead Pad type Supply domain Description
LED [2] 48 Bidirectional VDD_AUDIO_DRV_PADS2 Open-drain output
LED [1] 27 Bidirectional VDD_AUX_1V8_PADS1 Open-drain output
LED [0] 28 Bidirectional VDD_AUX_1V8_PADS1 Open-drain output
Power supplies andcontrol Lead Description
VOUT_3V3 36Positive supply for USB port and 3.3 V bypass linear regulator output.Connect external 2.2 μF ceramic decoupling capacitor.
LX_1V35 37 1.35 V switch-mode power regulator inductor connection.
LX_1V8 34 1.8 V switch-mode power regulator inductor connection.
SMPS_1V35_SENSE 39 1.35 V switch-mode power regulator sense input.
VBAT 35 Battery positive terminal.
VCHG 32Charger input.Typically connected to USB VBUS.
VDD_ANA_RADIO 10Bluetooth radio supply.Connect to 1.35 V supply.
VDD_AUDIO 1Positive supply for audio.Connect to 1.35 V supply.
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Power supplies andcontrol Lead Description
VDD_AUDIO_DRV_PADS2 6Positive supply for audio output amplifiers.Connect to 1.8 V supply.
VDD_AUX 11Auxiliary supply.Connect to 1.35 V supply.
VDD_AUX_1V8_PADS1 12Auxiliary LDO regulator input.Connect to 1.8 V supply.
VDD_DIG 29 Digital LDO regulator output.
VREGENABLE 31Regulator enable and multifunction button. A high input (tolerant to VBATvoltages) enables the on-chip regulators, which can then be latched oninternally and the button used as a multifunction input.
VREGIN_DIG 30Digital LDO regulator input.Typically connected to a 1.35 V supply.
VSS_SMPS_1V35 38 1.35 V switch-mode regulator ground.
VSS_SMPS_1V8 33 1.8 V switch-mode regulator ground.
VSS Exposed pad Ground connections.
Related Information“Example application schematic” on page 61
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1.3 Package dimensions
G-T
W-0
0159
35.1
.9
A2A
Laser Mark for Pin 1Identification in this Area
D
E
Top View Side View
38
3952
2712
26
1
13
E2
D2
Pin 1 ID
Seating PlaneA
C
Bottom View
Ldb
LE3
D3
Caaa
Caaa
CcccCbbb
A1B
C A B
C A B
M Addd BC
Scale1 mm
D1
E1
SD
SE
Figure 1-2 Package dimensions diagram
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Table 1-1 Package dimensions table
Description Min Typ Max Description Min Typ Max
A 0.48 0.54 0.60 E1 – 5.20 –
A1 – 0.09 – E2 3.73 3.78 3.83
A2 – 0.45 – E3 0.66 – –
b 0.15 0.20 0.25 L 0.30 0.35 0.40
D 5.90 6.00 6.10 aaa – 0.10 –
D1 – 4.40 – bbb – 0.10 –
D2 3.73 3.78 3.83 ccc – – –
D3 0.66 – – ddd – 0.10 –
d – 0.40 – SD – 0.20 –
E 5.9 6.00 6.10 SE – 0.20 –
Notes ■ Dimensions and tolerances conform to ASME Y14.5M. - 1994■ Pin 1 identifier is placed on top surface of the package by using identification mark or other
feature of package body.■ Exact shape and size of this feature is optional.■ Package warpage 0.08 mm maximum.
Description 52-lead Quad-Flat No-lead (QFN) package
Size 6 × 6 × 0.6 mm JEDEC Non-JEDEC
Pitch 0.4 mm pitch Unit mm
1.4 PCB design and assembly considerationsThis section lists recommendations to achieve maximum board-level reliability of the 6 × 6 × 0.6 mm QFN 52-leadpackage:■ The use of nonsolder mask defined (NSMD) lands (lands smaller than the solder mask aperture) are preferred,
because of the greater accuracy of the metal definition process compared to the solder mask process. Withsolder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the landinterface, which can cause stress concentration and act as a point for crack initiation.
■ Qualcomm Technologies International, Ltd. (QTIL) recommends that the printed circuit board (PCB) land patternis in accordance with Institute of Printed Circuits (IPC) standard IPC-7351.
■ Solder paste must be used during the assembly process.
1.5 Typical solder reflow profileFor information, see the Typical Solder Reflow Profile for Lead-free Devices Application Note.
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2 Bluetooth modem
The Bluetooth modem includes the following components:■ RF ports
■ RF receiver
■ RF transmitter
■ Bluetooth radio synthesizer
■ Baseband
2.1 RF ports (BT_RF)QCC3003 QFN contains an on-chip balun that combines the balanced outputs of the power amplifier (PA) ontransmit and produces the balanced input signals for the low noise amplifier (LNA) required on receive. No matchingcomponents are needed as the receive mode impedance is 50 Ω and the transmitter is optimized to deliver powerinto a 50 Ω load.
G-T
W-0
0122
03.1
.2
+
_PA
+
_LNA
BT_RFOn-chip Balun
VDD
VSS
Figure 2-1 Simplified circuit BT_RF
2.2 RF receiverThe receiver features a near-zero intermediate frequency (IF) architecture that enables the channel filters to beintegrated onto the die. Sufficient out-of-band blocking specification at the LNA input enables the receiver to operateclose to global system for mobile communications (GSM) and wideband code division multiple access (WCDMA)cellular phone transmitters without being desensitized. A digital frequency shift keying (FSK) discriminator meansthat no discriminator tank is needed and its excellent performance in the presence of noise enables QCC3003 QFNto exceed the Bluetooth requirements for cochannel and adjacent channel rejection.
2.2.1 Low noise amplifier
The LNA operates in differential mode and takes its input from the balanced port of the on-chip balun.
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2.2.2 RSSI analog-to-digital converter
The analog-to-digital converter (ADC) implements fast automatic gain control (AGC). The ADC samples the receivedsignal strength indication (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is changed according to themeasured RSSI value, keeping the first mixer input signal within a limited range. This feature improves the dynamicrange of the receiver, improving performance in interference-limited environments.
2.3 RF transmitter
2.3.1 I/Q modulator
The transmitter features a direct in-phase and quadrature (I/Q) modulator to minimize frequency drift during atransmit timeslot, which results in a controlled modulation index. Digital baseband transmit circuitry provides therequired spectral shaping.
2.3.2 Power amplifier
The internal PA output power is software controlled and configured through a persistent store key (PS Key). Theinternal PA on the QCC3003 QFN has a maximum output power that enables it to operate as an up to Class 1Bluetooth radio without requiring an external radio frequency (RF) PA.
2.4 Bluetooth radio synthesizerThe Bluetooth radio synthesizer is fully integrated onto the die with no requirement for an external voltage-controlledoscillator (VCO) screening can, varactor tuning diodes, an inductor (L) and capacitor (C) network (LC) resonators, orloop filter. The synthesizer is guaranteed to lock in sufficient time across the guaranteed temperature range to meetthe Bluetooth v5.0 specification.
2.5 BasebandThe baseband handles the digital functions of the Bluetooth modem, for example the Burst Mode Controller andPhysical Layer Hardware Engine.
QCC3003 QFN Data Sheet Bluetooth modem
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3 Clock generation
Crystals form a part of a crystal oscillator circuit to generate a clock signal.
3.1 CrystalQCC3003 QFN contains a crystal oscillator that acts as a transconductance amplifier and drives an external crystalconnected between XTAL_IN and XTAL_OUT. The crystal driver circuit forms a Pierce oscillator with the externalcrystal. External capacitors are not required for standard crystals that require a load capacitance of around 9 pF.
G-T
W-0
0114
78.2
.2
External Crystal
gm
Amplifier gmControl LVL[3:0]
On-chip Capacitance Control
XTAL_IN XTAL_OUT
Figure 3-1 Crystal oscillator overview
The on-chip capacitance is adjusted using PSKEY_XTAL_OSC_CONFIG, see Table 3-1. The default values suit atypical crystal requiring a 9 pF load capacitance. In deep sleep mode, the crystal oscillation is maintained, but at alower drive strength to reduce power consumption. The drive strength and load capacitance are configured with a PSKey.
Table 3-1 Typical on-chip capacitance values
Normal modePSKEY_XTAL_OSC_CONFIG [3:2]
Low-power modePSKEY_XTAL_OSC_CONFIG [1:0]
Value 00 01 10 11 00 01 10 11
XTAL_IN(Typical)
15.6 pF 10.8 pF 6.0 pF 1.1 pF 15.6 pF 10.8 pF 6.0 pF 1.1 pF
XTAL_OUT(Typical)
20.8 pF 16.0 pF 11.2 pF 6.4 pF 16.0 pF 11.2 pF 6.4 pF 1.5 pF
The drive strength is configured with PSKEY_XTAL_LVL. The default level for this PS Key is sufficient for typicalcrystals. The level control is set in the range 0 to 15, where 15 is the maximum drive level.
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Increasing the crystal amplifier drive level increases the transconductance of the crystal amplifier, which creates anincrease in the oscillator margin.
NOTE Excessive amplifier transconductance can increase the oscillator phase noise if the oscillator amplifieris excessively overdriven. Set the transconductance to the minimum level to give the intendedoscillation ratio. Higher values can increase power consumption. Also, insufficient drive strength canprevent the crystal from starting to oscillate.
3.1.1 Negative resistance model
The crystal and its load capacitor can be modeled as a frequency-dependent resistive element. Consider the driveramplifier as a circuit that provides negative resistance. For oscillation, the value of the negative resistance should begreater than that of the crystal circuit equivalence resistance.Equation 3-1 shows how to calculate the equivalent negative resistance.
Rneg=‐ gmCinCout
(2πf)2(CoutCin+(C0+Cint)(Cout+Cin))2+(C0+Cint)
2gm2
Equation 3-1 Negative resistance
Where:■ gm = Transconductance of the crystal oscillator amplifier
■ Co = Static capacitance of the crystal, which is sometimes referred to as the shunt or case capacitance
■ Cint = On-chip parasitic capacitance between input and output of crystal (XTAL) amplifier
■ Cin = Internal capacitance on XTAL_IN
■ Cout = Internal capacitance on XTAL_OUT
Table 3-2 Transconductance and on-chip parasitic capacitance
Parameter Min Typ Max Unit
Transconductance 2 – – mS
Cint – 1.5 – pF
3.1.2 Crystal specification
Table 3-3 Specification for an external crystal
Parameter Min Typ Max Unit
Frequency 16 26 32 MHz
Initial frequency error from nominal frequency thatcan be compensated for
– – ± 285 ppm
Frequency stability – – ± 20 ppm
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3.1.3 Crystal calibration
The actual crystal frequency depends on the capacitance of XTAL_IN and XTAL_OUT on the PCB and the QCC3003QFN, as well as the capacitance of the crystal.The Bluetooth specification requires ± 20 ppm clock accuracy. The actual frequency at which a crystal oscillatescontains two error terms, which are typically mentioned in the crystal device data sheets:■ Initial Frequency Error: The difference between the intended frequency and the actual oscillating frequency
caused by the crystal itself and its equivalent series resistance (ESR) connections. It is also called CalibrationTolerance or Frequency Tolerance.
■ Frequency Stability: The total of how far the crystal can move off frequency with temperature, aging, or othereffects. It is also called Temperature Stability, Frequency Stability, or Aging.
QCC3003 QFN has the capability to compensate for initial frequency errors by a simple per-device basis on theproduction line, with the trim value stored in the nonvolatile memory PS Key. However, it is not possible tocompensate for frequency stability, therefore a crystal must be chosen with a frequency stability that is better than ±20 ppm clock accuracy.Some crystal data sheets combine both these terms into one tolerance value. This causes a problem because onlythe initial frequency error can be compensated for and QCC3003 QFN cannot compensate for the temperature oraging performance. If frequency stability is not explicitly stated, QTIL cannot guarantee remaining within theBluetooth's ± 20 ppm frequency accuracy specification.Crystal calibration uses a single measurement of RF output frequency and can be performed quickly as part of theproduct final test. Typically, a TXSTART radio command is sent and then a measurement of the output RF frequencyis read. From this process, the calibration factor to correct actual offset from the intended frequency can becalculated. This offset value is stored in PSKEY_ANA_FTRIM_OFFSET. QCC3003 QFN then compensates for theinitial frequency offset of the crystal.The value in PSKEY_ANA_FTRIM_OFFSET is a 16-bit two's complement signed integer that specifies the fractionalpart of the ratio between the true crystal frequency, factual, and the value set in PSKEY_ANA_FREQ, fnominal.Equation 3-2 shows the value of PSKEY_ANA_FTRIM_OFFSET in parts per 220 rounded to the nearest integer.
PSKEY_ANA_FTRIM_OFFSET = (factual
fnominal ‐ 1) × 220
Equation 3-2 Crystal calibration using PSKEY_ANA_FTRIM_OFFSET
For more information on TXSTART radio test, see the BlueTest User Guide.
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4 Processors
4.1 Bluetooth stack microcontrollerThe QCC3003 QFN uses a 16‑bit reduced instruction set computer (RISC) 80 MHz microcontroller unit (MCU) forlow-power consumption and efficient use of memory. It contains a single-cycle multiplier and a memory protectionunit.The MCU, interrupt controller, and event timer run the Bluetooth software stack and control the Bluetooth radio andhost interfaces.
4.2 Kalimba DSPThe Kalimba digital signal processor (DSP) performs signal processing functions on over-air data or codec data toenhance audio applications. The key features of the DSP include:■ 80 million instructions per second (MIPS) performance, 24‑bit fixed-point DSP core
■ Single-cycle multiplier and accumulator (MAC); 24 × 24‑bit multiply and 56‑bit accumulate includes two rMACregisters and new instructions for improved performance over previous architecture
■ 32‑bit instruction word
■ Separate program memory and dual data memory, enabling an arithmetic logic unit (ALU) operation and up totwo memory accesses in a single cycle
■ Zero overhead looping, including a low-power 32‑instruction cache
■ Zero overhead circular buffer indexing
■ Single cycle barrel shifter with up to 56‑bit input and 56‑bit output
■ Multiple cycle divide (performed in the background)
■ Bit reversed addressing
■ Orthogonal instruction set
■ Low overhead interrupt
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5 Memory interface and management
5.1 Memory management unitThe memory management unit (MMU) provides buffers that hold the data in transit between the host, the air or theKalimba DSP. The use of direct memory access (DMA) ports also helps with efficient transfer of data to otherperipherals.
5.2 System RAM56 KB of integrated random access memory (RAM) supports the RISC MCU.
5.3 Kalimba DSP RAMAdditional integrated RAM provides support for the Kalimba DSP.
5.4 Internal ROMInternal read only memory (ROM) contains system firmware implementation and DSP applications.
5.5 Serial quad I/O flash interface (SQIF)The QCC3003 QFN uses external serial flash integrated circuit (IC)s for storage of:■ Device-specific data
■ Application
■ Libraries
■ Voice prompt files
■ Proprietary data
The QCC3003 QFN supports a 4‑bit input/output (I/O) flash-memory interface.
G-T
W-0
0144
10.2
.2
MemoryManagement
Unit
Serial QuadI/O Flash
MCU Program
MCU Data
Kalimba DSP Data
Kalimba DSP Program
MCU
Kalimba DSP
QSPI_FLASH_CLK
QSPI_FLASH_CS#
QSPI_IO[0]
SQIF
CLK
CS#
DI/IO0
WP#/IO2
RESET#/HOLD#/IO3QSPI_IO[3]
QSPI_IO[2]
QSPI_IO[1] DO/IO1
Figure 5-1 Typical connection between the QCC3003 QFN and a serial flash IC
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The serial quad input/output flash (SQIF) interface on the QCC3003 QFN requires use of a suitable quad serialperipheral interface (SPI) flash chip, connected as Figure 5-1 shows. For a list of supported quad SPI flash devices,see the QCC300x A14 ROM Firmware Release Note.
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6 Serial interfaces
6.1 USB interfaceQCC3003 QFN has a full-speed (12 Mbps) universal serial bus (USB) interface for communicating with othercompatible digital devices. The USB interface on QCC3003 QFN acts as a USB peripheral, responding to requestsfrom a master host controller.QCC3003 QFN contains internal USB termination resistors and requires no external resistors.QCC3003 QFN supports the Universal Serial Bus Specification, Revision v2.0 (USB v2.0 Specification), supportsUSB standard charger detection, and fully supports the USB Battery Charging Specification v1.2. For moreinformation on how to integrate the USB interface on QCC3003 QFN, see the Bluetooth and USB DesignConsiderations Application Note.As well as describing USB basics and architecture, the application note describes:■ Power distribution for high and low bus-powered configurations
■ Power distribution for self-powered configuration, which includes USB VBUS monitoring
■ USB enumeration
■ Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects of ferritebeads
■ USB suspend support
■ Battery charging from USB, which describes dead battery provision, charge currents, charging in suspendmodes, and USB VBUS voltage consideration
■ USB termination when interface is not in use
■ Internal modules, certification, and non-specification compliant operation
6.2 UART interfaceQCC3003 QFN has a universal asynchronous receiver transmitter (UART) serial interface that provides a simplemechanism for communicating with other serial devices using the RS232 protocol, including for test and debug. TheUART interface is multiplexed with programmable input/output (PIO)s and other functions, and hardware flow controlis optional.
Table 6-1 PS Keys for UART/PIO multiplexing
PS Key PIO location
PSKEY_UART_RX_PIO PIO[0]
PSKEY_UART_TX_PIO PIO[1]
PSKEY_UART_RTS_PIO PIO[8]
PSKEY_UART_CTS_PIO PIO[9]
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Figure 6-1 shows the 4 signals that implement the UART function.
G-T
W-0
0167
06.1
.2
PIO[1]
PIO[0]
PIO[8]
PIO[9]
UART_TX
UART_RX
UART_RTS
UART_CTS
Figure 6-1 Universal asynchronous receiver
When QCC3003 QFN is connected to another digital device, UART_RX and UART_TX transfer data between the 2devices. The remaining 2 signals, UART_CTS and UART_RTS, implement optional RS232 hardware flow controlwhere both are active low indicators.UART configuration parameters, such as baud rate and packet format, are set using the QCC3003 QFN firmware.
NOTE To communicate with the UART at its maximum data rate using a standard personal computer (PC), thePC requires an accelerated serial port adapter card.The use of UART and USB are mutually exclusive.
Table 6-2 Possible UART settings
Parameter Possible values
Baud rateMinimum
1200 baud (≤ 2% Error)
9600 baud (≤ 1% Error)
Maximum 4 Mbaud (≤ 1% Error)
Flow control RTS/CTS or None
Parity None, Odd or Even
Number of stop bits 1 or 2
Bits per byte 8
Table 6-3 lists common baud rates and their associated error values for PSKEY_UART_BITRATE. To set the UARTbaud rate, load PSKEY_UART_BITRATE with the number of bits per second.
Table 6-3 Standard baud rates
Baud rate PS Key value (bits per second) Error
1200 1200 1.73%
2400 2400 1.73%
4800 4800 1.73%
9600 9600 -0.82%
19200 19200 0.45%
38400 38400 -0.18%
57600 57600 0.03%
76800 76800 0.14%
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Table 6-3 Standard baud rates (cont.)
Baud rate PS Key value (bits per second) Error
115200 115200 0.03%
230400 230400 0.03%
460800 460800 -0.02%
921600 921600 0.00%
1382400 1382400 -0.01%
1843200 1843200 0.00%
2764800 2764800 0.00%
3686400 3686400 0.00%
6.3 SPI interfaceQCC3003 QFN provides a debug SPI interface for programming, configuring, and debugging the QCC3003 QFN.Access to this interface is required in production. Ensure the 4 SPI signals and the SPI_PCM# line are brought out toeither test points or a header. The SPI_PCM# line needs to be pulled high externally to use the SPI interface.QTIL provides development and production tools to communicate over the SPI from a PC, although a level translatorcircuit is often required. All are available from QTIL.
6.3.1 Multi-slave operation
Avoid connecting QCC3003 QFN in a multi-slave arrangement by simple parallel connection of slave master in slaveout (MISO) lines. When QCC3003 QFN is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead,QCC3003 QFN outputs 0 if the processor is running or 1 if it is stopped.
6.4 I²C interfaceThe QCC3003 QFN supports an inter-integrated circuit interface (I²C) interface for I/O port expansion. The defaultassignment of the I²C interface onto the PIOs on the QCC3003 QFN is:■ PIO[0] is the I²C interface serial clock line (SCL) line (AMP_I2C_SCL)
■ PIO[1] is the I²C interface serial data (SDA) line (AMP_I2C_SDA)
Alternatively, the I²C interface can be assigned to two PIOs from PIO[9:0] using PSKEY_I2C_SCL_PIO andPSKEY_I2C_SDA_PIO.
NOTE The I²C interface requires external pull-up resistors. Ensure that external pull-up resistors are suitablysized for the I²C interface speed and PCB track capacitance.
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7 Interfaces
7.1 Programmable I/O ports (PIO)QCC3003 QFN provides up to 10 lines of programmable bidirectional I/O, PIO[9:0].
Table 7-1 Alternative PIO functions
PIOFunction
Debug SPI UART I²C inter-integratedcircuit sound (I²S)
PIO[0] – UART_RX AMP_I2C_SCL(default)
–
PIO[1] – UART_TX AMP_I2C_SDA(default)
–
PIO[2] SPI_MOSI – Alternate I²C function I2S1_SD_IN
PIO[3] SPI_MISO – Alternate I²C function I2S1_SD_OUT
PIO[4] SPI_CS# – Alternate I²C function I2S1_WS
PIO[5] SPI_CLK – Alternate I²C function I2S1_SCK
PIO[6] – – Alternate I²C function –
PIO[7] – – Alternate I²C function –
PIO[8] – – Alternate I²C function Reserved
PIO[9] – – Alternate I²C function –
NOTE See the relevant software release note for the implementation of these PIO lines.
Related Information“I²C interface” on page 34“UART interface” on page 32
7.2 Analog I/O ports (AIO)QCC3003 QFN has one general-purpose analog interface pin, AIO[0]. Typically, this pin connects to a thermistor forbattery pack temperature measurements during charging.
Related Information“Example application schematic” on page 61
7.3 LED driversThe QCC3003 QFN includes a 3-pad pulse width modulation (PWM) LED driver for driving red green blue (RGB)LEDs for producing a wide range of colors. All LEDs are controlled by application.
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The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in serieswith a current-limiting resistor.
G-T
W-0
0055
34.4
.2
LED Forward Voltage, VF
Pad Voltage, VPAD
RLED
LED[2, 1 or 0]Resistor Voltage Drop, VR
LED Supply
I LED
Figure 7-1 LED equivalent circuit
From Figure 7-1 it is possible to derive Equation 7-1 to calculate ILED. If a known value of current is required throughthe LED to give a specific luminous intensity, then the value of RLED is calculated.
ILED =VDD − VF
RLED + Rpad
Equation 7-1 LED current
NOTE The supply domain for LED[2:0], VDD_PADS_2, or VDD_PADS_1, must remain powered for LEDfunctions to operate.
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8 Audio interface
The audio interface circuit consists of the following components:■ Single analog microphone input or dual analog line inputs
■ Dual analog audio outputs
■ 1 digital microphone input
■ 1 configurable I²S interface
Figure 8-1 shows the functional blocks of the audio interface. The coder decoder (codec) supports stereo/dual-monoplayback and recording of audio signals at multiple sample rates with a 16-bit resolution. The ADC and the digital-to-analog converter (DAC) of the codec each contain two independent high-quality channels. Each ADC or DACchannel runs at its own independent sample rate.
G-T
W-0
017226
.4.2
Stereo / Dual-mono Codec
Memory Management
Unit
MMU Voice Port
Register Interface
Voice Port
Registers
I2S1
StereoAudioCodecDriver
I2S1 Interface
2 x DifferentialDAC Outputs
2 x DifferentialADC Inputs
DigitalMicrophone
1 x Digital Microphone
Figure 8-1 QCC3003 QFN audio interface
8.1 Audio input and outputThe audio input circuitry consists of two independent 16-bit high-quality ADC channels:■ Programmable as either stereo or dual-mono for line input.
■ Programmable as mono for analog or digital microphone input.
■ Each channel can be connected as either single-ended or fully differential.
■ Each channel has an analog and digital programmable gain stage.
The audio output circuitry consists of a dual differential class A-B output stage.
NOTE QCC3003 QFN is designed for a differential audio output. If a single-ended audio output is required,use an external differential to single-ended converter.
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8.2 Audio codec interfaceThe interface has the following features:■ Mono analog input for voice band and audio band
■ Stereo and mono analog output for voice band and audio band
NOTE To avoid any confusion regarding stereo operation, this data sheet explicitly states which is the left andright channel for audio output. With respect to audio input, software, and any registers, channel 0 orchannel A represents the left channel and channel 1 or channel B represents the right channel.
8.2.1 Audio codec block diagram
G-T
W-0
0168
76.1
.4
Input AHigh-quality ADC 16LINE/MIC_APLINE/MIC_AN
Digital Codec
Stereo Audio and Voice Band Output
High-quality DAC
Low-pass Filter
SPKR_LNSPKR_LP
16
High-quality DACSPKR_RNSPKR_RP
16
Digital Circuitry
Stereo Audio, Voice Band and Digital Microphone Input
Low-pass Filter
Input BHigh-quality ADC 16LINELINE_BPLINE_BN
Digital Codec
Input C16Digital CodecDigital MicClockData
PIO[EVEN]PIO[ODD]
Digital Mic Interface
Note:L/R pins on digital microphonepulled up or down on the PCB
Figure 8-2 Audio codec input and output stages
The QCC3003 QFN audio codec uses a fully differential architecture in the analog signal path. This architectureresults in low common-mode-noise sensitivity and good power supply rejection while effectively doubling the signalamplitude. It operates from a dual power supply, VDD_AUDIO for the audio circuits and VDD_AUDIO_DRV_PADS2for the audio driver circuits.
8.2.2 ADC
The QCC3003 QFN consists of two high-quality ADCs:■ Each ADC has a second-order Sigma-Delta converter.
■ Each ADC is a separate channel with identical functionality.
■ Each channel has an analog and a digital gain stage.
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8.2.2.1 ADC sample rate selection
Each ADC supports the following predefined sample rates:■ 8 kHz
■ 11.025 kHz
■ 16 kHz
■ 22.050 kHz
■ 24 kHz
■ 32 kHz
■ 44.1 kHz
■ 48 kHz
8.2.2.2 ADC audio input gain
The QCC3003 QFN audio input gain consists of the following components:■ An analog gain stage based on a pre-amplifier and an analog gain amplifier
■ A digital gain stage
G-T
W-0
0055
35.5
.2
ADC Pre-amplifierand ADC Analog Gain: -3 dB to 42 dB in 3 dB steps
ADC Pre-amplifier:0 dB, 9 dB, 21 dB, and 30 dB
ADC Analog Gain:-3 dB to 12 dB in 3 dB steps
ADC Digital Gain:-24 dB to 21.5 dB in alternating2.5 dB and 3 dB steps
Audio Input To Digital Codec
System Gain = ADC Pre-amplifier + ADC Analog Gain + ADC Digital Gain
Figure 8-3 Audio input gain
8.2.2.3 ADC pre-amplifier and analog/digital gain
The gain of the ADC inputs can be configured in the range of -27 dB to 63.5 dB steps, making it suitable for line andmicrophone input levels. 0 dB is 1600 mV pk-pk input.The ADC input impedance is nominal 6 kΩ except when 0 dB pre-amplifier gain is selected when it becomes 12 kΩ.If the input pre-amplifier is disabled, the input impedance varies between 6 kΩ and 34 kΩ, depending on gainselection. In normal operation, the input pre-amplifier is enabled.Calls connected by the virtual machine (VM) stream automatically select the distribution of gain within the ADC forbest performance. Alternatively, the individual gain stages can be set.
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8.2.2.4 ADC digital gain
Table 8-1 lists how the ADC digital gain selection values map to digital gain settings.
Table 8-1 ADC audio input gain selection
Digital gain selection value ADC digital gain setting(dB) Digital gain selection value ADC digital gain setting
(dB)
0 0 8 -24
1 3.5 9 -20.5
2 6 10 -18
3 9.5 11 -14.5
4 12 12 -12
5 15.5 13 -8.5
6 18 14 -6
7 21.5 15 -2.5
8.2.2.5 ADC digital IIR filter
The ADC contains 2 integrated anti-aliasing filters:■ A long infinite impulse response (IIR) filter suitable for music (> 44.1 kHz).
■ G.722 filter. This is a digital IIR filter that improves the stop-band attenuation required for G.722 compliance. Thisfilter is the best selection for 8 kHz/16 kHz/voice.
For more information, contact QTIL.
8.2.3 DAC
The DAC consists of two high-quality DACs:■ Each DAC has a fourth-order Sigma-Delta converter.
■ Each DAC is a separate channel with identical functionality.
■ Each channel has an analog and a digital gain stage.
8.2.3.1 DAC sample rate selection
Each DAC supports the following sample rates:■ 8 kHz
■ 11.025 kHz
■ 16 kHz
■ 22.050 kHz
■ 32 kHz
■ 40 kHz
■ 44.1 kHz
■ 48 kHz
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8.2.3.2 DAC gain
The DAC outputs have two gain stages, a digital stage followed by an analog stage. The digital gain varies between-24 dB and 21.5 dB and the analog gain between 0 dB and -21 dB, giving a total range of -45 dB to 21.5 dB.Calls connected by the VM stream automatically select the distribution of gain within the DAC for best performance.Alternatively, the individual gain stages can be set.Table 8-2 and Table 8-3 list how the gain values are selected.
Table 8-2 DAC digital gain selection
Digital gain selection value DAC digital gain setting(dB) Digital gain selection value DAC digital gain setting
(dB)
0 0 8 -24
1 3.5 9 -20.5
2 6 10 -18
3 9.5 11 -14.5
4 12 12 -12
5 15.5 13 -8.5
6 18 14 -6
7 21.5 15 -2.5
Table 8-3 DAC analog gain selection
Analog gain selection value DAC analog gain setting(dB) Analog gain selection value DAC analog gain setting
(dB)
7 0 3 -12
6 -3 2 -15
5 -6 1 -18
4 -9 0 -21
8.2.3.3 DAC digital FIR filter
The DAC contains an integrated digital finite impulse response (FIR) filter with the following modes:■ A default long FIR filter for best performance at ≥ 44.1 kHz.
■ A short FIR to reduce latency.
■ A narrow FIR (a sharp roll-off at Nyquist) for G.722 compliance. Best for 8 kHz/16 kHz.
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8.2.4 Microphone bias generator
QCC3003 QFN contains an independent low-noise microphone bias generator. The microphone bias generator isrecommended for biasing electret condensor microphones.Figure 8-4 shows a typical biasing circuit for electret condenser microphones.
G-T
W-0
0129
80.1
.1C2R1
C1
Microphone Bias(MIC_BIAS)
LINE/MIC_AP
LINE/MIC_AN
MIC1+
Input Amplifier
Figure 8-4 Microphone biasing
The microphone bias generator provides a selectable output voltage of 1.8 V or 2.6 V nominal and derives its powerfrom VBAT or VOUT_3V3. No output capacitor is required.The bias resistor R1 should match the microphone load impedance, and typically is 2.2 kΩ. C1 and C2 are typically100/150 nF to give a bass roll-off to limit wind noise on the microphone.The mic bias generator has a maximum drop out of 300 mV, if VBAT drops below (selected output voltage – drop outvoltage), the output voltage will fall below specification. The generator will continue to operate but noise performancewill be impaired.
Related Information“Microphone bias generator” on page 71
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8.2.5 Line input
Figure 8-5 and Figure 8-6 show 2 circuits for line input operation and show connections for either differential orsingle-ended inputs.
G-T
W-0
0168
77.1
.3
C1
C2
LINE/MIC_AN
LINE/MIC_AP
C3
C4
LINE_BN
LINE_BP
Figure 8-5 Differential input
G-T
W-0
0168
78.1
.3
C1
C2
LINE/MIC_AP
LINE/MIC_AN
C1
C2
LINE_BP
LINE_BN
Figure 8-6 Single-ended input
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8.2.6 Output stage
The output stage digital circuitry converts the signal from 16 bit per sample, linear pulse code modulation (PCM) ofvariable sampling frequency to bit stream, which is fed into the analog output circuitry.The analog output circuit comprises a DAC, a buffer with gain-setting, a low pass filter, and a class AB output stageamplifier.Figure 8-7 shows that the output is available as a differential signal between SPKR_LN and SPKR_LP for the leftchannel, and between SPKR_RN and SPKR_RP for the right channel.
G-T
W-0
0055
37.1
.1
SPKR_LP
SPKR_LN
SPKR_RP
SPKR_RN
Figure 8-7 Speaker output
8.2.7 Mono operation
Mono operation is a single-channel operation of the stereo codec. The left channel represents the single monochannel for audio in and audio out. In mono operation, the right channel is the auxiliary mono channel for dual-monochannel operation.In single channel mono operation, disable the other channel to reduce power consumption.
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8.2.8 Sidetone
In some applications, it is necessary to implement sidetone. This sidetone function applies configurable gain to themicrophone signal and feeds it into the DAC stream. The sidetone routing selects the version of the microphonesignal from before or after the digital gain in the ADC interface and adds it to the output signal before or after thedigital gain of the DAC interface, see Figure 8-8.
G-T
W-0
0053
75.1
.1
Side Tone Route
Digital Input Analog Output
Digital Output Analog Input
Digital Gain
Demux
Mux
DAC
DAC Interface
Side Tone
Digital Gain
ADC
ADC Interface
Side Tone Route
Side Tone Gain
Figure 8-8 Sidetone
The ADC provides simple gain to the sidetone data. The gain values range from -32.6 dB to 12.0 dB in alternatingsteps of 2.5 dB and 3.5 dB, see Table 8-4.
Table 8-4 Sidetone gain
Value Sidetone gain Value Sidetone gain
0 -32.6 dB 8 -8.5 dB
1 -30.1 dB 9 -6.0 dB
2 -26.6 dB 10 -2.5 dB
3 -24.1 dB 11 0 dB
4 -20.6 dB 12 3.5 dB
5 -18.1 dB 13 6.0 dB
6 -14.5 dB 14 9.5 dB
7 -12.0 dB 15 12.0 dB
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8.2.9 Integrated digital IIR filter
QCC3003 QFN has a programmable digital filter integrated into the ADC channel of the codec. The filter is a 2-stage,second-order IIR and is for functions such as custom wind noise reduction. The filter also has optional direct current(DC) blocking.The filter has 10 configuration words in this order:■ 1 for gain value
■ 8 for coefficient values (b01, b02, a01, a02, b11, b12, a11, a12)
■ 1 for enabling and disabling the DC blocking
The gain and coefficients are all 12-bit two's complement signed integer with the format NN.NNNNNNNNNN.
NOTE The position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit.
For example:01.1111111111 = most positive number, close to 201.0000000000 = 100.0000000000 = 011.0000000000 = -110.0000000000 = -2, most negative number
Equation 8-1 shows the equation for the IIR filter.
Filter, H(z) = Gain ×1 + b01 z−1 + b02 z−2
1 + a01 z−1 + a02 z−2 ×1 + b11 z−1 + b12 z−2
1 + a11 z−1 + a12 z−2
Equation 8-1 IIR filter transfer function, H(z)
Equation 8-2 shows the equation for when the DC blocking is enabled.
Filter with DC Blocking, HDC (z) = H(z) × 1 − z−1
Equation 8-2 IIR filter plus DC blocking transfer function, HDC(z)
8.3 I²S1 interfaceQCC3003 QFN supports I²S input and output via the industry-standard I²S1 digital audio interface, left-justified orright-justified.
NOTE In this section, terms are defined as follows:■ I²S refers to the I²S1 interface.
■ SD_IN refers to I2S1_SD_IN.
■ SD_OUT refers to I2S1_SD_OUT.
■ WS refers to I2S1_WS.
■ SCK refers to I2S1_SCK.
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QCC3003 QFN also supports several alternative PCM data formats. For further details, contact QTIL. When in PCMmode, the following pin name to function mappings apply.
I²S pin PCM function
I2S1_SD_IN PCM_IN
I2S1_SD_OUT PCM_OUT
I2S1_WS PCM_SYNC
I2S1_SCK PCM_CLK
Figure 8-9 shows the timing diagram for the I²S interface.
G-T
W-0
0002
30.3
.2
WS
SCK
SD_IN/OUT
WS
SCK
SD_IN/OUT
WS
SCK
SD_IN/OUT
LSB
MSB LSB MSB LSB
MSB LSB MSB LSB
Left -justified Mode
Right -justified Mode
Left Channel Right Channel
Right ChannelLeft Channel
Left Channel Right Channel
MSB LSB MSB
I2 S Mode
Figure 8-9 Digital audio interface modes
The internal representation of audio samples within the QCC3003 QFN is 16-bit and data on SD_OUT is limited to16-bit per channel.
Table 8-5 Digital audio interface slave timing
Symbol Parameter Min Typ Max Unit
– SCK Frequency – – 6.2 MHz
– WS Frequency – – 96 kHz
tch SCK high time 80 – – ns
tcl SCK low time 80 – – ns
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Table 8-6 I²S slave mode timing
Symbol Parameter Min Typ Max Unit
tssu WS valid to SCK high set-up time 20 – – ns
tsh SCK high to WS invalid hold time 2.5 – – ns
topdSCK low to SD_OUT valid delaytime – – 20 ns
tisuSD_IN valid to SCK high set-uptime 20 – – ns
tihSCK high to SD_IN invalid holdtime 2.5 – – ns
G-T
W-0
0002
31.2
.2
SD_OUT
SD_IN
t
t
t
t
t
t
WS(Input)
SCK(Input)
ch
opd
ih
shssu
cl
isut
Figure 8-10 Digital audio interface slave timing
Table 8-7 Digital audio interface master timing
Symbol Parameter Min Typ Max Unit
– SCK Frequency – – 6.2 MHz
– WS Frequency – – 96 kHz
Table 8-8 I²S master mode timing parameters, WS and SCK as outputs
Symbol Parameter Min Typ Max Unit
tspd SCK low to WS valid delay time – – 39.27 ns
topd SCK low to WS valid delay time – – 18.44 ns
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Table 8-8 I²S master mode timing parameters, WS and SCK as outputs (cont.)
Symbol Parameter Min Typ Max Unit
tisuSD_IN valid to SCK high set-uptime 18.44 – – ns
tihSCK high to SD_IN invalid holdtime 0 – – ns
G-T
W-0
0002
32.2
.2
WS(Output)
SCK(Output)
SD_OUT
SD_IN
t isu t ih
topd
t spd
Figure 8-11 Digital audio interface master timing
QCC3003 QFN Data Sheet Audio interface
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9 Power control and regulation
The recommended configurations for power control and regulation on the QCC3003 QFN are:■ Dual-SMPS configuration using both 1.8 V and 1.35 V switch-mode regulators independently. This is the default
power control and regulation configuration for the QCC3003 QFN.■ A linear configuration using an external 1.8 V rail omitting both switch-mode power supply (SMPS) regulators.
Other combinations of switch-mode and low voltage drop-out (LDO) are possible, but with limitations. For moreinformation, contact QTIL.
Table 9-1 Recommended configurations for power control and regulation
SupplyConfiguration
RegulatorsSupply rail
Switch-mode VDD_AUXlinear
regulator
VDD_ANAlinear
regulator1.8 V 1.35 V 1.8 V 1.35 V
Dual-supplySMPS ON ON OFF OFF SMPS SMPS
Linear supply OFF OFF ON ON External LDO
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G-T
W-0
0168
70.1
.2
Charge Reference
Bypass Linear Regulator
Charger50 to 200 mA
Reference
1.8 V Switch-mode
Regulator
1.35 V Switch-mode
Regulator
VCHG
VBAT
Mic BiasMIC_BIAS
LX_1V35
LX_1V8
VOUT_3V3
3.3 V1.35 V1.8 V
Audio Driver
Audio Core
VDD_AUDIO_DRV_PADS2
VDD_AUDIO
Audio Circuits
VDD_AUX Regulator
VDD_ANA Regulator
I/O
Analogue and Auxiliary
Bluetooth
SENSE
IN
OUT
OUT
VDD_AUX
SENSE
OUT
OUT
VDD_ANA_RADIOSENSE
IN
SENSE
Auxiliary Circuits
IN
IN
Digital Core Circuits
VDD_DIGRegulator
OUT
SENSE
IN
VDD_DIGVREGIN_DIG
EN
EN
EN
EN
EN
EN
OUT
SENSE
VREGENABLE
VDD_AUX_1V8_PADS1
SMPS_1V35_SENSE
Figure 9-1 1.8 V and 1.35 V dual-supply switch-mode system configuration
QCC3003 QFN Data Sheet Power control and regulation
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9.1 Switch-mode regulatorsFor greater power efficiency, the QCC3003 QFN contains 2 switch-mode regulators:■ One to generate a 1.8 V supply rail with an output current of 185 mA.
■ One to generate a 1.35 V supply rail with an output current of 160 mA.
Related Information“1.8 V switch-mode regulator” on page 52“1.35 V switch-mode regulator” on page 53
9.1.1 1.8 V switch-mode regulator
QTIL recommends using the integrated switch-mode regulator to power the 1.8 V supply rail.Figure 9-2 shows that an external LC filter circuit of a low-resistance series inductor, L1 (4.7 μH), followed by a lowESR shunt capacitor, C3 (2.2 μF), is required between the LX_1V8 terminal and the 1.8 V supply rail. Connect the1.8 V supply rail and the VDD_AUDIO_DRV_PADS2 pin.
G-T
W-0
0168
71.1
.2
VDD_AUDIO_DRV_PADS2
LX_1V81.8 V Switch-mode
RegulatorSENSE
LX
L14.7 µH
C32.2 µF
1.8 V Supply Rail
VSS_SMPS_1V8
VBATVOUT_3V3
To 1.35 V Switch-mode Regulator Input
C12.2 µF
C22.2 µF
Figure 9-2 1.8 V switch-mode regulator output configuration
Minimize the series resistance of the tracks between the regulator input, VBAT and VOUT_3V3, ground terminals,the filter and decoupling components, and the external voltage source to maintain high-efficiency power conversionand low supply ripple.Ensure a solid ground plane between C1, C2, C3, and VSS_SMPS_1V8.Also minimize the collective parasitic capacitance on the track between LX_1V8 and the inductor L1, to maximizeefficiency.For the regulator to meet its specifications, it requires a total resistance of < 1.0 Ω (< 0.5 Ω recommended) for thefollowing:■ The track between the battery and VBAT.
■ The track between LX_1V8 and the inductor.
■ ESR of the inductor L1.
■ The track between the inductor, L1, and the sense point on the 1.8 V supply rail.
The following enable the 1.8 V switch-mode regulator:■ VREGENABLE pin
■ The QCC3003 QFN firmware with reference to PSKEY_PSU_ENABLES
■ VCHG pin
The switching frequency is adjustable by setting an offset from 4 MHz using PSKEY_SMPS_FREQ_OFFSET, whichalso affects the 1.35 V switch-mode regulator.
QCC3003 QFN Data Sheet Power control and regulation
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When the 1.8 V switch-mode regulator is not required, leave unconnected:■ The regulator input VBAT and VOUT_3V3
■ The regulator output LX_1V8
9.1.2 1.35 V switch-mode regulator
QTIL recommends using the integrated switch-mode regulator to power the 1.35 V supply rail.Figure 9-3 shows that an external LC filter circuit of a low-resistance series inductor L1 (4.7 μH), followed by a lowESR shunt capacitor, C3 (4.7 μF), is required between the LX_1V35 terminal and the 1.35 V supply rail. Connect the1.35 V supply rail and the SMPS_1V35_SENSE pin.
G-T
W-0
0146
15.2
.2
SMPS_1V35_SENSE
LX_1V351.35 V Switch-
mode RegulatorSENSE
LX
L14.7 µH
C34.7 µF
1.35 V Supply Rail
VSS_SMPS_1V35
VBATVOUT_3V3
To 1.8 V Switch-mode Regulator Input
C12.2 µF
C22.2 µF
Figure 9-3 1.35 V switch-mode regulator output configuration
Minimize the series resistance of the tracks between the regulator input, VBAT and VOUT_3V3, ground terminals,the filter and decoupling components, and the external voltage source to maintain high-efficiency power conversionand low supply ripple.Ensure a solid ground plane between C1, C2, C3, and VSS_SMPS_1V35.Also minimize the collective parasitic capacitance on the track between LX_1V35 and the inductor L1, to maximizeefficiency.For the regulator to meet its specifications, it requires a total resistance of < 1.0 Ω (< 0.5 Ω recommended) for thefollowing:■ The track between the battery and VBAT.
■ The track between LX_1V8 and the inductor.
■ ESR of the inductor L1.
■ The track between the inductor, L1, and the sense point on the 1.35 V supply rail.
The following enable the 1.35 V switch-mode regulator:■ VREGENABLE pin
■ The QCC3003 QFN firmware with reference to PSKEY_PSU_ENABLES
■ VCHG pin
The switching frequency is adjustable by setting an offset from 4 MHz using PSKEY_SMPS_FREQ_OFFSET, whichalso affects the 1.8 V switch-mode regulator.When the 1.35 V switch-mode regulator is not required, leave unconnected:■ The regulator input VBAT and VOUT_3V3
■ The regulator output LX_1V35
QCC3003 QFN Data Sheet Power control and regulation
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9.1.3 Inductor choice
Correct switch-mode power supply performance depends on inductor choice. A key parameter is the saturationcurrent of the inductor. As an inductor saturates, its effective inductance decreases significantly and the switchingcurrents increase further. This can eventually lead to:■ Poor regulator performance
■ RF interference
■ Possible instability
QTIL recommends inductor selection to ensure that the inductance reduction at 250 mA is less than 30% of nominalinductance. This is often stated as the inductor parameter Rated Current (L change) Max and the value is the currentat which the rated inductance has fallen by a specified percentage.
NOTE Some inductor manufacturers state the inductor's rated current as the temperature rise (DC current atwhich the inductor temperature increases by a specified temperature). This is not the same assaturation current.The saturation performance can be particularly poor with small package inductors.
Another key inductor parameter is the DC resistance, because high DC resistance in the inductor decreasesswitch‑mode power supply efficiency.
NOTE Pay attention to the frequency for which the inductor parameters are specified. The switch-mode powersupply operates at 4 MHz, so inductor parameters should be stated at 4 MHz or higher.
Within QTIL, all testing and characterization is carried out on boards using Taiyo-Yuden CB2012T4R7M parts in a0805 (2012 metric) package.
Table 9-2 Inductor choice, QTIL's testing and characterization
Parameter Min Typ Max Unit
Nominal inductance value (± 20% tolerance) 3.84 4.7 5.64 μH
Inductor Rdc for SMPS stability 0.1 0.25 1 Ω
Inductor Rdc for SMPS efficiency 0.1 0.25 0.4 Ω
Inductor saturation current (-30% reduction from the nominalinductor value) 250 – – mA
Inductor self-resonant frequency 10 – – MHz
Direct capacitance on SMPS output (including tolerance andde-rating) 1.5 2.2/4.7 10 μF
QCC3003 QFN Data Sheet Power control and regulation
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9.2 LDO linear regulatorsQCC3003 QFN contains 4 LDO linear regulators:■ 3.3 V bypass regulator.
■ 0.85 V to 1.25 V VDD_DIG linear regulator.
■ 1.35 V VDD_AUX linear regulator.
■ 1.35 V VDD_ANA linear regulator.
Related Information“Bypass LDO linear regulator” on page 55“Low-voltage VDD_DIG linear regulator” on page 55“Low-voltage VDD_AUX linear regulator” on page 55“Low-voltage VDD_ANA linear regulator” on page 55
9.2.1 Bypass LDO linear regulator
The integrated bypass LDO linear regulator provides a 3.3 V supply rail and is an alternative supply rail to the batterysupply. This is especially useful when the battery is discharged and the QCC3003 QFN needs to power up. The inputvoltage should be between 4.25 V and 6.5 V.Externally decouple the output of this regulator using a low ESR multilayer ceramic (MLC) capacitor of a minimum2.2 μF to the VOUT_3V3 pin.The regulator is enabled when VCHG rises above 3V (typical).
Related Information“Example application schematic” on page 61
9.2.2 Low-voltage VDD_DIG linear regulator
The integrated low-voltage VDD_DIG linear regulator powers the digital circuits on QCC3003 QFN. Externallydecouple the output of this regulator using a low ESR 470 nF MLC capacitor.
9.2.3 Low-voltage VDD_AUX linear regulator
The integrated low-voltage VDD_AUX linear regulator optionally provides a 1.35 V auxiliary supply rail when the1.35 V switch-mode regulator is not used. When using the integrated low-voltage VDD_AUX linear regulator,externally decouple the output of this regulator using a low ESR 470 nF MLC capacitor connected to the VDD_AUXpin.
9.2.4 Low-voltage VDD_ANA linear regulator
The integrated low-voltage VDD_ANA linear regulator is optionally available to power the 1.35 V analog supply railwhen the 1.35 V switch-mode regulator is not used. When using the integrated low-voltage VDD_ANA linearregulator, externally decouple the output of this regulator using a 2.2 μF low ESR MLC capacitor connected to theVDD_ANA pin.
QCC3003 QFN Data Sheet Power control and regulation
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9.3 Voltage regulator enable pinWhen the integrated regulators are used, the voltage regulator enable pin, VREGENABLE, enables the followingregulators:■ 1.8 V switch-mode regulator
■ 1.35 V switch-mode regulator
■ Low-voltage VDD_DIG linear regulator
■ Low-voltage VDD_AUX linear regulator
An internal pull-down device (typically 100 kΩ) on the VREGENABLE pin can be disabled by thePSKEY_VREG_ENABLE_STRONG_PULL PS Key.QCC3003 QFN boots up when the voltage regulator enable pin is pulled high typically for 10 to 15 ms, enabling theregulators. The firmware then latches the regulators on. The voltage regulator enable pin can then be released.The status of the VREGENABLE pin is available to firmware through an internal connection. VREGENABLE alsoworks as an input line.
NOTE VREGENABLE should be asserted after the VBAT supply when VREGENABLE is not used as apower‑on button.
9.4 External regulators and power sequencingQTIL recommends that the integrated regulators supply the QCC3003 QFN and it is configured based on theinformation in this data sheet.If any of the supply rails for the QCC3003 QFN are supplied from an external regulator, then its parameters shouldmatch or be better than the internal regulator available on QCC3003 QFN.
NOTE The internal regulators including both the switch-mode and LDO linear regulators are not recommendedfor powering external circuitry other than that shown in the example application schematics.For information about power sequencing of external regulators to supply the QCC3003 QFN, contactQTIL.
Related Information“Electrical characteristics” on page 64“Example application schematic” on page 61
9.5 ResetQCC3003 QFN is reset from several sources:■ Power-on reset
■ USB charger attach reset
■ Software configured watchdog timer
At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate.
NOTE Reset can also be triggered by a UART break symbol if:■ Host interface is any UART transport
And■ PSKEY_HOSTIO_UART_RESET_TIMEOUT is set to a value more than 1000
QCC3003 QFN Data Sheet Power control and regulation
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A reboot function is also available under software control.
9.5.1 Digital pin states on reset
Table 9-3 Pin states on reset
Pin name I/O type Full chip reset Pin name I/O type Full chip reset
USB_DP Digitalbidirectional Tristate PIO[4] Digital
bidirectional PDW
USB_DN Digitalbidirectional Tristate PIO[5] Digital
bidirectional PDW
PIO[0] Digitalbidirectional PUS PIO[6] Digital
bidirectional PDS
PIO[1] Digitalbidirectional PUS PIO[7] Digital
bidirectional PDS
PIO[2] Digitalbidirectional PDW PIO[8] Digital
bidirectional PUS
PIO[3] Digitalbidirectional PDW PIO[9] Digital
bidirectional PDS
NOTE PUS – Strong pull-upPDS – Strong pull-downPUW – Weak pull-upPDW – Weak pull-down
9.6 Automatic reset protectionQCC3003 QFN includes an automatic reset protection circuit that restarts the QCC3003 QFN when an unexpectedreset occurs, for example, electrostatic discharge (ESD) strike. This reset protection circuit automatically restarts theQCC3003 QFN and enables the application to restore previous operation.
QCC3003 QFN Data Sheet Power control and regulation
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10 Battery charger
10.1 Battery charger hardware operating modesThe battery charger hardware is controlled by the on-chip application. The battery charger has 5 modes:■ Disabled
■ Trickle charge
■ Fast charge
■ Standby: fully charged or float charge
■ Error: charging input voltage, VCHG, is too low
Transitions between the trickle charge, fast charge and standby modes are triggered by changes in battery voltageand charger current.
Table 10-1 Battery charger operating modes determined by battery voltage and charger current
Mode Battery charger enabled VBAT
Disabled No X
Trickle charge Yes > 0 and < Vfast
Fast charge Yes > Vfast and < Vfloat
Standby Yes Iterm a and > (Vfloat - Vhyst)
Error Yes > (VCHG - 50mV)a Iterm is approximately 10% of Ifast for a given Ifast setting
Figure 10-1 shows the mode-to-mode transition voltages.
G-T
W-0
0055
83.3
.2
Battery voltage
Cha
rge
curr
ent
Vfast
Ifast
ItermVhystItrickle
Vfloat
Trickle charge mode
Fast charge mode Constant current
Fast charge mode Constant voltage
Standby mode
Figure 10-1 Battery charger mode-to-mode transition diagram
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The transition between modes can occur at any time.
NOTE The battery voltage remains constant in fast charge constant voltage mode, the curved line on figure isfor clarity only.
10.1.1 Disabled mode
In the disabled mode the battery charger is fully disabled and does not actively draw or deliver current on any of itsterminals.
10.1.2 Trickle charge mode
In the trickle charge mode, when the voltage on VBAT is lower than the Vfast threshold, a current of approximately10% of the fast charge current, Ifast, is sourced from the VBAT pin.The Vfast threshold detection has hysteresis to prevent the charger from oscillating between modes.
10.1.3 Fast charge mode
When the voltage on VBAT is greater than Vfast, the current sourced from the VBAT pin increases to Ifast. Ifast isbetween 10 mA and 200 mA set by PS Key or a VM trap. In addition, Ifast is calibrated in production test to correct forprocess variation in the charger circuit.The current is held constant at Ifast until the voltage at VBAT reaches Vfloat, then the charger reduces the currentsourced to maintain a constant voltage on the VBAT pin.When the current sourced is below the termination current, Iterm, the charging stops and the charger enters standbymode. Iterm is typically 10% of the fast charge current.
10.1.4 Standby mode
When the battery is fully charged, the charger enters standby mode, and battery charging stops. The battery voltageon the VBAT pin is monitored, and when it drops below a threshold set at Vhyst below the final charging voltage, Vfloat,the charger re-enters fast charge mode.
10.1.5 Error mode
The charger enters the error mode if the voltage on the VCHG pin is too low to operate the charger correctly (VBAT isgreater than VCHG - 50 mV (typical)).In this mode, charging is stopped. The battery charger does not require a reset to resume normal operation.
10.2 Battery charger trimming and calibrationThe battery charger default trim values are written by QTIL into non-volatile memory when each IC is produced. QTILprovides various PS Keys for overriding the default trims.
10.3 On-chip application battery charger controlThe on-chip application charger code has overall supervisory control of the battery charger and is responsible for:■ Responding to charger power connection/disconnection events
■ Monitoring the temperature of the battery
■ Monitoring the time spent in the various charge states
QCC3003 QFN Data Sheet Battery charger
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■ Enabling/disabling the charger circuitry based on the monitored information
■ Driving the user-visible charger status light-emitting diode (LED)(s)
10.4 Battery charger firmware and PS KeysThe battery charger firmware sets up the charger hardware based on the PS Key settings and traps called from theon-chip application charger code.For more information on the QCC3003 QFN, including details on setting up, calibrating, trimming, and the PS Keys,see the Lithium Polymer Battery Charger Calibration and Operation for CSR8670.
QCC3003 QFN Data Sheet Battery charger
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11 Example application schematic
PIO[8] / UART_RTS# 43PIO[9] / UART_CTS#
G-T
W-0
0169
62.2
.2
26 MHzXT1
GR
EE
N
D103
Li+ CELL
VBAT
3.7VCON101
1V8
VBAT
1V81V8
F2S102
F3S101
F4S100
RE
D D102
BLU
E
D101
1V81V8
VOL-S104
VOL+S103
LED
_0
LED
_1
LED
_2
LED outputs
VBUS
GND 5ID 4D+ 3D- 2VBUS 1
GN
D6
GN
D7
USB MINI-BCON100
USB_PUSB_N
BAT54CD100
VBUS
VBATVBUS
3V3_USB
VBAT 1V8_SMPS
MFBS1
4u7L2
1V35_SMPS
STARSP100
PIO_0
LED_1LED_0
PIO_1
PIO_2PIO_3PIO_4PIO_5
PIO_6PIO_7PIO_8PIO_9
AIO_0
USB_PUSB_N
SPI_PCM#
LED_2
2u2C1
2u2C2
2u2C3
2u2C4
10nC5
10nC6
470nC10
15pC8
PIO / UART
PIO / Debug SPI / I2S1
Analog input / output
USB (12 Mb/s)
Optional ancilliary circuitsUSB / Charger Interface Lithium Polymer Battery
(battery protection built in)Typical LEDs and Buttons
Ensure the following tracks have good low impedance connections
PCB Layout Notes
(no via share and short thick tracks)VSS_SMPS_1V8 to Battery GroundVSS_SMPS_1V35 to Battery Ground
LX_1V8 to InductorLX_1V35 to Inductor
L1 to C4 trackL2 to C7 track
VBAT to Battery and C2 - should be <1ohm from batteryVCHG to charger connector and C1
VDD_DIG to Ground
Suggest analog and digital grounds are separated if possible
QTIL recommend low Rdc inductors (<0.5R) for L1 & L2 for optimum power efficiencyFor example Taiyo Yuden CB2012T4R7M
4u7L1
and star connected near VSS_AUDIO as shownEnsure analog tracks stay over Analog ground as much as possible
220R0402 R101
330R0402 R102
330R0402 R103
PIO
_n
PIO
_n
PIO
_n
PIO
_n
PIO
_n
Ensure the following components are placed next to QCC3003 and have good low impedance connections both to signal and GND
C2 and C3
C4 to VSS_SMPS_1V8C7 to VSS_SMPS_1V35
SPI_PCM# high for SPI. Low for all other functions
Ensure good low impedance ground return path through GND plane for SMPSUcurrent from C4 to VSS_SMPS_1V8 and C7 to VSS_SMPS_1V35 back to C3 & C4
2u2C9
4u7C7
Ensure routing from L2 to pin 39 and from L2 to C8/9 & pins 11 & 13 are kept separate
10kTHERM
AIO_0
Battery temperature sensor
9k10402
R1001V35_SMPS
10n0201 C102
S
D
G
Q1
PIO_n
15nH
L4
MIC
_1N
MIC
_1P
MIC
_BIA
S
SPK
R_L
NS
PKR
_LP
SPKR
_RN
SPKR
_RP
MIC_1
15pC17
Speakers (16 to 32 Ohm)Left RightMicrophone input
2u2C12
2k2
R1
100nC14
100nC13
CE 1SO/SIO12WP/SIO23
VSS 4
SI/SIO05SCK 6
HOLD/SIO37
VDD8U100
SPI Flash
10n
C1011V8_SMPS
PIO_n (odd)
DigitalMic(s)
PIO_n (even)CLOCK
DATA
1V8_SMPS
QSPI_FLASH_CS#
QSPI_FLASH_CS#QSPI_FLASH_CLKQSPI_IO0QSPI_IO1QSPI_IO2QSPI_IO3
QSPI_FLASH_CLK
Quad SPI Flash
VDD
_AU
DIO
1
VD
D_D
IG_M
EM29
QCC3003
VDD
_AU
X11
VR
EGEN
ABLE
31
VC
HG
32
VBAT
35
LX_1
V834
BYPASS REG
CHARGER
DIG LDO
AUX LDO
ANA LDO
VSS
_SM
PS
_1V3
538
3.3 V
1.35 V
1.35 V
VREG
IN_D
IG30
VBAT 1.8 V SMPS
1.35 V SMPS
LX_1
V35
37
SM
PS
_1V3
5_S
EN
SE39
VD
D_A
UX
_1V
8_P
AD
S112
52-lead, 6 x 6 mm 0.4 mm pitch QFN
1.35 V
VSS
_SM
PS
_1V8
33
47
XTAL_IN 14
XTAL_OUT 13
AIO[0] 15
LED[1] 27LED[0] 28
LED[2] 48
USB_P 41USB_N 40
QSPI_FLASH_CS# 17
QSPI_IO[2] 18QSPI_IO[3] 16
QSPI_IO[0] 21QSPI_IO[1] 25
VDD
_AU
DIO
_DR
V_PA
DS
26
GN
D P
ADD
LE53
QSPI_FLASH_CLK 20
PIO[4] / I2S1_WS / SPI_CS# 19PIO[5] / I2S1_SCK / SPI_CLK 26
SPI_PCM# 23
PIO[3] / I2S1_SD_OUT / SPI_MISOPIO[2] / I2S1_SD_IN / SPI_MOSI
PIO[6] 42PIO[1] / UART_TX 45PIO[0] / UART_RX 44
VDD
_AN
A_R
ADIO
10
VOU
T_3V
336
MIC
_BIA
S52
AU_R
EF51
MIC BIAS
SPKR
_RN
4SP
KR_R
P5
SPK
R_L
N7
SPK
R_L
P8
LIN
E/M
IC_A
P49
LIN
E/M
IC_A
N50
LIN
E_B
P
LIN
E_B
N
VDD_AUX
VDD_PADS1
VDD_PADS1
VDD_PADS2
VDD_PADS1
LED pad Vmax = VBAT
VDD_PADS2
100nC11
23
PIO[7] 46
24 22
BT_RFANT 2 OUT IN 4
3 GND GND 1
2.45 GHz
U2
Bluetooth RF
9 BT_RF
Figure 11-1 QCC3003 QFN example application schematic
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G-T
W-0
0169
63.2
.2
26 MHzXT1
LED outputs
15nH
L4
STARSP100
MIC
_1N
MIC
_1P
MIC_BIAS
SPKR
_LN
SPKR
_LP
SPKR
_RN
SPKR
_RP
PIO_0
LED_1LED_0
PIO_1
PIO_2PIO_3PIO_4PIO_5
PIO_6PIO_7PIO_8PIO_9
AIO_0
SPI_PCM#
LED_2
MIC_1
FR_TBTNA OUT2 IN 4
GND 1GND3
2.45 GHz
U2
2u2C4
470nC10
15pC17
PIO / UART
PIO / Debug SPI / I2S1
Analog input / output
Bluetooth RF
Speakers (16 to 32 Ohm)Left RightMicrophone input
2u2C12
2k2
R1
SPI_PCM# high for SPI. Low for all other functions
Single 1.8 V only supply. No USB, No switchmodes
GND
VBAT & VCHG grounded
1V8_INPUT
470nC6
GNDGND GND GND
100nC5
GND
1V35
NOTE: With 1.8 V input it is not possible to maintain internal mic bias performance,so use of an external mic bias supply is recommended if required.
100nC14
100nC13
100nC3
15pC8
2u2C9
CE 1SO/SIO12WP/SIO23
VSS 4
SI/SIO05SCK 6
HOLD/SIO37
VDD8U100
SPI Flash
10n
0201
C101QSPI_FLASH_CS#
QSPI_FLASH_CS#QSPI_FLASH_CLKQSPI_IO0QSPI_IO1QSPI_IO2QSPI_IO3
QSPI_FLASH_CLK
Quad SPI Flash
1V8_INPUT
VDD
_AU
DIO
1
VD
D_D
IG_M
EM29
BT_RF9
QCC3003
VDD
_AU
X11
VR
EGEN
ABLE
31
VC
HG
32
VBAT
35
LX_1
V834
BYPASS REG
CHARGER
DIG LDO
AUX LDO
ANA LDO
VSS
_SM
PS
_1V3
538
3.3 V
1.35 V
1.35 V
VREG
IN_D
IG30
VBAT 1.8 V SMPS
1.35 V SMPS
LX_1
V35
37
SM
PS
_1V3
5_S
EN
SE39
VD
D_A
UX
_1V
8_PA
DS1
1252-lead, 6 x 6 mm 0.4 mm pitch QFN
1.35 V
VSS
_SM
PS
_1V8
33
XTAL_IN 14
XTAL_OUT 13
AIO[0] 15
LED[1] 27LED[0] 28
LED[2] 48
USB_P 41USB_N 40
QSPI_FLASH_CS# 17
QSPI_IO[2] 18QSPI_IO[3] 16
QSPI_IO[0] 21QSPI_IO[1] 25
VDD
_AU
DIO
_DR
V_P
ADS2
6
GN
D P
ADD
LE53
QSPI_FLASH_CLK 20
PIO[2] / I2S1_SD_IN / SPI_MOSI 24PIO[3] / I2S1_SD_OUT / SPI_MISO 22
PIO[4] / I2S1_WS / SPI_CS# 19PIO[5] / I2S1_SCK / SPI_CLK 26
SPI_PCM# 23
PIO[0] / UART_RX 44PIO[1] / UART_TX 45
PIO[6] 47PIO[7] 42
PIO[8] / UART_RTS# 46PIO[9] / UART_CTS# 43
VDD
_AN
A_R
ADIO
10
VOU
T_3V
336
MIC
_BIA
S52
AU_R
EF51
MIC BIAS
SPKR
_RN
4SP
KR_R
P5
SPKR
_LN
7SP
KR_L
P8
MIC
_AP
49
MIC
_AN
50
MIC
_BP
3
MIC
_BN
2
VDD_AUX
VDD_PADS1
VDD_PADS1
VDD_PADS2
VDD_PADS1
LED pad Vmax = VBAT
VDD_PADS2
100nC11
FDV301N
S
D
G
Q1470nC19
GNDGND
VREGENABLE
VREGENABLE delay circuitVREGENABLE requires to be asserted ~10ms
after the system supply has risen in this configuration
This circuit can be used to providethe required delay.
or equivalent
47k
R3
47kR4
In this configuration set PSKEY_VREG_ENABLE_STRONG_PULLto FALSE to disable the strong pull down on VREGENABLE.
In this configuration set PSKEY_PSU_ENABLESto 0xC to disable SMPS and enable LDO's
Figure 11-2 Single 1.8 V only supply, with no USB or SMPSs
QCC3003 QFN Data Sheet Example application schematic
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G-T
W-0
0169
64.2
.2
26 MHzXT1
LED outputs
15nH
L4
STARSP100
MIC
_1N
MIC
_1P
MIC
_BIA
S
SPKR
_LN
SPKR
_LP
SPKR
_RN
SPKR
_RP
PIO_0
LED_1LED_0
PIO_1
PIO_2PIO_3PIO_4PIO_5
PIO_6PIO_7PIO_8PIO_9
AIO_0
SPI_PCM#
LED_2
MIC_1
FR_TBTNA OUT2 IN 4
GND 1GND3
2.45 GHz
U2
2u2C3
470nC10
15pC17
PIO / UART
PIO / I2S1 / Debug SPI
Bluetooth RF
Speakers (16 to 32 Ohm)Left RightMicrophone input
2u2C12
2k2
R1
SPI_PCM# high for SPI. Low for all other functions
Single 3.3 V only supply. USB, Dual switchmodes
3V3_INPUT
GND GND
1V8_SMPS
2u2C4
10nC5
4u7L1
GND
4u7L2
1V35_SMPS
10nC6
4u7C7
USB_PUSB_N
Analog input / output
USB (12 Mb/s)
2u2C1
GND
100nC14
100nC13
CE 1SO/SIO12WP/SIO23
VSS 4
SI/SIO05SCK 6
HOLD/SIO37
VDD8U100
SPI Flash
10n
C1011V8_SMPS
QSPI_FLASH_CS#
QSPI_FLASH_CS#QSPI_FLASH_CLKQSPI_IO0QSPI_IO1QSPI_IO2QSPI_IO3
QSPI_FLASH_CLK
Quad SPI Flash
15pC8
2u2C9
VDD
_AU
DIO
1
VD
D_D
IG_M
EM29
BT_RF9
QCC3003
VDD
_AU
X11
VR
EGEN
ABLE
31
VC
HG
32
VBAT
35
LX_1
V834
BYPASS REG
CHARGER
DIG LDO
AUX LDO
ANA LDO
VSS
_SM
PS
_1V3
538
3.3 V
1.35 V
1.35 V
VREG
IN_D
IG30
VBAT 1.8 V SMPS
1.35 V SMPS
LX_1
V35
37
SM
PS
_1V3
5_S
EN
SE39
VD
D_A
UX
_1V
8_PA
DS1
1252-lead, 6 x 6 mm 0.4 mm pitch QFN
1.35 V
VSS
_SM
PS
_1V8
33
XTAL_IN 14
XTAL_OUT 13
AIO[0] 15
LED[1] 27LED[0] 28
LED[2] 48
USB_P 41USB_N 40
QSPI_FLASH_CS# 17
QSPI_IO[2] 18QSPI_IO[3] 16
QSPI_IO[0] 21QSPI_IO[1] 25
VDD
_AU
DIO
_DR
V_P
ADS2
6
GN
D P
ADD
LE53
QSPI_FLASH_CLK 20
PIO[2] / I2S1_SD_IN / SPI_MOSI 24PIO[3] / I2S1_SD_OUT / SPI_MISO 22
PIO[4] / I2S1_WS / SPI_CS# 19PIO[5] / I2S1_SCK / SPI_CLK 26
SPI_PCM# 23
PIO[0] / UART_RX 44PIO[1] / UART_TX 45
PIO[6] 47PIO[7] 42
PIO[8] / UART_RTS# 46PIO[9] / UART_CTS# 43
VDD
_AN
A_R
ADIO
10
VOU
T_3V
336
MIC
_BIA
S52
AU_R
EF51
MIC BIAS
SPKR
_RN
4SP
KR_R
P5
SPKR
_LN
7SP
KR_L
P8
MIC
_AP
49
MIC
_AN
50
MIC
_BP
3
MIC
_BN
2
VDD_AUX
VDD_PADS1
VDD_PADS1
VDD_PADS2
VDD_PADS1
LED pad Vmax = VBAT
VDD_PADS2
100nC11
FDV301N
S
D
G
Q1
47k
R3
100kR4
470nC19
GNDGND
VREGENABLE
VREGENABLE delay circuit
after the system supply has risen in this configuration
This circuit can be used to providethe required delay.
or equivalent
VREGENABLE requires to be asserted ~10ms
In this configuration set PSKEY_VREG_ENABLE_STRONG_PULLto FALSE to disable the strong pull down on VREGENABLE.
Figure 11-3 Single 3.3 V only supply, with USB and dual SMPSs
QCC3003 QFN Data Sheet Example application schematic
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12 Electrical characteristics
12.1 Absolute maximum ratings
Rating Min Max Unit
Storage temperature -40 105 °C
Supply voltage
Charger VCHG -0.4 6.50 V
LEDs LED[2:0] -0.4 4.40 V
3.3 V 3V3_USB -0.4 3.60 V
BatteryVBAT -0.4 4.40 V
VREGENABLE -0.4 4.40 V
PIOVDD_AUX_1V8_PADS1 -0.4 1.95 V
VDD_AUDIO_DRV_PADS2 -0.4 1.95 V
1.35 V
SMPS_1V35_SENSE -0.4 1.45 V
VDD_AUDIO -0.4 1.45 V
VREGIN_DIG -0.4 1.95 V
VDD_ANA_RADIO -0.4 1.45 V
Other terminal voltages VSS - 0.4 VDD + 0.4 ≤ 3.60 a Va VDD is the VDD_PADS supply domain for this I/O. Voltage must not exceed 3.6 V on any I/O.
Related Information“Device terminal functions” on page 18
12.2 Recommended operating conditions
Rating Min Typ Max Unit
Operating temperature range -40 20 85 °C
Supply voltage
ChargerVCHG, 4.20 V float setting 4.75 / 3.10 a 5.00 6.50 V
VCHG, 4.35 V float setting 4.90 / 3.10 b 5.00 6.50 V
LEDs LED[2:0] 1.10 3.70 4.30 V
3.3 V VOUT_3V3 3.10 3.30 3.60 V
BatteryVBAT 0 3.70 4.30 V
VREGENABLE 0 3.70 4.25 V
PIOVDD_AUX_1V8_PADS1 1.70 1.80 1.95 V
VDD_AUDIO_DRV_PADS2 1.70 1.80 1.95 V
1.35 V SMPS_1V35_SENSE 1.30 1.35 1.45 V
VDD_AUDIO 1.30 1.35 1.45 V
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Rating Min Typ Max Unit
VREGIN_DIG 1.30 1.35 or 1.80 c 1.95 V
VDD_ANA_RADIO 1.30 1.35 1.40 Va Reduced specification if VCHG - VBAT < 0.55 V. Full specification > 4.75 V.b Reduced specification if VCHG - VBAT < 0.55 V. Full specification > 4.90 V.c Typical value depends on power supply configuration.
Related Information“Low-voltage VDD_DIG linear regulator” on page 67
12.3 Input/Output terminal characteristicsFor all I/O terminal characteristics:
■ Current drawn into a pin is defined as positive.
■ Current supplied out of a pin is defined as negative.
12.3.1 Regulators available for external use■ 1.8 V switch-mode regulator
■ Combined 1.8 V and 1.35 V switch-mode regulator
■ Bypass LDO regulator
12.3.1.1 1.8 V switch-mode regulator
1.8 V switch-mode regulator Min Typ Max Unit
Input voltage 2.80 3.70 4.40 V
Output voltage 1.70 1.80 1.90 V
Normal operation
Transient settling time – 30 – μs
Load current – – 185 mA
Current available for external use, audio with 16 Ω load a 25 – – mA
Peak conversion efficiency b – 90 – %
Switching frequency – 4.00 – MHz
Inductor saturation current (-30% reduction from the nominal inductor value) 250 – – mA
Inductor ESR 0.1 0.3 1.0 Ω
Low-power mode, automatically entered in Deep Sleep
Transient settling time – 200 – μs
Load current 0.005 – 5 mA
Current available for external use 5 – – mA
Peak conversion efficiency – 85 – %
Switching frequency 100 – 200 kHza More current available for audio loads above 16 Ω.b Conversion efficiency depends on inductor selection.
QCC3003 QFN Data Sheet Electrical characteristics
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12.3.1.2 Bypass LDO regulator
Normal operation Min Typ Max Unit
Input voltage 4.25 / 3.10 a 5.00 6.50 V
Output voltage (Vin > 4.75 V) 3.00 3.30 3.60 V
Output current (Vin > 4.75 V) b – – 250 mAa Minimum input voltage of 4.25 V is required for full specification, regulator operates at reduced load current from 3.1 V.b This regulator starts in a low-power mode, and is not designed to power external circuitry other than that shown in the
example application schematics.
Related Information“Example application schematic” on page 61
12.3.2 Regulators for internal use only■ 1.35 V switch-mode regulator
■ Low-voltage VDD_DIG linear regulator
■ Low-voltage VDD_AUX linear regulator
■ Low-voltage VDD_ANA linear regulator
12.3.2.1 1.35 V switch-mode regulator
1.35 V switch-mode regulator Min Typ Max Unit
Input voltage 2.80 3.70 4.40 V
Output voltage 1.30 1.35 1.40 V
Normal operation
Transient settling time – 30 – μs
Load current – – 160 mA
Current available for external use – – 0 mA
Peak conversion efficiency a – 88 – %
Switching frequency – 4.00 – MHz
Inductor saturation current (-30% reduction from the nominal inductor value) 250 – – mA
Inductor ESR 0.1 0.3 1.0 Ω
Low-power mode, automatically entered in Deep Sleep
Transient settling time – 200 – μs
Load current 0.005 – 5 mA
Current available for external use – – 0 mA
Peak conversion efficiency – 85 – %
Switching frequency 100 – 200 kHza Conversion efficiency depends on inductor selection.
QCC3003 QFN Data Sheet Electrical characteristics
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12.3.2.2 Low-voltage VDD_DIG linear regulator
Normal operation Min Typ Max Unit
Input voltage 1.30 1.35 or 1.80 1.95 V
Output voltage a 0.80 0.90 / 1.20 1.25 V
Internal load current – – 80 mAa Output voltage level is software controlled.
12.3.2.3 Low-voltage VDD_AUX linear regulator
Normal operation Min Typ Max Unit
Input voltage 1.70 1.80 1.95 V
Output voltage 1.30 1.35 1.45 V
Internal load current – – 5 mA
12.3.2.4 Low-voltage VDD_ANA linear regulator
Normal operation Min Typ Max Unit
Input voltage 1.70 1.80 1.95 V
Output voltage 1.30 1.35 1.45 V
Internal load current – – 60 mA
12.3.3 Regulator enable
VREGENABLE,switching threshold Min Typ Max Unit
Rising threshold - - 1.0 V
12.3.4 Battery charger
Battery charger Min Typ Max Unit
Input voltage, VCHG, 4.20 V float setting 4.75 / 3.10 a 5.00 6.50 V
Input voltage, VCHG, 4.35 V float setting 4.90 / 3.10 b 5.00 6.50 Va Reduced specification if VCHG - VBAT < 0.55 V. Full specification > 4.75 V.b Reduced specification if VCHG - VBAT < 0.55 V. Full specification > 4.90 V.
Trickle charge mode Min Typ Max Unit
Charge current Itrickle, as percentage of fast charge current 8 10 12 %
Vfast rising threshold – 2.9 – V
Vfast rising threshold trim step size – 0.1 – V
Vfast falling threshold – 2.8 – V
QCC3003 QFN Data Sheet Electrical characteristics
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Fast charge mode Min Typ Max Unit
Charge current duringconstant current mode, Ifast
Maximum charge setting(VCHG - VBAT > 0.55 V) 194 200 206 mA
Minimum charge setting(VCHG - VBAT > 0.55 V) – 10 – mA
Reduced headroom chargecurrent, as a percentage ofIfast
(VCHG - VBAT < 0.55 V) 50 – 100 %
Charge current step size – 10 – mA
Vfloat threshold, 4.20 V 4.16 4.20 4.24 V
Vfloat threshold, 4.35 V 4.31 4.35 4.39 V
Charge termination current Iterm, as percentage of Ifast 7 10 20 %
Standby mode Min Typ Max Unit
Voltage hysteresis on VBAT, Vhyst 100 – 150 mV
Error charge mode Min Typ Max Unit
Headroom a error falling threshold – 50 – mVa Headroom = VCHG - VBAT
12.3.5 USB
USB Min Typ Max Unit
VOUT_3V3 for correct USB operation 3.1 3.3 3.6 V
Input threshold
VIL input logic level low - - 0.3 xVOUT_3V3 V
VIH input logic level high 0.7 xVOUT_3V3 - - V
Output voltage levels to correctly terminated USB cable
VOL output logic level low 0 - 0.2 V
VOH output logic level high 2.8 - VOUT_3V3 V
12.3.6 Stereo codec: analog-to-digital converter
Analog-to-digital converter
Parameter Conditions Min Typ Max Unit
Resolution - - - 16 Bits
Input sample rate,Fsample
- 8 - 48 kHz
Maximum ADC inputsignal amplitude 0 dB = 1600 mVpk-pk 13 - 2260 mVpk-pk
SNR fin = 1 kHzFsample
8 kHz - 94.0 - dB
QCC3003 QFN Data Sheet Electrical characteristics
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Analog-to-digital converter
Parameter Conditions Min Typ Max UnitB/W = 20 Hz→Fsample/2 (20 kHzmax)A - Weighted total harmonicdistortion plus noise (THD+N) <0.1%1.6 Vpk-pk input
16 kHz - 93.3 - dB
32 kHz - 93.1 - dB
44.1 kHz - 93.3 - dB
48 kHz - 92.8 - dB
THD+N
fin = 1 kHzB/W = 20 Hz→Fsample/2 (20 kHzmax)1.6 Vpk-pk input
Fsample
8 kHz - 0.0041 - %
48 kHz - 0.0080 - %
Digital gain Digital gain resolution = 1/32 -24 - 21.5 dB
Analog gainPre-amplifier setting = 0 dB, 9 dB, 21 dBor 30 dBAnalog setting = -3 dB to 12 dB in 3 dB steps
-3 - 42 dB
Stereo separation (crosstalk) - -87.3 - dB
12.3.7 Stereo codec: digital-to-analog converter
Digital-to-analog converter
Parameter Conditions Min Typ Max Unit
Resolution - - - 16 Bits
Output samplerate, Fsample
- 8 - 48 kHz
SNR
fin = 1 kHzB/W = 20 Hz → 20kHz A - WeightedTHD+N < 0.1%0 dBFS input
Fsample Load
48 kHz 100 kΩ - 96.4 - dB
48 kHz 32 Ω - 96.3 - dB
48 kHz 16 Ω - 96.2 - dB
THD+Nfin = 1 kHzB/W = 20 Hz → 20kHz 0 dBFS input
Fsample Load
8 kHz 100 kΩ - 0.0022 - %
8 kHz 32 Ω - 0.0022 - %
8 kHz 16 Ω - 0.0023 - %
48 kHz 100 kΩ - 0.0030 - %
48 kHz 32 Ω - 0.0031 - %
48 kHz 16 Ω - 0.0033 - %
Digital gain Digital gain resolution = 1/32 -24 - 21.5 dB
Analog gain Analog gain resolution = 3 dB -21 - 0 dB
Output voltage Full-scale swing (differential) - - 778 mVrms
Stereo separation (crosstalk) - -90.0 - dB
QCC3003 QFN Data Sheet Electrical characteristics
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12.3.8 Digital
Digital terminals Min Typ Max Unit
Input voltage
VIL input logic level low -0.4 – 0.4 V
VIH input logic level high 0.7 x VDD – VDD + 0.4 V
Tr/Tf – – 25 ns
Output voltage
VOL output logic level low, lOL = 4.0 mA – – 0.4 V
VOH output logic level high, lOH = -4.0 mA 0.75 x VDD – – V
Tr/Tf – – 5 ns
Input and tristate currents
Strong pull-up -150 -40 -10 μA
Strong pull-down 10 40 150 μA
Weak pull-up -5 -1.0 -0.33 μA
Weak pull-down 0.33 1.0 5.0 μA
CI input capacitance 1.0 – 5.0 pF
12.3.9 LED driver pads
LED driver pads Min Typ Max Unit
Current, IPADHigh impedance state – – 5 µA
Current sink state – – 10 mA
LED pad voltage, VPAD IPAD = 10 mA – – 0.55 V
VOL output logic level lowa – 0 – V
VOH output logic level higha – 0.8 – V
VIL input logic level low – 0 – V
VIH input logic level high – 0.8 – Va LED output port is open-drain and requires a pull-up
12.3.10 Auxiliary ADC
Auxiliary ADC Min Typ Max Unit
Resolution – – 10 Bits
Input voltage range a 0 – VDD_AUX V
Accuracy(Guaranteed monotonic)
INL -1 – 1 LSB
DNL 0 – 1 LSB
Offset -1 – 1 LSB
Gain error -0.8 – 0.8 %
QCC3003 QFN Data Sheet Electrical characteristics
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Auxiliary ADC Min Typ Max Unit
Input bandwidth – 100 – kHz
Conversion time 1.38 1.69 2.75 µsa least significant bit/Byte (LSB) size = VDD_AUX/1023
12.4 Microphone bias generatorTable 12-1 Microphone bias generator
Microphone bias generator Min Typ Max Unit
Output voltage (1.8 V selected) 1.62 1.8 1.98 V
Output voltage (2.6 V selected) 2.34 2.6 2.86 V
Drop out from VBAT input – – 300 mV
Output current available – – 2.8 mA
Minimum load for stated performance 70 – – uA
12.5 ESD protectionApply ESD static handling precautions during manufacturing.
Table 12-2 ESD handling ratings
Condition Class Max rating
Human Body Model Contact Discharge per ANSI/ESDA/JEDEC JS-001
2 2 kV (all pins)
Charged Device Model Contact Discharge perJEDEC/EIA JESD22‑C101
III 500 V (all pins)
QCC3003 QFN Data Sheet Electrical characteristics
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71
13 Power consumption
DUT role Connection Packet type Averagecurrent Unit
N/A Deep sleep With UART host connection – 66 µA
N/A Page scanPage = 1280 ms intervalWindow = 11.25 ms
– 270 µA
N/A Inquiry andpage scan
Inquiry = 1280 ms intervalPage = 1280 ms intervalWindow = 11.25 ms
– 426 µA
Master ACL No traffic DH1 4.80 mA
Master ACL File transfer DH1 7.36 mA
Master ACL Sniff = 500 ms, 1 attempt, 0 timeout DH1 160 µA
Master ACL Sniff = 1280 ms, 8 attempts, 1 timeout DH1 134 µA
Master SCO Sniff = 100 ms, 1 attempt, PCM HV3 9.13 mA
Master SCO Sniff = 100 ms, 1 attempt, mono audio codec HV3 11.46 mA
Master eSCO Setting S3, sniff = 100 ms, PCM 2EV3 7.32 mA
Master eSCO Setting S3, sniff = 100 ms, PCM 3EV3 6.95 mA
Master eSCO Setting S3, sniff = 100 ms, codec 2EV3 9.62 mA
Master eSCO Setting S3, sniff = 100 ms, codec 3EV3 9.25 mA
Slave ACL No traffic DH1 7.73 mA
Slave ACL File transfer DH1 8.70 mA
Slave ACL Sniff = 500 ms, 1 attempt, 0 timeout DH1 178 µA
Slave ACL Sniff = 1280 ms, 8 attempts, 1 timeout DH1 166 µA
Slave SCO Sniff = 100 ms, 1 attempt, PCM HV3 9.48 mA
Slave SCO Sniff = 100 ms, 1 attempt, mono audio codec HV3 11.80 mA
Slave eSCO Setting S3, sniff = 100 ms, PCM 2EV3 7.78 mA
Slave eSCO Setting S3, sniff = 100 ms, PCM 3EV3 7.42 mA
Slave eSCO Setting S3, sniff = 100 ms, codec 2EV3 10.07 mA
Slave eSCO Setting S3, sniff = 100 ms, codec 3EV3 9.71 mA
Master Bluetoothlow energy Connected, 500 ms interval – 125 µA
Slave Bluetoothlow energy Connected, 500 ms interval – 166 µA
N/A Bluetoothlow energy
Non-connectable, 1.28 s, 15 octet,3 channels
– 102 µA
N/A Bluetoothlow energy Discoverable, 1.28 s, 15 octet, 3 channels – 112 µA
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DUT role Connection Packet type Averagecurrent Unit
N/A Bluetoothlow energy Connectable, 1.28 s, 15 octet, 3 channels – 114 µA
N/A Bluetoothlow energy Scanning 1.28 s, 11.25 ms, single frequency – 244 µA
NOTE Current consumption values are taken on QTIL development board in the following configuration:■ VBAT pin = 3.7 V
■ RF Tx power set to 0 dBm
■ No RF retransmissions in case of extended synchronous connection-oriented (eSCO)
■ Microphones and speakers disconnected
■ Audio gateway transmits silence when synchronous connection-oriented (SCO) or eSCO channel isopen
■ LEDs disconnected
■ The adaptive frequency hopping (AFH) classification master disabled
These values exclude SPI flash device current.For application current measurements, see the QCC3003.WIN.1.0 Release Note.
QCC3003 QFN Data Sheet Power consumption
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14 Software
QCC3003 QFN includes the following components:■ Integrated Bluetooth v5.0 specification qualified host controller interface (HCI) stack firmware
■ The sub-band coding (SBC) and Advanced Audio Coding (AAC) audio codecs
■ 8th generation 1-mic cVc headset audio noise reduction and echo cancellation
The QCC3003 QFN software architecture enables Bluetooth processing and the application program to run on theinternal RISC MCU and the audio enhancements on the Kalimba DSP.
14.1 QCC3003 application softwareHigh-level features running on the QCC3003 include:■ Advanced multipoint support
■ Advanced Audio Distribution Profile (A2DP) multipoint support
■ Wired audio mode
■ USB modes including USB audio mode
■ GAIA interface for smartphone applications
■ Programmable audio prompts
■ Intelligent power management
■ QTIL's proximity pairing and QTIL's proximity connection
For details, see the QCC3003.WIN.1.0 Release Note.
14.2 8th generation 1-mic cVc ENR technology for headset and audioenhancements1-mic cVc headset full-duplex voice processing software is a fully integrated and highly optimized set of DSPalgorithms developed to ensure easy design and build of headset products.cVc enables greater acoustic design flexibility for a wide variety of environments and configurations as a result ofsophisticated noise and echo suppression technology. cVc reduces the affects of noise on both sides of theconversation and smartly adjusts the receive volume levels and dynamically frequency shapes the voice to achieveoptimal intelligibility and comfort for the headset user.The 8th generation cVc has the following features:■ Full-duplex acoustic echo cancellation (AEC)
■ Bit error and packet loss concealment
■ Transmit and receive noise suppression including wind noise reduction (WNR)
■ Transmit and receive Parametric Equalization
■ Transmit and receive AGC
■ Noise dependent volume control
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■ Receive frequency enhanced speech intelligibility using adaptive equalizer
■ Narrowband, wideband, and frequency expansion operations
1-mic cVc headset includes a tuning tool enabling the developer to easily adapt cVc with different audioconfigurations and tuning parameters. The tool provides real-time system statistics with immediate feedbackenabling designers to quickly investigate the effect of changes.Figure 14-1 shows the functional block diagram of QTIL’s proprietary 1-mic cVc headset DSP solution.
G-T
W-0
0101
88.1
.1
Packet Loss Concealment
Noise Suppression
Adaptive Equalizer
Receive EqualizerReceive AGCClipper
Send AGCSend EqualizerComfort NoiseNoise Suppression
NDVC
Auxiliary Stream Mix
Acoustic Echo Canceller
Mic Gain
Speaker Gain
Bluetooth R
adio
Nonlinear Processing
Howling Control
Send In
Send Out
Receive Out
Receive In
Figure 14-1 1-mic cVc headset block diagram
14.2.1 Acoustic echo cancellation
The AEC includes the following features:■ A referenced sub-band adaptive linear filter that models the acoustic path from the receive reference point to the
microphone input■ A nonlinear processing function that applies narrowband and wideband attenuation adaptively as a result of
residual echo present after the linear filter
14.2.2 Noise suppression with wind noise reduction
The signal-channel noise suppression block is implemented in both signal paths. They are independent andindividually tuned. Noise suppression is a sub-band stationary/quasi-stationary noise suppression algorithm thatuses the temporal characteristics of speech and noise to remove the noise from the composite signal whilemaximizing speech quality. The current implementation can improve the signal-to-noise ratio (SNR) by up to 20 dB.In the transmit path, noise suppression aggressiveness is typically 95% improving SNR by 15 dB to 19 dB tocompensate for the upstream processing and to maintain superior voice quality, while the receive or receiver (Rx) istypically tuned down to 80% improving SNR by 8 dB to 12 dB because of the cellular network processing. The usercan parametrically adjust these default settings.The noise suppression block contains a WNR feature, for send path only. The WNR removes unwanted noise duringa hands-free conversation, cleaning the audio for the far-end listener. It detects and tackles winds of variousintensities and durations. Once the wind is detected, a good balance between voice quality and WNR is achieved.
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14.2.3 Nonlinear processing
The nonlinear processing module detects the presence of echo after the primary sub-band linear filter and adaptivelyapplies attenuation at frequencies where echo is identified. It minimizes echo because of nonlinearity caused by thesystem, for example, from the loudspeaker, microphone, amplifiers, or electronics. QTIL recommends minimal use ofnonlinear processing because of the inherent distortion that it introduces.
14.2.4 Howling control
The Howling control is a programmable coupling threshold. When triggered, Howling control applies attenuation tothe send path. This control enables cVc to operate in car-to-car calls without experiencing echo events in highvolume situations.
14.2.5 Comfort noise generator
The comfort noise generation (CNG):■ Creates a spectrally and temporally consistent noise floor for the far-end listener.
■ Adaptively inserts noise modeled from the noise present at the microphone into gaps introduced when thenonlinear processing of the AEC applies attenuation. The noise level applied is user-controllable.
■ Allows selectable colored noise.
14.2.6 Equalization
The equalization filters have the following features:■ Independent in the send and receive signal channels.
■ Independently enabled.
■ Configurable to achieve the required frequency response.
■ Each channel comprises of 5-stage cascaded second-order IIR filters.
■ Compensate for the frequency response of transducers in the system, which are the microphone and loudspeaker.
14.2.7 Automatic gain control
The AGC block attempts to do the following:■ Normalize the amplitude of the incoming audio signal to an intended range to increase perceived loudness
■ Reduce distortion because of clipping
■ Reduce amplitude variance observed from different users, phones, and networks
By maintaining a consistent long-term loudness for the speech, AGC ensures the speech to be more easily heard bythe listener and provides the subsequent processing block with a larger amplitude signal to process. The behavior ofthe AGC differs from a dynamic range audio compressor. The convergence time for the AGC is much slower toreduce the nonlinear distortion.
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14.2.8 Packet loss concealment
Bit errors and packet loss can occur in the Bluetooth transmission for various reasons, for example Wi-Fiinterference or RF signal degradation because of distance or physical objects. As a result of these errors, the userhears glitches referred to as pops and clicks in the audio stream. The packet loss concealment (PLC) block improvesthe receive path audio quality in the presence of bit and packet errors within the Bluetooth link by using varioustechniques such as pitch-based waveform substitution.The PLC tries to resynthesize the lost packet from the history buffer with the same pitch period. The PLC uses ahighly efficient 3-phase pitch estimator and performs crossfading at the concatenation boundaries. This means thatthe PLC attempts to clean up the audio signal by removing the pops and clicks and smoothing out gaps. Thisimproves the audio quality for the user and the improved signal enables preceding processing blocks to performbetter.The PLC significantly improves dealing with bit errors, using the bad frame indicator (BFI) output from the firmware.The DSP calculates an average bit error rate (BER) and selectively applies the PLC to the incoming data. Thisoptimizes audio quality for various bit errors and packet loss conditions.
NOTE The PLC is enabled in all modes, hands-free kit (HFK) (full processing), pass-through, and loopback bydefault.
14.2.9 Adaptive equalization
The adaptive equalization block improves the intelligibility of the receive path voice signal in the presence ofnear‑end noise by altering the spectral shape of the receive path signal while maintaining the overall power level. It isempirically observed that consonants, which are dominantly high-frequency based and much lower in amplitude thanvowels, significantly contribute to the intelligibility of the voice signal. In the presence of noise, the lower amplitudeconsonants are masked by this noise. Therefore, by increasing the frequency of components that contribute to theconsonants while in the presence of noise, the intelligibility can be improved.To maintain a consistent amplitude level, the adaptive equalization block adaptively increases the high frequenciesrelative to the middle frequencies and also reduces the low frequencies accordingly. The adaptive equalizer can alsocompensate for variations in voice transmission channels, which include far-end devices and telecommunicationchannels.The Frequency Emphasis feature can be used with any standard narrowband call, when the DAC is operating at asample rate of 8 kHz. To complement the adaptive equalizer (AEQ), High Frequency Emphasis can be added toimprove the intelligibility of the far-end caller. The emphasis feature repairs frequencies from 3469 Hz to 4000 Hz thatwere lost because of the filters of the cellular network and Bluetooth link. Information contained in the original speechfrom 281 Hz to 3469 Hz is used to reconstruct the lost high frequency content.The Frequency Expansion feature can be used with any standard narrowband call, but a special mode is invokedwhen the DAC operates at a sample rate of 16 kHz. The frequency expansion allows users to add in frequencies farbeyond the band limits caused by the cellular network and Bluetooth link. These expansion frequencies are addedbetween 3469 Hz and 6156 Hz. As in frequency emphasis, it uses the information contained in the original speechfrom 281 Hz to 3469 Hz to reconstruct the lost high frequency content.
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14.2.10 Auxiliary stream mix
The auxiliary stream mixer enables the system to seamlessly mix audio signals such as tones, beeps, and voiceprompts with the incoming SCO stream. This avoids any interruption to the SCO stream and as a result prevents anyspeech from being lost.
14.2.11 Clipper
The clipper block intentionally distorts or clips the receive signal before the reference input of the AEC to moreaccurately model the behavior of the post reference input blocks such as the DAC, power amplifier, and theloudspeaker. The AEC attempts to correlate the signal received at the reference input and the microphone input. Anynonlinearities introduced that are not accounted for after the reference input significantly degrade the AECperformance. This processing block can significantly improve the echo performance in cheap nonlinear systemdesigns.
14.2.12 Noise dependent volume control
The noise-dependent volume control (NDVC) block improves the intelligibility of the receive path signal by increasingthe analog DAC gain value based on the send noise estimate from the send path noise suppression block. As thesend noise estimate increases, the NDVC algorithm increases the analog DAC gain value. The NDVC useshysteresis to minimize the artifacts generated by rapidly adjusting the DAC gain because of the fluctuation in theenvironmental noise.
14.2.13 Input/output gains
Fixed gain controls are provided at the input to the cVc system. The mic gain is used to set the ADC level so thatproper levels can be set according to hardware constraints, industry standards, and the digital resolution of the DSPfixed-point processor. The speaker gain represents the output DAC that drives the speaker. The DAC level variesunder software control for events such as the Bluetooth volume, NDVC, tone mixing, and other volume-basedactivities.
14.3 Audio features
14.3.1 Audio codecs
QCC3003 QFN supports the following audio codecs:■ SBC
■ AAC
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14.3.2 Configurable EQ
QCC3003 QFN has 2 forms of equalizer (EQ):■ User configurable EQ: made up of up to 6 banks of 5-stage. Contains tiering for multiple customer presets, for
example user, rock, pop, classical, and jazz. This enables the device user to select between the EQ bankpresets through button presses.
■ Manufacturer configurable speaker EQ: made up of 1 bank of 0 to 10-stage. Contains an easy-to-use graphicaluser interface (GUI), with drag points, see Figure 14-2.
Figure 14-2 Configurable EQ GUI with drag points
14.3.3 Stereo widening (S3D)
The stereo widening feature on QCC3003 QFN:■ Simulates loudspeaker listening to provide 3D listening experience
■ Is highly optimized at < 1 MIPS of the Kalimba DSP
■ Reduces listener fatigue for headphone listening
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14.3.4 Volume boost
The volume boost feature on the QCC3003 QFN is a dynamic range compander and provides the followingfunctions:■ Extra loudness without clipping
■ Multistage compression and expansion
■ Processing modules for dynamic bass boost
■ New optional volume control hard limiter
■ Louder audio output without distortion
■ Easy-to-use GUI with drag points, see Figure 14-3
Figure 14-3 Volume boost GUI with drag points
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14.4 QCC3003 development kitQCC3003 development kit includes:
■ A basic package:□ Example QCC3003 QFN module design
□ Carrier board
□ Headphone amplifier board
□ Interface adapters and cables
□ QCC3003 application binary image
□ QCC300x ADK Configuration Tool
□ QCC300x Universal Front End Tool
■ A separate, optional package:□ QCC300x ADK software development kit
□ Bluetooth Developer’s License – Entry Level
NOTE The QCC3003 development kit is subject to change and updates. For up-to-date information, see theQTIL Support website.
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15 Environmental declaration statement for QTILsemiconductor products
This declaration statement applies to QTIL products.QTIL semiconductor products and packing materials meet the following substance restriction requirements, including Table 15-1:■ EU RoHS Directive 2011/65/EU1 maximum concentration values
■ EU REACH, Regulation (EC) No 1907/20061:□ List of substances subject to authorization (Annex XIV)
□ Restrictions on the manufacture, placing on the market and use of certain dangerous substances,preparations, and articles (Annex XVII)
■ POP regulation (EC) No 850/20041
■ EU Packaging and Packaging Waste, Directive 94/62/EC1
■ Montreal Protocol on substances that deplete the ozone layer
■ “California Prop 65”
Table 15-1 Restricted substances present in QTIL products
Found in products Substances CAS no. Amountpresent, ppm Applicable regulations
WLP packaged N-Methyl pyrrolidone 872-50-4 150-210 REACH SVHC, Prop 65
QTIL products contain less than 900 ppm of bromine or chlorine and less than 1500 ppm of bromine and chlorinecombined in each homogeneous material (“BrCl-free”).For more information about QTIL responsible product design, including substances QTIL avoids, refer to the ProductResponsibility section of the Qualcomm® website: http://www.qualcomm.com.
1 Applicable amendments as published in the EU Official Journal.
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16 Tape and reel information
For Tape and reel packing and labeling, see the IC Packing and Labelling Specification.
16.1 Tape orientation
G-T
W-0
0163
49.1
.4
User Direction of Feed
Figure 16-1 QCC3003 QFN tape orientation
16.2 Tape dimensions
G-T
W-0
0163
50.1
.3
0.25 ± 0.05
Bo
Ko
Section Y-Y
Section X-X
2.0 ± 0.1 mm (Note 1)
YØ 1.55 ± 0.05 mm
Ø 1.5 min
Y
X X
12.00 ± 0.1 mm Ao
A
16.00 +0.3/-0.0 mm
4.0 ± 0.1 mm (Note 2)
7.50 ± 0.1 mm(Note 3)
DETAIL A
1.75 ± 0.1 mm
REFR0.5 REF
R0.5
Figure 16-2 QCC3003 QFN tape dimensions diagram
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A0 B0 K0 Unit Notes
6.30 6.30 0.90 mm
1. Measured from centreline of sprocket hole to centreline ofpocket.
2. Cumulative tolerance of 10 sprocket holes is ±0.2.3. Measured from centreline of sprocket hole to centreline of
pocket.4. Other material available.
16.3 Reel information
G-T
W-0
0163
81.1
.2
102.02.0
330.02.0
W1(MEASURED AT HUB)
(MEASURED AT HUB)
"A"
ATTENTIONElectrostatic Sensitive Devices Safe Handling Required
W2
20.2
MIN
2.0 0.5
13.0+0.5-0.2
Detail "A"
Detail "B"
6 PS
PS
6
a(rim height)
88 REF
"b" REF
Figure 16-3 Reel dimensions
Package typeNominal hubwidth (tape
width)a b W1 W2 max Unit
6 × 6 × 0.6 mmQFN 16 4.5 98.0 16.8 (+1.6/-0.4) 22.4 mm
16.4 Moisture sensitivity levelQCC3003 QFN is qualified to moisture sensitivity level MSL3 in accordance with Joint Electron Device EngineeringCouncil (JEDEC) J-STD-020.
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Glossary
Term Definition
8DPSK 8-phase differential phase shift keying
A2DP Advanced Audio Distribution Profile
AAC Advanced Audio Coding
ACL Asynchronous connection-less
ADC Analog-to-digital converter
ADK Audio development kit
AEC Acoustic echo cancellation
AEQ Adaptive equalizer
AFH Adaptive frequency hopping
AGC Automatic gain control
AIO Analog input/output
ALU Arithmetic logic unit
AVRCP Audio/Video Remote Control Profile
BAS Battery Service Profile
BER Bit error rate
BFI Bad frame indicator
CNG Comfort noise generation
codec Coder decoder
CPU Central processing unit
DAC Digital-to-analog converter
DC Direct current
DMA Direct memory access
DSP Digital signal processor
DUT Device under test
EC Echo cancellation
EQ Equalizer
eSCO Extended synchronous connection-oriented
ESD Electrostatic discharge
ESR Equivalent series resistance
FIR Finite impulse response (filter)
FMP Find Me Profile
FSK Frequency shift keying
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Term Definition
G.722 An ITU-T standard wideband speech codec operating at 48 kbps, 56 kbps, and 64 kbps
GSM Global system for mobile communications
GUI Graphical user interface
HCI Host controller interface
HFK Hands-free kit
HFP Hands Free Profile
HOGP HID over GATT Profile
HSP Headset Profile
I/O Input/output
I/Q In-phase and quadrature
IC Integrated circuit
IEEE Institute of Electronic and Electrical Engineers
IF Intermediate frequency
IIR Infinite impulse response (filter)
IPC Institute of Printed Circuits, see www.ipc.org
I²C Inter-integrated circuit interface
I²S Inter-integrated circuit sound
JEDEC Joint Electron Device Engineering Council (now the JEDEC Solid State TechnologyAssociation)
LC An inductor (L) and capacitor (C) network
LDO Low (voltage) drop-out
LED Light-emitting diode
LNA Low noise amplifier
LSB Least significant bit (or Byte)
MAC Multiplier and accumulator
MCU Microcontroller unit
MIPS Million instructions per second
MISO Master in slave out
MLC Multilayer ceramic
MMU Memory management unit
MSB Most significant bit (or Byte)
N/A Not applicable
NDVC Noise-dependent volume control
NR Noise reduction
NSMD Nonsolder mask defined
PA Power amplifier
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Term Definition
PC Personal computer
PCB Printed circuit board
PCM Pulse code modulation
PIO Programmable input/output, also known as general-purpose I/O
PLC Packet loss concealment
PS Key Persistent store key
PWM Pulse width modulation
PXP Proximity Profile
QSPI Quad serial peripheral interface (flash)
QTIL Qualcomm Technologies International, Ltd.
RAM Random access memory
RF Radio frequency
RGB Red green blue
RISC Reduced instruction set computer
RoHS Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive(2002/95/ EC)
ROM Read only memory
RSSI Received signal strength indication
Rx Receive or receiver
SBC Sub-band coding
SCL Serial clock line
SCO Synchronous connection-oriented
SDA Serial data (line)
SMPS Switch-mode power supply
SNR Signal-to-noise ratio
SPI Serial peripheral interface
SPP Serial port profile
SQIF Serial quad input/output flash (interface)
THD+N Total harmonic distortion plus noise
Tx Transmit or transmitter
UART Universal asynchronous receiver transmitter
USB Universal serial bus
VCO Voltage-controlled oscillator
VM Virtual machine
WCDMA Wideband code division multiple access
WNR Wind noise reduction
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Term Definition
XTAL Crystal
π/4 DQPSK π/4 rotated differential quadrature phase shift keying
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Document references
Document Reference
BlueTest User Guide CS-00102736-UG
Bluetooth and USB Design Considerations CS-00101412-AN
Configuring the Power Supplies on CSR8670 Application Note CS-00204573-AN
Core Specification of the Bluetooth System Bluetooth Specification Version 5.0,06 December 2016
Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurementtechniques – Electrostatic discharge immunity test
IEC 61000-4-2, Edition 2.0, 2008-12
ESDA/JEDEC Joint Standard For Electrostatic Discharge Sensitivity TestingHuman Body Model (HBM) - Component Level
ANSI/ESDA/JEDECJS-001-201
Field-Induced Charged-Device Model Test Method for Electrostatic- Discharge-Withstand Thresholds of Microelectronic Components
JESD22-C101E
IC Packing and Labelling Specification CS-00112584-SP
Lithium Polymer Battery Charger Calibration and Operation for CSR8670 CS-00204572-AN
Moisture/Reflow Sensitivity Classification for Nonhermitic Solid State SurfaceMount Devices
IPC/JEDEC J-STD-020
QCC3003.WIN.1.0 Release Note 80-CF098-1/CS-00405091-RN
QCC3003 QFN Audio Performance Specification 80-CE949-1/CS-00404253-SP
QCC3003 QFN Bluetooth Performance Specification 80-CE948-1/CS-00404161-SP
QCC300x A14 ROM Firmware Release Note CS-00403389-RN
Typical Solder Reflow Profile for Lead-free Devices Application Note CS-00116434-AN
Universal Serial Bus Specification v2.0, 27 April 2000
USB Battery Charging Specification v1.2 v1.2 December 7th 2010, also errata andECNs through March 15th 2012. See www.usb.org
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