energies

Article

Development of an SDBC-MMCC-BasedDSTATCOM for Real-Time Single-Phase LoadCompensation in Three-Phase PowerDistribution Systems

Wei-Neng Chang 1,* and Ching-Huan Liao 2

1 Department of Electrical Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-Shan Dist.,Tao-Yuan City 333, Taiwan

2 National Chung-Shan Institute of Science and Technology, 486, 6th Neighborhood, Sec. Jia’an, ZhongzhengRoad, Longtan Dist., Tao-Yuan City 325, Taiwan; howardliao05@gmail.com

* Correspondence: nchang@mail.cgu.edu.tw; Tel.: +886-3-211-8800

Received: 31 August 2019; Accepted: 5 December 2019; Published: 10 December 2019

Abstract: This paper proposes a newly developed single-delta bridge-cell, modular multilevel cascadeconverter (SDBC-MMCC)-based distribution-level static synchronous compensator (DSTATCOM)for single-phase load compensation in three-phase, three-wire electric power distribution systems.Each main circuit arm of the DSTATCOM uses a modular multilevel cascade converter basedon full-H-bridge (FHB) cells. The three main DSTATCOM arms are delta-connected to allowphase-independent operations for phase balancing and unity power factor correction of thesingle-phase load in three-phase, three-wire electric power distribution systems. By using thesymmetrical components method, a feedforward compensation algorithm was employed for theDSTATCOM. A simulation of the DSTATCOM was performed for functioning verification. Finally, ahardware test system was built by using a multi-DSP-based control system. The test results verified theeffectiveness of the proposed SDBC-MMCC-based DSTATCOM in single-phase load compensation.

Keywords: DSTATCOM; full-H-bridge converter; phase balancing; power factor correction;SDBC-MMCC; single-phase load compensation

1. Introduction

In a three-phase electric power distribution system, a large power capacity of single-phase load(e.g., an electrical railway traction system) absorbs unbalanced (negative-sequence) load current andreactive power. The unbalanced load current produces an unbalanced voltage drop on the electricpower distribution line. The resulting unbalanced voltage affects other sensitive loads connected tothe distribution system. For example, AC rotary machines will induce extra losses, and rectifier loadswill generate ripples in their DC links. Moreover, the unbalanced current will disturb the normaloperation of an electric power generator. To keep good power quality, the unbalanced current from thesingle-phase load should be improved [1,2].

Traditionally, the delta connection of passive inductive/capacitive reactances, also known as a“Steinmetz compensator”, was employed for single-phase load compensations in three-phase powersystems [3–5]. The operation principle of the Steinmetz compensator has been used in many applicationsof unbalanced load compensations [6]. Presently, static var compensators (SVC) are widely used inthe load compensations of high-power, single-phase traction systems [7–9]. The thyristor-controlledreactor with fixed capacitor (TCR–FC) type of SVC is applied in these traction systems. A drawback ofthe TCR–FC type of SVC is that it demands large space for installation. Two-level converters can also

Energies 2019, 12, 4705; doi:10.3390/en12244705 www.mdpi.com/journal/energies

Energies 2019, 12, 4705 2 of 15

be used for single-phase load compensations in three-phase power systems [10–12]. However, thepower ratings of two-level converters are limited.

Recently, static synchronous compensators (STATCOMs) have been introduced as thenext-generation shunt compensators [13–16]. Compared to traditional SVCs, STATCOMs havequicker response times, more compact structures, wider compensation ranges, and smaller installationspace demand. Therefore, distribution-level static synchronous compensators (DSTATCOMs) arehighly suitable for unbalanced load compensations in modern three-phase electric power distributionsystems. Various types of converters can be employed to construct the main circuit of a DSTATCOM.Due to lower voltage stress and modular structure, single-delta bridge-cell, modular multilevel cascadeconverters (SDBC-MMCCs) are very suitable for the main circuits of DSTATCOMs in high-voltage andhigh-power applications [17–20]. Hence, the SDBC-MMCC-based DSTATCOMs can replace the SVCsin single-phase load compensations.

In this paper, a new concept of applying an SDBC-MMCC-based DSTATCOM for real-timesingle-phase load compensation in a three-phase, three-wire power distribution system is proposed.Applications of multilevel full-H-bridge (FHB) converters and staircase modulation in the DSTATCOMmain circuit can achieve high-efficiency operation in practical applications. A feedforwardcompensation algorithm derived from the symmetrical components method was designed for theDSTATCOM, which was constructed using the MATLAB/SimuLink program for preliminary verification.Finally, a hardware prototype test system was built using a multi-TMS320F2812 digital signal processor(DSP)-based control system. Experimental results show that the proposed SDBC-MMCC-basedDSTATCOM has a rapid response and a satisfactory compensation effect. This paper is a furtherdevelopment of the SDBC-MMCC-based DSTATCOM for three-phase unbalanced load compensationthat we previously described [21]. In single-phase load compensation, the control algorithm of theDSTACOM is more compact, and the sizing of the DSTATCOM is more precisely defined.

2. DSTATCOM Load Compensation Algorithm

Figure 1 illustrates the study system for deriving the DSTATCOM compensation algorithm. A shunttype of DSTATCOM is installed for the on-site single-phase load compensation. The feedforwardcompensation algorithm detects the load power parameters, PL

ab and QLab, and sends three reactive power

compensation commands, QST∗ab,bc,ca, to the DSTATCOM’s main circuit arms. The three DSTATCOM arms

independently regulate their reactive power inputs, then the synthesized DSTATCOM line currentcompensates the unbalanced single-phase load current. Consequently, the source currents are balancedwith a unity power factor. Using the symmetrical components method, we derived the feedforwardcompensation algorithm. Figure 2 shows the phase-sequence circuits of Figure 1.

Energies 2019, 12, x FOR PEER REVIEW 2 of 16

systems. A drawback of the TCR–FC type of SVC is that it demands large space for installation. Two-level converters can also be used for single-phase load compensations in three-phase power systems [10–12]. However, the power ratings of two-level converters are limited.

Recently, static synchronous compensators (STATCOMs) have been introduced as the next-generation shunt compensators [13–16]. Compared to traditional SVCs, STATCOMs have quicker response times, more compact structures, wider compensation ranges, and smaller installation space demand. Therefore, distribution-level static synchronous compensators (DSTATCOMs) are highly suitable for unbalanced load compensations in modern three-phase electric power distribution systems. Various types of converters can be employed to construct the main circuit of a DSTATCOM. Due to lower voltage stress and modular structure, single-delta bridge-cell, modular multilevel cascade converters (SDBC-MMCCs) are very suitable for the main circuits of DSTATCOMs in high-voltage and high-power applications [17–20]. Hence, the SDBC-MMCC-based DSTATCOMs can replace the SVCs in single-phase load compensations.

In this paper, a new concept of applying an SDBC-MMCC-based DSTATCOM for real-time single-phase load compensation in a three-phase, three-wire power distribution system is proposed. Applications of multilevel full-H-bridge (FHB) converters and staircase modulation in the DSTATCOM main circuit can achieve high-efficiency operation in practical applications. A feedforward compensation algorithm derived from the symmetrical components method was designed for the DSTATCOM, which was constructed using the MATLAB/SimuLink program for preliminary verification. Finally, a hardware prototype test system was built using a multi-TMS320F2812 digital signal processor (DSP)-based control system. Experimental results show that the proposed SDBC-MMCC-based DSTATCOM has a rapid response and a satisfactory compensation effect. This paper is a further development of the SDBC-MMCC-based DSTATCOM for three-phase unbalanced load compensation that we previously described [21]. In single-phase load compensation, the control algorithm of the DSTACOM is more compact, and the sizing of the DSTATCOM is more precisely defined.

2. DSTATCOM Load Compensation Algorithm

Figure 1 illustrates the study system for deriving the DSTATCOM compensation algorithm. A shunt type of DSTATCOM is installed for the on-site single-phase load compensation. The feedforward compensation algorithm detects the load power parameters, L

abP and LabQ , and sends

three reactive power compensation commands, *, ,

STab bc caQ , to the DSTATCOM’s main circuit arms. The

three DSTATCOM arms independently regulate their reactive power inputs, then the synthesized DSTATCOM line current compensates the unbalanced single-phase load current. Consequently, the source currents are balanced with a unity power factor. Using the symmetrical components method, we derived the feedforward compensation algorithm. Figure 2 shows the phase-sequence circuits of Figure 1.

SanV

SjX

SjX

SjX

Single-PhaseLoad

STabjQ

STbcjQ

STcajQ

DSTATCOM

LabZ

+

-

a

b

c

L Lab abP jQ+

ScnV

SbnV

+-

+

+

-

-

SaI

SbI

ScI

LanV

LbnV

LcnV

LabV

LaI

L Lb aI I= −

STaI

STbIST

cIn

Figure 1. Three-phase, three-wire power distribution system with single-phase load and distribution-level static synchronous compensator (DSTATCOM). Figure 1. Three-phase, three-wire power distribution system with single-phase load anddistribution-level static synchronous compensator (DSTATCOM).

Energies 2019, 12, 4705 3 of 15Energies 2019, 12, x FOR PEER REVIEW 3 of 16

SjX

+-

1S

I1L

V1ST

I1S

V1L

I-

+

Positive sequence

SjX2S

I

2L

V2ST

I 2L

I-

+

Negative sequence

Figure 2. Phase-sequence circuits of Figure 1.

Equation (1) expresses the line voltage of the load bus illustrated in Figure 1, where llV represents the line voltage. The phase-a load current is shown in Equation (2), in which the relationship of *( )

L L L Laab ab abV I P jQ⋅ = − is used. The symmetrical components of the load current are then

calculated using Equation (3).

30L L L ll oab an bnV V V V= − = ∠ (1)

1 ( )30

= −∠ −

L L La ab abll oI P jQ

V (2)

0

21

22

1 1 11 1 3 01

L La

L La

L

I II a a I

a aI

= −

(3)

Equation (3) can be rewritten as rectangular forms, as indicated in Equations (4) and (5). The zero-sequence component of the load current is zero. Equation (6) gives the three arm currents of the DSTATCOM, where the relationship of *

V I P jQ⋅ = − is used. Equation (7) shows the DSTATCOM line currents. Using the symmetrical components transformation in Equation (8), Equation (9) shows the symmetrical components of the DSTATCOM line current in terms of the reactive power flows of the three DSTATCOM arms. For a DSTATCOM with a delta-connected main circuit, the zero-sequence current, 0

STI , in Equation (8) is zero.

1

1 1

1 [ ]3 3 3

Re Im

= − = −

= +

L LL L L ab ab

ll ll llab ab

L L

P QI P jQ j

V V V

I j I (4)

2

2 2

1 1 3 1 3 1( ) ( )2 2 2 23 3

= Re Im

L L L L Lll llab ab ab ab

L L

I P Q j P QV V

I j I

= + + −

+ (5)

( ) /( 30 )

( ) /( 90 )

( ) /( 150 )

ST ST ll oab abST ST ll obc bcST ST ll oca ca

I jQ V

I jQ V

I jQ V

= − ∠ −

= − ∠

= − ∠ −

(6)

ST ST STa ab ca

ST ST STb bc ab

ST STSTca bcc

I I I

I I I

I II

− = − −

(7)

0

21

22

1 1 11 1 3 1

ST STa

ST STb

ST STc

I II a a I

a aI I

=

, 1 120oa = ∠ (8)

Figure 2. Phase-sequence circuits of Figure 1.

Equation (1) expresses the line voltage of the load bus illustrated in Figure 1, where Vll representsthe line voltage. The phase-a load current is shown in Equation (2), in which the relationship of

(VLab)∗

·ILa = PL

ab − jQLab is used. The symmetrical components of the load current are then calculated

using Equation (3).

VLab = V

Lan −V

Lbn = Vll∠30o (1)

ILa =

1Vll∠− 30o

(PLab − jQL

ab) (2)IL0

IL1

IL2

= 13

1 1 1

1aa2

1a2a

ILa

−ILa

0

(3)

Equation (3) can be rewritten as rectangular forms, as indicated in Equations (4) and (5). Thezero-sequence component of the load current is zero. Equation (6) gives the three arm currents of theDSTATCOM, where the relationship of V

∗

·I = P− jQ is used. Equation (7) shows the DSTATCOM linecurrents. Using the symmetrical components transformation in Equation (8), Equation (9) shows thesymmetrical components of the DSTATCOM line current in terms of the reactive power flows of thethree DSTATCOM arms. For a DSTATCOM with a delta-connected main circuit, the zero-sequence

current, IST0 , in Equation (8) is zero.

IL1 = 1

√3Vll [P

Lab − jQL

ab] =PL

ab√3Vll − j

QLab√

3Vll

= ReIL1

+ jIm

IL1

(4)

IL2 = 1

√3Vll (

12 PL

ab +√

32 QL

ab) + j 1√

3Vll (√

32 PL

ab −12 QL

ab)

= ReIL2

+ jIm

IL2

(5)

ISTab =

(− jQST

ab

)/(Vll∠− 30

)

ISTbc =

(− jQST

bc

)/(Vll∠90

)

ISTca =

(− jQST

ca

)/(Vll∠− 150

)

(6)

ISTa

ISTb

ISTc

=

ISTab − I

STca

ISTbc − I

STab

ISTca − I

STbc

(7)

IST0

IST1

IST2

= 13

1 1 11 a a2

1 a2 a

ISTa

ISTb

ISTc

, a = 1∠120

(8)

IST1 =

− j3Vll (Q

STab + QST

bc + QSTca )

IST2 = 1

√3Vll (

√3

2 QSTab −

√3

2 QSTca ) + j 1

√3Vll (

−12 QST

ab + QSTbc −

12 QST

ca )(9)

Energies 2019, 12, 4705 4 of 15

As shown in Figure 2, for the single-phase load compensation, the DSTATCOM should compensatethe entire negative-sequence component and imaginary part of the positive-sequence componentcurrents generated by the single-phase load, as revealed in Equation (10) [21,22]. The source currentonly supplies the real part of the positive-sequence load current. As a result, with the assistance of theDSTATCOM compensation, the source current is balanced with a unity power factor.

IST1 + Im

IL1

= 0, I

ST2 + I

L2 = 0 (10)

Finally, combining Equations (4), (5) and (9), (10), we obtained the required load compensationalgorithm of each DSTATCOM arm for real-time single-phase load compensation, as indicated byEquation (11). Equation (11) is very compact and suitable for the SDBC-MMCC-based DSTATCOM.The sizing of the DSTATCOM can easily be calculated using Equation (11). The DSTATCOM is treatedas a reactive power load in the compensation. The reactive power flow of each DSTATCOM arm,which can be inductive or capacitive, is independently controlled by the compensation algorithm inEquation (11). By using power calculation definitions, P = (

∫T i·v dt)/T and Q = (−

∫T i·v(π/2)dt)/T,

in the time domain, Equation (12) shows another version of Equation (11) for the DSATCOM, where Tis the period of the fundamental frequency. Equation (12) can easily be digitized and implementedin a digital controller. Finally, Equation (13) shows the three-phase source current with DSTATCOMcompensation.

QST∗ab = −QL

abQST∗

bc = −PLab/√

3QST∗

ca = PLab/√

3(11)

QST∗ab = 1

√3T×

∫T [iLa ·(vL

ca − vLbc)]dt

QST∗bc = −1

√3T×

∫T (iLa ·vL

ab) dt

QST∗ca = 1

√3T×

∫T (iLa ·vL

ab) dt(12)

ISa

ISb

ISc

=

1 1 11 a2 a1 a a2

IS0

IS1

IS2

=

1 1 11 a2 a1 a a2

0PL

ab/(√

3Vll)

0

=

PLab/(√

3Vll)∠0

PLab/(√

3Vll)∠−120

PLab/(√

3Vll)∠120

(13)

3. DSTATCOM Main Circuit

Figure 3 shows a three-phase power distribution system, a single-phase load, and the proposedseven-level, SDBC-MMCC-based DSTATCOM as the test system in the paper. Each STATCOM armconsists of an internal voltage source, VST, modulated by a seven-level, cascade full-H-bridge converterand a commutation reactor, XST. In this study, each DSTATCOM arm is equivalent to a purely reactivepower load.

The reactive power flows of these three DSTATCOM arms are regulated independently for thesingle-phase load compensation. The power inputs of each DSTATCOM arm in Figure 3 are expressedin Equations (14) and (15), respectively. An indirect phasor-domain power angle regulation method isused for the reactive power control in the DSTATCOM. For a reactive power demand, the DSTATCOMcontroller regulates the power angle, δST, to absorb or release the active power from the power sourceaccording to Equation (14). The active power flow charges or discharges the DC-link capacitors and thenregulates the DC-link voltages. Finally, the cascaded DC-link voltages synthesize the internal voltage,VST, then the DSTATCOM absorbs capacitive or inductive reactive power according to Equation (15).When the reactive power response is completed, the power angle returns to near-zero values. Withthe delta-connected main circuit, the three DSTATCOM arms achieve phase-independent operation.Hence, much like a traditional SVC, the DSTATCOM can easily compensate the unbalanced loadcurrent and correct the power factor caused by a single-phase load.

Energies 2019, 12, 4705 5 of 15Energies 2019, 12, x FOR PEER REVIEW 5 of 16

STX

1abC 2abC 3abC

LbcV

LcaV

Single-PhaseLoad

SanVSbnVScnV

, ,Sa b cZ

STabI

0LabV ∠

ST STab abV δ∠

1STabv 2

STabv 3

STabv

+

+

+

-

-

1dc

abV 2dc

abV 3dc

abV+

+

-

-

--

-

Arm b-cArm c-a

Arm a-b

+

+

++

+

--

-

LabV

+

-

Figure 3. The test system with a single-phase load and the proposed seven-level, single-delta, bridge-cell, modular multilevel cascade converter (SDBC-MMCC)-based DSTATCOM.

The reactive power flows of these three DSTATCOM arms are regulated independently for the single-phase load compensation. The power inputs of each DSTATCOM arm in Figure 3 are expressed in Equations (14) and (15), respectively. An indirect phasor-domain power angle regulation method is used for the reactive power control in the DSTATCOM. For a reactive power demand, the DSTATCOM controller regulates the power angle, STδ , to absorb or release the active power from the power source according to Equation (14). The active power flow charges or discharges the DC-link capacitors and then regulates the DC-link voltages. Finally, the cascaded DC-link voltages synthesize the internal voltage, STV , then the DSTATCOM absorbs capacitive or inductive reactive power according to Equation (15). When the reactive power response is completed, the power angle returns to near-zero values. With the delta-connected main circuit, the three DSTATCOM arms achieve phase-independent operation. Hence, much like a traditional SVC, the DSTATCOM can easily compensate the unbalanced load current and correct the power factor caused by a single-phase load.

A typical staircase modulation scheme, depicted in Figure 4, enables the DSTATCOM main circuit to operate with high efficiency. Each level and internal voltage waveform of the DSTATCOM arm a-b in Figure 3 are also shown [21]. The internal voltage STv shows a staircase waveform. The three switching angles, 1θ – 3θ , should be determined to minimize the harmonics generated. The internal voltage STv in Figure 4 can be represented as a Fourier series, as detailed in Equation (16), where n is the harmonic order ( 1,3,5,7,...n = ). Ideally, the harmonic order contains only odd-order components. Equation (17) shows the harmonic components in Equation (16).

sinST L

ST STST

V VPX

δ= − (14)

( - cos )L L ST STST

ST

V V VQX

δ= (15)

Figure 3. The test system with a single-phase load and the proposed seven-level, single-delta, bridge-cell,modular multilevel cascade converter (SDBC-MMCC)-based DSTATCOM.

A typical staircase modulation scheme, depicted in Figure 4, enables the DSTATCOM main circuitto operate with high efficiency. Each level and internal voltage waveform of the DSTATCOM arma-b in Figure 3 are also shown [21]. The internal voltage vST shows a staircase waveform. The threeswitching angles, θ1–θ3, should be determined to minimize the harmonics generated. The internalvoltage vST in Figure 4 can be represented as a Fourier series, as detailed in Equation (16), where n isthe harmonic order (n = 1, 3, 5, 7, . . .). Ideally, the harmonic order contains only odd-order components.Equation (17) shows the harmonic components in Equation (16).

PST = −VSTVL

XST sin δST (14)

QST =VL(VL

−VST cos δST)

XST (15)

vST(ωt) = 4Vdc

π

∑n[cos(nθ1) + cos(nθ2) + cos(nθ3)]·

sin(nωt)n , 0

< θ1 < θ2 < θ3 < 90

, n = 1, 3, 5, 7, . . . (16)

H(n) =4Vdc

nπ[cos(nθ1) + cos(nθ2) + cos(nθ3)] (17)

Energies 2019, 12, x FOR PEER REVIEW 6 of 16

2STabv

1STabv

3 dcV−

3 dcV

STabδ

0 2π

π 2π tω

tω

tω

tω

3dc

abV

2dc

abV

1dc

abV

1dc

abV−

3θ3π θ−

2θ2π θ−

1θ1π θ−

Labv * (1)ST

abv1 2 3

ST ST ST STab ab ab abv v v v= + +

STabi

2dc

abV−

3dc

abV−3

STabv

Figure 4. Voltage waveforms of the DSTATCOM arm a-b using staircase modulation.

[ ]1 2 3 1 2 34 0 90

dcST

n

V sin( n t )v ( t ) cos( n ) cos( n ) cos( n ) , , n=1,3,5,7,...n

ωω θ θ θ θ θ θπ

= + + ⋅ ° < < < < ° (16)

[ ]1 2 3

4( ) cos( ) cos( ) cos( )dcVH n n n n

nθ θ θ

π= + + (17)

In Equation (17), setting 1n = produces the fundamental component (1)H , which consists of

the DC-link voltage dcV and three switching angles, 1θ – 3θ . The fundamental component (1)H is used for the reactive power regulation. To eliminate the specified harmonic orders, a harmonic-minimizing method is used [23]. Assigning (1) 3 dcH V= for the fundamental-component modulation and setting (5) (7) 0H H= = for the 5th and 7th orders’ harmonic cancellation produces Equation (18). Subsequently, solving Equation (18) results in the required switching angles, namely, 1θ =11.68o , 2θ= 31.18o , 3θ = 58.58o .

( ) ( ) ( )( ) ( ) ( )( ) ( ) ( )

1 2 3

1 2 3

1 2 3

cos cos cos 3 / 4cos 5 cos 5 cos 5 0

cos 7 cos 7 cos 7 0

θ θ θ πθ θ θθ θ θ

+ + =

+ + =

+ + =

(18)

Figure 5 depicts the functional block diagram of the DSTATCOM controller proposed in this

paper. As noted, the control algorithm using Equation (11) calculates the required reactive power values of the three DSTATCOM arms in real time. Three well-tuned proportional integral derivative (PID) feedback controllers in the inner loops regulate the reactive power inputs of the three DSTATCOM arms independently, as shown in Equation (19). The three output commands of the PID controllers, ST*

ab,bc,caδ , generate the gating signals, as shown in Figure 4 for these switching elements in the three DSTATCOM arms. With the proposed controller shown in Figure 5, the DSTATCOM completes the single-phase load compensation in real time. The DSTATCOM controller in Figure 5 requires a fast power detection method. Figure 6 schematizes the fast calculation method of active and reactive powers that applies the single-phase -α β reference axis method. Applying this fast calculation results in the load power values for Equation (11) and the reactive power inputs of the three DSTATCOM arms in real time.

Figure 4. Voltage waveforms of the DSTATCOM arm a-b using staircase modulation.

Energies 2019, 12, 4705 6 of 15

In Equation (17), setting n = 1 produces the fundamental component H(1), which consists of theDC-link voltage Vdc and three switching angles, θ1–θ3. The fundamental component H(1) is used forthe reactive power regulation. To eliminate the specified harmonic orders, a harmonic-minimizingmethod is used [23]. Assigning H(1) = 3Vdc for the fundamental-component modulation andsetting H(5) = H(7) = 0 for the 5th and 7th orders’ harmonic cancellation produces Equation (18).Subsequently, solving Equation (18) results in the required switching angles, namely, θ1 = 11.68

, θ2 =

31.18

, θ3 = 58.58

.cos(θ1) + cos(θ2) + cos(θ3) = 3π/4cos(5θ1) + cos(5θ2) + cos(5θ3) = 0cos(7θ1) + cos(7θ2) + cos(7θ3) = 0

(18)

Figure 5 depicts the functional block diagram of the DSTATCOM controller proposed in this paper.As noted, the control algorithm using Equation (11) calculates the required reactive power valuesof the three DSTATCOM arms in real time. Three well-tuned proportional integral derivative (PID)feedback controllers in the inner loops regulate the reactive power inputs of the three DSTATCOM armsindependently, as shown in Equation (19). The three output commands of the PID controllers, δST∗

ab,bc,ca,generate the gating signals, as shown in Figure 4 for these switching elements in the three DSTATCOMarms. With the proposed controller shown in Figure 5, the DSTATCOM completes the single-phaseload compensation in real time. The DSTATCOM controller in Figure 5 requires a fast power detectionmethod. Figure 6 schematizes the fast calculation method of active and reactive powers that appliesthe single-phase α− β reference axis method. Applying this fast calculation results in the load powervalues for Equation (11) and the reactive power inputs of the three DSTATCOM arms in real time.

δST∗ab,bc,ca = KP∆QST

ab,bc,ca + KI∫

∆QSTab,bc,cadt + KD

ddt ∆QST

ab,bc,cawhere, ∆QST

ab,bc,ca = QST∗ab,bc,ca −QST

ab,bc,ca(19)

Energies 2019, 12, x FOR PEER REVIEW 7 of 16

*, , , , , , , ,

ST ST ST STab bc ca P ab bc ca I ab bc ca D ab bc ca

dK Q K Q dt K Qdt

δ = Δ + Δ + Δ

where, *, , , , , , ST ST ST

ab bc ca ab bc ca ab bc caQ Q QΔ = − (19)

Load P,Q and Compensation Scheme Calculations

DSTATCOMMain CircuitandPowerDistributionSystem

Lai , ,

Lab bc cav

Master Controller PID

Switching Patterns

Generator

Phase c-aQ Calculation

PLL

Gating Signals

Arm c-a Control

STcaQ

*STcaQ

,ST Lca cai v

*STcaδ

2 / 3tω π+

11 4~ ng g

PIDSwitching Patterns

Generator

Phase b-cQ Calculation

PLL

Gating Signals

Arm b-c Control

STbcQ

*STbcQ

,ST Lbc bci v

*STbcδ

2 / 3tω π−

11 4~ ng g

PIDSwitching Patterns

Generator

Phase a-b Q Calculation

PLL

Gating Signals

Arm a-b Control

STabQ

*STabQ

,ST Lab abi v

*STabδmaxδ

minδtω

11 4~ ng g

maxδ

maxδ

minδ

minδ

Figure 5. The proposed DSTATCOM controller.

( )i tβ ( )Q t

( ) ( )i t i tα=

( )v tβ

( ) ( )v t v tα=

( )i t

( )v t 90o∠

90o∠ ×

×

+-( ) ( )v t i tα β

( ) ( )v t i tβ α

( )P t×

×

( ) ( )v t i tα α

( ) ( )v t i tβ β

+

Figure 6. Fast power calculation method.

4. Simulation Verification

Figure 7 shows the simulation system, which was developed in the MATLAB/SimuLink program for a preliminary verification of the proposed DSTATCOM. A single-phase inductive load was used in the testing. First, the DSTATCOM main circuit was built according to Figure 3. In the simulation, the switch (SW) in Figure 7 was closed at t = 0.605 s to make a step response caused by the single-phase load. With the setting, the transient and steady-state performances of the DSTATCOM compensation were observed from the simulation results. Appendix A lists the system parameters.

Figure 5. The proposed DSTATCOM controller.

Energies 2019, 12, 4705 7 of 15

Energies 2019, 12, x FOR PEER REVIEW 7 of 16

*, , , , , , , ,

ST ST ST STab bc ca P ab bc ca I ab bc ca D ab bc ca

dK Q K Q dt K Qdt

δ = Δ + Δ + Δ

where, *, , , , , , ST ST ST

ab bc ca ab bc ca ab bc caQ Q QΔ = − (19)

Load P,Q and Compensation Scheme Calculations

DSTATCOMMain CircuitandPowerDistributionSystem

Lai , ,

Lab bc cav

Master Controller PID

Switching Patterns

Generator

Phase c-aQ Calculation

PLL

Gating Signals

Arm c-a Control

STcaQ

*STcaQ

,ST Lca cai v

*STcaδ

2 / 3tω π+

11 4~ ng g

PIDSwitching Patterns

Generator

Phase b-cQ Calculation

PLL

Gating Signals

Arm b-c Control

STbcQ

*STbcQ

,ST Lbc bci v

*STbcδ

2 / 3tω π−

11 4~ ng g

PIDSwitching Patterns

Generator

Phase a-b Q Calculation

PLL

Gating Signals

Arm a-b Control

STabQ

*STabQ

,ST Lab abi v

*STabδmaxδ

minδtω

11 4~ ng g

maxδ

maxδ

minδ

minδ

Figure 5. The proposed DSTATCOM controller.

( )i tβ ( )Q t

( ) ( )i t i tα=

( )v tβ

( ) ( )v t v tα=

( )i t

( )v t 90o∠

90o∠ ×

×

+-( ) ( )v t i tα β

( ) ( )v t i tβ α

( )P t×

×

( ) ( )v t i tα α

( ) ( )v t i tβ β

+

Figure 6. Fast power calculation method.

4. Simulation Verification

Figure 7 shows the simulation system, which was developed in the MATLAB/SimuLink program for a preliminary verification of the proposed DSTATCOM. A single-phase inductive load was used in the testing. First, the DSTATCOM main circuit was built according to Figure 3. In the simulation, the switch (SW) in Figure 7 was closed at t = 0.605 s to make a step response caused by the single-phase load. With the setting, the transient and steady-state performances of the DSTATCOM compensation were observed from the simulation results. Appendix A lists the system parameters.

Figure 6. Fast power calculation method.

4. Simulation Verification

Figure 7 shows the simulation system, which was developed in the MATLAB/SimuLink programfor a preliminary verification of the proposed DSTATCOM. A single-phase inductive load was used inthe testing. First, the DSTATCOM main circuit was built according to Figure 3. In the simulation, theswitch (SW) in Figure 7 was closed at t = 0.605 s to make a step response caused by the single-phaseload. With the setting, the transient and steady-state performances of the DSTATCOM compensationwere observed from the simulation results. Appendix A lists the system parameters.Energies 2019, 12, x FOR PEER REVIEW 8 of 16

b

a

c

STcaQ ST

abQ

SW LabZ

Sai

Sbi

Sci

SaXS

anv

Sbnv

Scnv

Lai

SbX

ScX

Lanv

Lbnv

Lcnv

,Labv L

aiSTci

STai

STbi

DSTATCOMController(Figure 5)

Lbi

Labv+

-

, ,STab bc cai

, ,Lab bc cav

GatingSignalsDSTATCOM

STbcQ

PT/CT

n

Figure 7. DSTATCOM simulation system setup.

Figures 8 and 9 are the simulation results. Figure 8a shows the transient load current response. With the assistance of the DSTATCOM, the three-phase source current was corrected to be balanced with a unity power factor, as shown in Figure 8b. Figure 8c depicts the synthesized line current of the DSTATCOM. Figures 8d and 8e show the power flows from the power source to the load, which reveal that the DSTATCOM very rapidly compensated the reactive power demand of the load. Figure 9 shows the compensation response in the DSTATCOM. Figure 9a is a recording of the internal voltage responses in the three DSTATCOM arms. When the single-phase load was switched in, the three DSTATCOM arms changed to phase-independent operation, as shown in Figure 9a, b. Figure 9c–e reveal other DSTATCOM responses in the single-phase load compensation for reference.

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

Curre

nt (A

)

0.0

-7.0

-14

7.014 /10L

anv

Lai

Lbi

0Lci =

0.70

(a)

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

Curre

nt (A

)

0.0

-7.0

-14

7.0

14/14L

avSai S

biSci

0.70

(b)

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

Curre

nt (A

)

0.0

-5.0

-10

5.0

10 STbiST

aiSTci

0.70

(c)

Figure 7. DSTATCOM simulation system setup.

Figures 8 and 9 are the simulation results. Figure 8a shows the transient load current response.With the assistance of the DSTATCOM, the three-phase source current was corrected to be balancedwith a unity power factor, as shown in Figure 8b. Figure 8c depicts the synthesized line current of theDSTATCOM. Figure 8d,e show the power flows from the power source to the load, which reveal thatthe DSTATCOM very rapidly compensated the reactive power demand of the load. Figure 9 shows thecompensation response in the DSTATCOM. Figure 9a is a recording of the internal voltage responsesin the three DSTATCOM arms. When the single-phase load was switched in, the three DSTATCOMarms changed to phase-independent operation, as shown in Figure 9a,b. Figure 9c–e reveal otherDSTATCOM responses in the single-phase load compensation for reference.

The simulation results in Figures 8 and 9 clearly indicate that the proposed DSTATCOM discussedin this paper is suitable for single-phase load compensation. It is also observed that the unbalancedoperation of the three DSTATCOM arms produce high-order harmonic currents. The harmonic currentstend to flow into the system and aggravate the electric power quality. An adequate front-end filter canbe installed to lessen the harmonic current pollution. Increasing the cascade numbers of the FHB cellsin the DSTATCOM main circuit can markedly reduce the high-order harmonic currents.

Energies 2019, 12, 4705 8 of 15

Energies 2019, 12, x FOR PEER REVIEW 8 of 16

b

a

c

STcaQ ST

abQ

SW LabZ

Sai

Sbi

Sci

SaXS

anv

Sbnv

Scnv

Lai

SbX

ScX

Lanv

Lbnv

Lcnv

,Labv L

aiSTci

STai

STbi

DSTATCOMController(Figure 5)

Lbi

Labv+

-

, ,STab bc cai

, ,Lab bc cav

GatingSignalsDSTATCOM

STbcQ

PT/CT

n

Figure 7. DSTATCOM simulation system setup.

Figures 8 and 9 are the simulation results. Figure 8a shows the transient load current response. With the assistance of the DSTATCOM, the three-phase source current was corrected to be balanced with a unity power factor, as shown in Figure 8b. Figure 8c depicts the synthesized line current of the DSTATCOM. Figures 8d and 8e show the power flows from the power source to the load, which reveal that the DSTATCOM very rapidly compensated the reactive power demand of the load. Figure 9 shows the compensation response in the DSTATCOM. Figure 9a is a recording of the internal voltage responses in the three DSTATCOM arms. When the single-phase load was switched in, the three DSTATCOM arms changed to phase-independent operation, as shown in Figure 9a, b. Figure 9c–e reveal other DSTATCOM responses in the single-phase load compensation for reference.

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

Curre

nt (A

)

0.0

-7.0

-14

7.014 /10L

anv

Lai

Lbi

0Lci =

0.70

(a)

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

Curre

nt (A

)

0.0

-7.0

-14

7.0

14/14L

avSai S

biSci

0.70

(b)

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

Curre

nt (A

)

0.0

-5.0

-10

5.0

10 STbiST

aiSTci

0.70

(c) Energies 2019, 12, x FOR PEER REVIEW 9 of 16

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

P(kW

) , Q

(kV

Ar)

0.0

-0.5

0.5

1.01

LP φ

1LQ φ

0.70

(d)

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

P(kW

) , Q

(kV

Ar)

0.0

-0.6

0.6

1.23SP φ

3 0SQ φ ≅0.70

(e)

Figure 8. DSTATCOM compensation response. (a) Three-phase load current ( , ,La b ci ); (b) Three-phase

source current ( , ,Sa b ci ); (c) Line current of DSTATCOM ( ST

a,b,ci ); (d) Power ( 1LPφ , 1

LQ φ ) to the single-phase

load; (e) Power ( 3SP φ , 3

SQ φ ) from the source.

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

Vol

tage

(V)

0.0

-110

-220

110

220 STbcvST

abv STcav

0.70

(a)

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

Curre

nt (A

)

0.0

-5.0

-10

5.0

10 STbciST

abiSTcai

0.70

(b)

Time (s)0.58 0.6 0.62 0.64 0.66 0.68 0.70

*STabQ

Reac

tive

Pow

er (k

VA

r)

*STbcQ

0.60.0-0.6

*STcaQ

0.60.0-0.6

0.60.0-0.6

(c)

Figure 8. DSTATCOM compensation response. (a) Three-phase load current (iLa,b,c); (b) Three-phase

source current (iSa,b,c); (c) Line current of DSTATCOM (iSTa,b,c); (d) Power (PL

1φ, QL1φ) to the single-phase

load; (e) Power (PS3φ, QS

3φ) from the source.

Figure 10 shows the steady-state power flow with the DSTATCOM compensation. It canbe observed that the DSTATCOM offers a path to rearrange the power flow for single-phaseload compensation.

Energies 2019, 12, 4705 9 of 15

Energies 2019, 12, x FOR PEER REVIEW 9 of 16

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

P(kW

) , Q

(kV

Ar)

0.0

-0.5

0.5

1.01

LP φ

1LQ φ

0.70

(d)

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

P(kW

) , Q

(kV

Ar)

0.0

-0.6

0.6

1.23SP φ

3 0SQ φ ≅0.70

(e)

Figure 8. DSTATCOM compensation response. (a) Three-phase load current ( , ,La b ci ); (b) Three-phase

source current ( , ,Sa b ci ); (c) Line current of DSTATCOM ( ST

a,b,ci ); (d) Power ( 1LPφ , 1

LQ φ ) to the single-phase

load; (e) Power ( 3SP φ , 3

SQ φ ) from the source.

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

Vol

tage

(V)

0.0

-110

-220

110

220 STbcvST

abv STcav

0.70

(a)

Time (s)0.58 0.6 0.62 0.64 0.66 0.68

Curre

nt (A

)

0.0

-5.0

-10

5.0

10 STbciST

abiSTcai

0.70

(b)

Time (s)0.58 0.6 0.62 0.64 0.66 0.68 0.70

*STabQ

Reac

tive

Pow

er (k

VA

r)

*STbcQ

0.60.0-0.6

*STcaQ

0.60.0-0.6

0.60.0-0.6

(c)

Energies 2019, 12, x FOR PEER REVIEW 10 of 16

Time (s)0.58 0.6 0.62 0.64 0.66 0.68 0.70

*STabδ

*STbcδ

Pow

er A

ngle

(Deg

)

100.0-10

*STcaδ

100.0-10

100.0-10

(d)

Time (s)0.58 0.6 0.62 0.64 0.66 0.68 0.70

705030

DC-

Link

Vol

tage

(V)

705030705030

1,2,3dc

abV

1,2,3dc

bcV

1,2,3dc

caV

(e)

Figure 9. DSTATCOM compensation response. (a) Internal voltage ( STab,bc,cav ); (b) Current ( ST

ab,bc,cai ); (c) Compensation command ( *

, ,STab bc caQ ); (d) Power angle command ( *

, ,STab bc caδ ); (e) DC-link voltages of full-

H-bridge (FHB) cells.

The simulation results in Figures 8 and 9 clearly indicate that the proposed DSTATCOM

discussed in this paper is suitable for single-phase load compensation. It is also observed that the unbalanced operation of the three DSTATCOM arms produce high-order harmonic currents. The harmonic currents tend to flow into the system and aggravate the electric power quality. An adequate front-end filter can be installed to lessen the harmonic current pollution. Increasing the cascade numbers of the FHB cells in the DSTATCOM main circuit can markedly reduce the high-order harmonic currents.

Figure 10 shows the steady-state power flow with the DSTATCOM compensation. It can be observed that the DSTATCOM offers a path to rearrange the power flow for single-phase load compensation.

Figure 9. DSTATCOM compensation response. (a) Internal voltage (vSTab,bc,ca); (b) Current (iST

ab,bc,ca);

(c) Compensation command (QST∗ab,bc,ca); (d) Power angle command (δST∗

ab,bc,ca); (e) DC-link voltages offull-H-bridge (FHB) cells.

Energies 2019, 12, 4705 10 of 15Energies 2019, 12, x FOR PEER REVIEW 11 of 16

+

+

+

SanV

SbnV

ScnV

3.71 0S oaI = ∠

235.48 0SaS j= +

3.71 120S obI = ∠ −

235.48 0SbS j= +

6.86 9.4L oaI = ∠

430.0 70.9LaS j= −

6.86 170.6L obI = ∠ −

276.4 337.0LbS j= +

2.42 120

3.71 0

3.71 60

STab

STbc

STca

I

I

I

= ∠ °

= ∠ °

= ∠ °

407j+ 266j−407j−

3.71 120S ocI = ∠

235.48 0ScS j= +

SabV

SbcV

15 5.65

LZj

=+

705.8 266

LabS

j=

+

c

a

b

110 30

110 90

110 150

S oab

S obc

S oca

V

V

V

= ∠ = ∠ −

= ∠

Figure 10. Steady-state power flow with DSTATCOM compensation.

5. Hardware Experimental Results

Figure 11 shows the hardware prototype test system constructed in the laboratory, and Appendix B lists the system parameters used. A single-phase load was used for verification testing in the physical experiment. The SDBC-MMCC-based DSTATCOM main circuit had a seven-level, transformerless configuration with a delta connection. In the hardware implementation of the DSTATCOM main circuit, insulated-gate bipolar transistors (IGBTs) were used. The DSTATCOM controller was a multi-TMS320F2812 DSP-based system with a sampling time of 0.52 ms to digitize the three PID controllers in Figure 5. The control program in the multi-DSP-based controller was first developed in C language on a host PC. The execution file was downloaded to the multi-DSP-based controller through Joint Test Action Group (JTAG) data links. Two multi-channel digital scopes were employed to record the transient responses of the DSTATCOM. During the DSTATCOM operation, some selected on-line calculation results in the controller were sent to the host PC for further evaluation.

STbci

STcai ST

abi

SaiSbiSci

SavSbvScv

Lai

b

a

c

Master ControllerTMS320F2812

LavLbvLcv

STci

STai

STbi

Slaver ControllerTMS320F2812

Each ArmGating Signals

DSTATCOM Main Circuit

, ,STab bc cai , ,

Lab bc cav

*, ,

STab bc caQ

... ...

...

, ,Sa b cX

CT,PT

LZφSW

Host PC

Single-PhaseLoad

JTAG

,Lbc cav

,L Lab abv i

Labv

+

-

Arm a-bArm b-c

Arm c-a Figure 11. Functional block diagram of the DSTATCOM hardware prototype test system.

Figure 10. Steady-state power flow with DSTATCOM compensation.

5. Hardware Experimental Results

Figure 11 shows the hardware prototype test system constructed in the laboratory, and Appendix Blists the system parameters used. A single-phase load was used for verification testing in the physicalexperiment. The SDBC-MMCC-based DSTATCOM main circuit had a seven-level, transformerlessconfiguration with a delta connection. In the hardware implementation of the DSTATCOM maincircuit, insulated-gate bipolar transistors (IGBTs) were used. The DSTATCOM controller was amulti-TMS320F2812 DSP-based system with a sampling time of 0.52 ms to digitize the three PIDcontrollers in Figure 5. The control program in the multi-DSP-based controller was first developedin C language on a host PC. The execution file was downloaded to the multi-DSP-based controllerthrough Joint Test Action Group (JTAG) data links. Two multi-channel digital scopes were employedto record the transient responses of the DSTATCOM. During the DSTATCOM operation, some selectedon-line calculation results in the controller were sent to the host PC for further evaluation.

Energies 2019, 12, x FOR PEER REVIEW 11 of 16

+

+

+

SanV

SbnV

ScnV

3.71 0S oaI = ∠

235.48 0SaS j= +

3.71 120S obI = ∠ −

235.48 0SbS j= +

6.86 9.4L oaI = ∠

430.0 70.9LaS j= −

6.86 170.6L obI = ∠ −

276.4 337.0LbS j= +

2.42 120

3.71 0

3.71 60

STab

STbc

STca

I

I

I

= ∠ °

= ∠ °

= ∠ °

407j+ 266j−407j−

3.71 120S ocI = ∠

235.48 0ScS j= +

SabV

SbcV

15 5.65

LZj

=+

705.8 266

LabS

j=

+

c

a

b

110 30

110 90

110 150

S oab

S obc

S oca

V

V

V

= ∠ = ∠ −

= ∠

Figure 10. Steady-state power flow with DSTATCOM compensation.

5. Hardware Experimental Results

Figure 11 shows the hardware prototype test system constructed in the laboratory, and Appendix B lists the system parameters used. A single-phase load was used for verification testing in the physical experiment. The SDBC-MMCC-based DSTATCOM main circuit had a seven-level, transformerless configuration with a delta connection. In the hardware implementation of the DSTATCOM main circuit, insulated-gate bipolar transistors (IGBTs) were used. The DSTATCOM controller was a multi-TMS320F2812 DSP-based system with a sampling time of 0.52 ms to digitize the three PID controllers in Figure 5. The control program in the multi-DSP-based controller was first developed in C language on a host PC. The execution file was downloaded to the multi-DSP-based controller through Joint Test Action Group (JTAG) data links. Two multi-channel digital scopes were employed to record the transient responses of the DSTATCOM. During the DSTATCOM operation, some selected on-line calculation results in the controller were sent to the host PC for further evaluation.

STbci

STcai ST

abi

SaiSbiSci

SavSbvScv

Lai

b

a

c

Master ControllerTMS320F2812

LavLbvLcv

STci

STai

STbi

Slaver ControllerTMS320F2812

Each ArmGating Signals

DSTATCOM Main Circuit

, ,STab bc cai , ,

Lab bc cav

*, ,

STab bc caQ

... ...

...

, ,Sa b cX

CT,PT

LZφSW

Host PC

Single-PhaseLoad

JTAG

,Lbc cav

,L Lab abv i

Labv

+

-

Arm a-bArm b-c

Arm c-a Figure 11. Functional block diagram of the DSTATCOM hardware prototype test system. Figure 11. Functional block diagram of the DSTATCOM hardware prototype test system.

Energies 2019, 12, 4705 11 of 15

Figures 12 and 13 reveal the hardware experimental results. Figure 12 shows the current responseswith DSTATCOM compensation. In Figure 12a, the switching-in of the single-phase load created anunbalanced operation. The single-phase load operation requires active power with a lagging powerfactor. Figure 12b illustrates the source current response; the phase-a-to-ground voltage waveformwas recorded at the same time for reference. With the real-time compensation of the DSTATCOM, thesource current was corrected very quickly to be balanced with a unity power factor. Figure 12c showsthe transient response of the synthesized DSTATCOM line current in the compensation. Table 1 recordsthe steady-state DSTATCOM compensation result in Figure 12. The current unbalanced ratio IUR(%),expressed in Equation (20) indicates the effect of current balancing in the power source. The unbalancedratio of the load current, IL

UR(%), was 100%. With DSTATCOM compensation, the unbalanced ratio ofthe source current, IS

UR(%), was substantially improved to a nearly perfect value of 3.26%.

IUR(%) = Max(∣∣∣Ia − Iavg

∣∣∣, ∣∣∣Ib − Iavg∣∣∣, ∣∣∣Ic − Iavg

∣∣∣)/Iavg × 100% (20)

Energies 2019, 12, x FOR PEER REVIEW 12 of 16

Figures 12 and 13 reveal the hardware experimental results. Figure 12 shows the current responses with DSTATCOM compensation. In Figure 12a, the switching-in of the single-phase load created an unbalanced operation. The single-phase load operation requires active power with a lagging power factor. Figure 12b illustrates the source current response; the phase-a-to-ground voltage waveform was recorded at the same time for reference. With the real-time compensation of the DSTATCOM, the source current was corrected very quickly to be balanced with a unity power factor. Figure 12c shows the transient response of the synthesized DSTATCOM line current in the compensation. Table 1 records the steady-state DSTATCOM compensation result in Figure 12. The current unbalanced ratio (%)URI , expressed in Equation (20) indicates the effect of current balancing in the power source. The unbalanced ratio of the load current, (%)L

URI , was 100%. With DSTATCOM compensation, the unbalanced ratio of the source current, (%)S

URI , was substantially improved to a nearly perfect value of 3.26%.

Time (ms)0.0 25 50 75 100 125

Curre

nt (A

)

0.0

-12.5

12.5 /10Lanv

Lai L

bi 0Lci =

150

(a)

Time (ms)0.0 25 50 75 100 125

Curre

nt (A

)

0.0

-12.5

12.5 /10Lav S

aiSbi

Sci

150

(b)

Time (ms)0.0 25 50 75 100 125

Curre

nt (A

)

0.0

-10

10 STaiST

biSTci

150

(c)

Figure 12. Transient responses with DSTATCOM compensation. (a) Single-phase load current ( , ,La b ci

); (b) Source current ( , ,Sa b ci ); (c) DSTATCOM line current ( , ,

STa b ci ).

(%) ( , , ) / 100%UR a avg b avg c avg avgI Max I I I I I I I= − − − × (20)

Table 1. DSTATCOM compensation result in the hardware test.

Load LaI L

bI LcI (%)L

URI 6.46 6.43 0 100%

Source SaI S

bI ScI (%)S

URI 4.1 3.85 4.0 3.26%

Figure 13 shows other responses in the DSTATCOM main circuit. The three DSTATCOM arms changed to phase-independent operation when the single-phase load was switched in. The physical test results agreed with the simulation results presented in Figure 9. The transient compensation response of the DSTATCOM was quite fast. The delta-connected DSTATCOM main circuit and the harmonics-minimizing method eliminated the specified harmonic components in the synthesized

Figure 12. Transient responses with DSTATCOM compensation. (a) Single-phase load current (iLa,b,c);

(b) Source current (iSa,b,c); (c) DSTATCOM line current (iSTa,b,c).

Table 1. DSTATCOM compensation result in the hardware test.

Load ILa IL

b ILc IL

UR(%)6.46 6.43 0 100%

Source ISa IS

b ISc IS

UR(%)4.1 3.85 4.0 3.26%

Energies 2019, 12, 4705 12 of 15

Energies 2019, 12, x FOR PEER REVIEW 13 of 16

DSTATCOM line currents, as shown in Figures 13b,c. However, high-order harmonic currents were unavoidably generated in the three DSTATCOM arms.

The hardware experimental results verified that the proposed SDBC-MMCC-based DSTATCOM is suitable for real-time phase balancing and power factor correction of single-phase loads in three-phase, three-wire power distribution systems.

Time (ms)0.0 25 50 75 100 125

Vol

tage

(V)

0.0

-250

250STabv

150

STcav

STbcv

(a)

Time (ms)0.0 25 50 75 100 125

Curre

nt (A

)

0.0

-10

10STabi

STbciST

cai

150

(b)

Time (ms)0.0 25 50 75 100 125V

olta

ge (V

), Cu

rrent

(A)

0.0

-12.5

12.5 / 20STabv

STabi

150

(c)

Time (ms)0.0 25 50 75 100 125

Reac

tive

Pow

er (V

Ar)

150

*STabQ

*STbcQ

*STcaQ

Capacitive

Inductive

-530VAr

Capacitive

+530VAr

(d)

Time (ms)0.0 25 50 75 100 125

30150

5070

DC-

Link

Vol

tage

(V)

30

507030

5070

1,2,3dc

abV

1,2,3dc

bcV

1,2,3dc

caV

(e)

Figure 13. Transient responses of the DSTATCOM. (a) Internal voltage ( , ,STab bc cav ); (b) Arm current (

, ,STab bc cai ); (c) Arm a-b voltage and current ( ST

abv , STabi ); (d) Compensation command ( *

, ,STab bc caQ ); (e) DC-link

voltages ( 1,2,3dc

abV , 1,2,3dc

bcV , 1,2,3dc

caV ).

Figure 13. Transient responses of the DSTATCOM. (a) Internal voltage (vSTab,bc,ca); (b) Arm current

(iSTab,bc,ca); (c) Arm a-b voltage and current (vST

ab , iSTab ); (d) Compensation command (QST∗

ab,bc,ca); (e) DC-link

voltages (Vdcab1,2,3, Vdc

bc1,2,3, Vdcca1,2,3).

Figure 13 shows other responses in the DSTATCOM main circuit. The three DSTATCOM armschanged to phase-independent operation when the single-phase load was switched in. The physicaltest results agreed with the simulation results presented in Figure 9. The transient compensation

Energies 2019, 12, 4705 13 of 15

response of the DSTATCOM was quite fast. The delta-connected DSTATCOM main circuit and theharmonics-minimizing method eliminated the specified harmonic components in the synthesizedDSTATCOM line currents, as shown in Figure 13b,c. However, high-order harmonic currents wereunavoidably generated in the three DSTATCOM arms.

The hardware experimental results verified that the proposed SDBC-MMCC-based DSTATCOM issuitable for real-time phase balancing and power factor correction of single-phase loads in three-phase,three-wire power distribution systems.

6. Conclusion

In a three-phase, three-wire electric power distribution system, a newly designedSDBC-MMCC-based DSTATCOM employing staircase modulation and an indirect phasor-domainpower angle regulation method for real-time single-phase load compensation was studied. An effectivefeedforward compensation algorithm was proposed for the DSTATCOM. The computer simulationresults showed that the function of the proposed DSTATCOM was quite satisfactory. Finally, ahardware test system was built for functional verification. The proposed DSTATCOM showed a fasttransient response and a satisfactory steady-state compensation effect. However, the simulation andexperimental results also revealed that unbalanced operation of the DSTATCOM induced unbalancedharmonic currents in the three DSTATCOM arms. Thus, in practical applications, harmonic filtersshould be installed to enhance the electric power quality. Increasing the cascade numbers of the FHBcells in each DSTATCOM main circuit arm can also reduce undesired harmonic currents.

Author Contributions: W.-N.C. conceived this paper and composed the study system; C.-H.L. conducted thetheoretical study, computer simulation, and hardware implementation; all authors wrote the paper.

Funding: The financial support from the Ministry of Science and Technology (MOST), Taiwan, is acknowledged.

Acknowledgments: Valuable comments and discussions from the reviewers are appreciated.

Conflicts of Interest: The authors declare no conflict of interest.

Nomenclature

General:P active powerQ reactive powerv instantaneous voltagei instantaneous currentδ power angleV voltage phasorI current phasorC dc-link capacitorX reactanceRe real partIm imaginary partSuperscripts:S power sourceL loadll line to lineST DSTATCOMST∗ DSTATCOM commanddc dc link∗ complex conjugateSubscripts:3φ three-phase1φ single-phase0, 1, 2 Zero, positive, negative sequences

Energies 2019, 12, 4705 14 of 15

Appendix A. Simulation System Parameters

System side:

VSll = 110V, fS = 60Hz, XS

a,b,c = 0.1Ω, ZLab = 15 + j5.655Ω

DSTATCOM side:

Cab1,2,3 = Cbc1,2,3 = Cca1,2,3 = 3, 300µF, XSTab,bc,ca = 3.77Ω, θ1 = 11.68

, θ2 = 31.18

, θ3 = 58.58

, KP = 1.0,KI = 0.65, KD = 0.0007

Appendix B. Experimental System Parameters

System side:

VSll = 110V, fS = 60Hz, XS

a,b,c = 0.1Ω, ZLab = 15 + j5.655Ω

DSTATCOM side:

Cab1,2,3 = Cbc1,2,3 = Cca1,2,3 = 3, 300µF, XSTab,bc,ca = 3.77Ω, θ1 = 11.68

, θ2 = 31.18

, θ3 = 58.58

, KP = 0.8,KI = 0.65, KD = 0.0007

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