Development and Characterization of STT-RAM Cells
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Transcript of Development and Characterization of STT-RAM Cells
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Development and Characterization of STT-RAM Cells
Ilya Krivorotov
Team Members:Kang L Wang (PI) - UCLAPedram Khalili (PM) – UCLA Ken Yang (Investigator) - UCLADejan Markovic (Investigator) - UCLAHongwen Jiang (Investigator) - UCLAYaroslav Tserkovnyak (Investigator) - UCLAIlya Krivorotov (Investigator) - UC IrvineJian-Ping Wang (Investigator) - University of Minnesota
IBM Trusted Foundry (Fabrication Vendor)Rep by Scott Marvenko
SVTC/Singulus (Fabrication Vendor)Rep by Eric Kent, Mike Moore
MICRON and Intel (Supporting and on Advisory Board)Rep by Gurtej Sandhu & Mike Violette (MICRON)Rep by George Bourianoff, Tahir Ghani, Tanay Karnik (Intel)
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Outline• STT-RAM optimization to approaching Phase 1 metrics
– Free layer dimensions (area, aspect ratio, thickness)– Optimal MgO thickness– Optimal write voltage pulse amplitude and duration– Energy-efficient switching with perpendicular polarizer
• Measurement techniques – Thermal stability– Switching with short voltage pulses
• Recent results and metrics update• Summary and Outlook
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Where we were 3 month ago
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1.22 V 1.10 V 0.96 V 0.83 V 0.77 V 0.71 V
At the pervious review meeting we were reported initial results of non-optimized I-STT-RAM cells. They showed the following metrics parameters:
- Write energy per bit 7.5 pJ- Write time 2.5 ns- Upper bound on thermal stability: < 90- Lower bound on endurance of 105
Since the review meeting in November 2009, we have substantially improved the metrics through STT-RAM device optimization
Voltage at the sample, Vs
Data reported in November 2009
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
STT-RAM Optimization: Free Layer Dimensions
VMe
PI sc
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Tk
MV
lwd
Tk
VMH
B
s
B
sK211
~2
- For a given material, to reduce Ic one should decrease the free layer volume V without sacrificing thermal stability d
w
l
- critical current for I-STT-RAM
-To decrease volume V while keeping constant, we must increase thickness and decrease width w. The width has been decreased to 50 nm.
- Thermal stability
Fundamental constants and material parameters
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
STT-RAM Optimization: Barrier Thickness
RA VS MgO thickness
TMR ratio VS MgO thickness
We found that the optimal MgO thickness for I-STT-RAM devices is right at the knee in RA and TRM plots versus MgO thickness (3 *m2).
- Since energy per write is I2R tw, low RA MgO also decreases energy per write- Low TMR is signature of pinholes an lower-voltage dielectric breakdown- MgO thickness with lowest RA that still has high TMR is needed
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R (
%)
tMgO
(nm)
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(m
2 )
tMgO
(nm)
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
STT-RAM Optimization: Write Pulse Shaping
For short switching times, switching time versus pulse duration is well fit by the following functional dependence:
1/ 0
VVd
This is a signature of quasi-ballistic switching dominated by angular momentum transfer rather than temperature
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Sw
itch
ing
tim
e (n
s)Pulse Amplitude (V)
This (V) allows us to determine the optimal write voltage V for minimizing the energy per write
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V0 is the (zero-temperature) critical voltage for switching
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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rite
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rgy
(arb
.u.)
Voltage (arb. u.)
STT-RAM Optimization: Write Pulse Shaping
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0 1V V
Energy per write: R
VE
2
Write time: 1/ 0
02
VVR
VE
- E(V) has a minimum at V=2V0
- Minimum energy per write is at twice the critical voltage- This is consistent with our data
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
STT-RAM Optimization: Write Pulse Shaping
Experimental data Theory
Predicted write energy minimum is experimentally observed
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Wri
te E
ner
gy
(pJ)
Pulse Amplitude (V)
Phase I target
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Wri
te E
nerg
y (a
rb.u
.)
Voltage (arb. u.)
Sample size65nm*160nm Ewrite = 0.46 pJ
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
STT-RAM Optimization: Non-collinear structures
Micromagnetic simulations show that for collinear free and fixed layer geometries:
- there is long incubation time between the leading edge of the write pulse and the nanomagnet switching
- energy is wasted on excitation of non-uniform modes
AFM
PL Barrier FL
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Switching I=1.4mA, Pulse t=1ns, Field Torque 0.1
Z A
xis
Y AxisX Axis
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
STT-RAM Optimization: Non-collinear structures
Collinear free and fixed layers, I-STT-RAM simulations
Non-collinear free and fixed layers,C-STT-RAM simulations
The incubation time results from small initial spin torque in the collinear geometry (spin torque )Polarizer that is non-collinear with the free layer provides larger spin torque, accelerates the switching process
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MS
Time (ns)
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Time (ns)
Mx/
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
C-STT Cell DevelopmentWe have successfully implemented the C-STT device idea.
The C-STT-RAM device uses a perpendicular polarizer layer to push free layer magnetization out of the sample plane and precessionally switch it in half precession cycle (fast switching).
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Materials for non-collinear structuresWe developed materials with perpendicular anisotropy for C-STT-RAM structures with non-collinear magnetizations based on Co/Pd multilayers
perpendicularfiled
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em
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PerIn
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
C-STT Device Hysteresis LoopHysteresis loop of resistance versus field of C-STT-RAM cell shows features consistent with fully or partially perpendicular polarizer
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Re
sist
an
ce ()
Magnetic Field (Oe)
Perpendicular polarizer layerFree layer
SAF reference/in-plane polarizer
Sample size70nm*180nm
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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1.29 V 1.47 V 1.64 V
- Our measurements of switching of devices with non-collinear magnetization revealed deep sub-ns switching.
- This is a salient feature of precessional switching due to perpendicular polarizer
- Pulse shaping is expected to further improve the energy per write
Device shape and magnetic multilayer optimization is also expected to significantly improve the non-collinear device performance compared to this initial demonstration. This device concept is very promising for meeting Phase 2 metrics.
STT-RAM Optimization: C-STT-RAM structures
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Sample size70nm*180nm
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Measurement Techniques of Metrics
• Energy per write and write time– Switching in response to ns and sub-ns pulses
• Thermal stability measurements– Thermally activated switching– Field-assisted switching– Hard axis hysteresis loop measurement
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Switching by Short Voltage Pulse
Pulse Generator(0.1 – 10 ns pulse width)
Multimeter(resistance measurement)
DMM
STT-RAMelement
-Pulses of variable duration are sent to the sample
-Sample resistance before and after the switching is measured
- Probability of switching is determined
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Voltage of Short Pulse at the Sample- Voltage at the sample is a sum of incident and reflected voltages
- Since the sample resistance is much higher than 50 , the voltage at the sample is nearly doubled compared to the incident voltage
- We use a pulse generator that absorbs the reflected pulse without affecting the incident pulse
50
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s
sinins R
RVVV
Vs
Vin
Vref
s
s
R
VI
Rs
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.140
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Co
un
ts
Time before switching [s]
- Switching in response to long, relatively low-voltage pulses- Switching time histograms are measured and switching voltage versus pulse duration is obtained- Extrapolation of the plot of switching voltage versus pulse duration down to zero voltage, (V=0) gives the bit lifetime and thermal stability
Fitting to exponential function gives the average bit life time, , at a given voltage
Thermal Stability: Method 1 Thermally-Activated Switching
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0/)0(ln
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Method 1 Thermally-Activated Switching- Applying current-assisted switching, lower bound on thermal stability is determined.- This is only a lower bound due to current noise, ohmic heating and possible current-induced magnon excitation
Time [s]
Thermally Activated
Δ=63; ts(0 Volt) = 31 billion years
Quasi-ballistic switching
10,000,000 switching attempts
Ri Rf Ri Rf Ri Rf
Initial measurementFinal measurement
Reset Pulse
Train of 10,000 write/reset pulses
Single switching attempt sequence
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65 nm x 190 nm ellipse
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Method 2: coercivity vs field sweep rate
Another approach to determining thermal stability is to measure the sweep rate dependence of the coercive field. The coercive field under the sweep time based on the Neel-Arrhenius model is:
})]ln([1{)( 00n
u
Bc tf
VK
TkHtH
Coercivity vs sweep time. Resistance vs magnetic field at different sweep time.
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Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Thermal Stability: Method 3 Hard-axis Loop
Hard Axis Hysteresis Loop
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ista
nce
[]
Magnetic Field [Oe]
HL HR
Estimating the anisotropy field as:
2/RLK HHH
- Anisotropy field estimated by this method is ~ 570 Oe
- Micromagnetic OOMMF simulations give the hard-axis saturation field ~ 520 Oe.
-The origin of the hard-axis loop asymmetry is not clear
- Using 520 Oe value, the thermal stability estimate gives an upper bound on thermal stability
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free free
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Current status of STT CellsAs a result of a combination of aforementioned STT-RAM optimization procedures, device performance has been substantially improved since the last review meeting.
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Hc=-70-75 Oe
Hf=-104 Oe
MR=122%
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Device size: 65 nm by 160 nm, RA = 3.4 Ohm*m2
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Switching of Improved STT-RAM Cells
In the optimized devices, at the optimal voltage pulse amplitude, write energy of 0.46 pJ has been achieved.
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te E
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Pulse Amplitude (V)
Phase I target
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Vs=0.48 V
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itch
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Pulse Width (ns)
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0.46 pJ>55
Device size: 65 nm by 160 nm, RA = 3.4 Ohm*m2
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Two Thermal Stability Measurements of I-STTHard axis saturation – upper limit for Thermally activated switching –
lower limit for
HK 650 Oe as average of HL and HR -> 90
HK 550 Oe from micromagnetic simulations
Two measurements give the bounds on the thermal stability 55<<90
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ista
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Δ=55
Device size: 65 nm by 160 nm, RA = 3.4 Ohm*m2
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Metrics Update for STT-RAM
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Status at previous meeting(Nov 2009)
Status (Feb 1, 2010)
BAA Targets
Write Energy E=7.5 pJ/bit E=0.46 pJ/bit E=0.25 pJ/bit
Write Speed (tW)
2.5 ns/bit 1.3 ns/bit 5 ns/bit
Cell Size N.A.0.23 um2
(27F2)0.24 um2 (<28F2)
Memory Bit Area (A)
0.01 um2 0.01 um2 0.02 um2
Thermal Stability (∆)
N.A. 55 < ∆ < 90 60
Endurance >105 >107 1x1016
Wafer Yield >40% >40% 40%
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Summary• We made a significant progress towards optimizing
the performance of STT-RAM cell through device optimization:– Free layer dimensions (area, aspect ratio, thickness)– Optimal MgO thickness– Optimal write voltage pulse amplitude and duration– Energy-efficient switching with perpendicular polarizer
• All Phase 1 metrics are clearly within reach with modest further optimization.
• We are also on the way towards meeting Phase 2 metrics using C-STT-RAM structures.
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