Developing test systems for multi-modules hardware designs
description
Transcript of Developing test systems for multi-modules hardware designs
Developing test systems for multi-modules hardware designs
Mikhail Chupilko
Institute for System Programming of RAShttp://hardware.ispras.ru
Outline
•Introduction•How to perform hardware verification•Single design under test case•Plenty of designs under test case•Results of the approach application•Conclusion
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Introduction
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DesignUnderTest
Stimuli ReactionsMUT
MUT
MUT
MUT
MUT
MUT
mem_2p #(ADDR_SIZE,DATA_SIZE) mem(.DO(DO_tmp),.RD_A(RD_A),.WR_A(WR_A),.DI(DI_tmp),.RD_CLK(CLK),.WR_CLK(CLK),.CE_N_RD(~CE_RD_tmp),.CE_N_WR(~CE_WR_tmp),.OE_N(1'b0));
always @(posedge CLK) begin if(RST) begin DO_VAL <= 1'b0; DO_R_VAL <= 1'b0; IS_EMPTY <= 1'b1; IS_R_FULL <= 1'b0; IS_RR_FULL <= 1'b0;
How to perform…
•Formal approaches like Model checking•Simulation-based approaches
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MUT
SIMULATOR
Testbench elements
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MUT
SIMULATOR
TestStimuli
Generator
Stimuli ReactionChecker /
Oracle
Reactions
Test CompletenessEstimator
InformationInformation
Approach: the common view
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Stimuli generator
Reaction checker
Coverage tracker
Target design
Stimuli
Reactions
Stimuli
Verification report generator
Simulator
Coverage
Verdict
Stimuli generator
•Random-based generation•FSM-based generation
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ABCD
DUTState
Reaction checker
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Reaction checker
Precondition checkers
MS
Failed
Stimuli generator
Model adapter
Ref. model
Input interfaces models
Functional model
Output interfaces models
Reactions queues
Reaction matchers
Postcondition checkers
Input interfaces adapters
Reaction detectors
Output interfaces adapters
MR MR
MR MR
MR
MR
CR
DSInput interface
Target design
DROutput interface
VerdictStimuli generator
Primary arbiters
Secondary arbiters
Moving to multi-modules…
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Stimuli generator
Coverage tracker
Target design
Stimuli
Reactions
Stimuli
Verification report generator
Simulator
Coverage
Verdict
Common reactionchecker
RC RC RC
Connected stimuli generators
•Random-based generation•FSM-based generation
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ABCD
MUT1
State6
EFGH
MUT2
State5
State7
State8
State1
State2
State3
State4
State1
State2
State3
State4
Connected reaction checkers
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Common reaction checker
Precondition checkers
MS
Failed
Stimuli generator
Model adapter
Ref.model
Input interfaces models
Functional model
Output interfaces models
Reaction queues
Reaction matchers
Postcondition checkers
Inputinterfacesadapters
Reactiondetectors
Output interfacesadapters
MR MR
MR MR
MR
MR
CR
DSInputinterfaces
Targetdesign
DROutputinterfaces
Verdict
Stimuli generator
Primary arbiters
Secondary arbiters
Ref. model of unit A
Unit A funct. model
Overloaded outputinterfaces models
Ref. model of unit B
Unit B funct. model
Overloaded outputinterfaces models
MR MR
MR MR
Overloaded inputinterfaces models
Overloaded input interfaces models
Returning to the chip
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Stimuli ReactionsMUT
MUT
MUT
MUT
MUT
MUT
DesignUnderTest
Some results of the application
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Design under verification
Depth of verification
Source code, KLOC
Labor costs, man-months
Translation lookaside buffer (TLB)
Up to cycle-accurate
2.5 2.5
Non-blocking L2 cache
Up to detailed-timed
3 6
Northbridge data switch
Up to cycle-accurate
3 3
Memory access unit (MAU)
Up to cycle-accurate
1 1
Conclusions
•The approach is applicable in hardware verification;
•It supports both single modules as well as
their unions.
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Thank you!Any questions?
Open Verification MethodologyOVC
Master
TransactionSystemGenerator
Driver Monitor
Slave
TransactionSystemGenerator
Driver MonitorCoverageCollector
DUT