Developing Processing Electronics for BPM Prototype at the AWA RF Photo-Injector

Chuan Yin∗

Department of Physics, The University of Chicago

John Power and Jiahang ShaoArgonne Wakefield Accelerator facility, High Energy Division, Argonne National Laboratory

Chunguang JingEuclid Techlabs

(Dated: August 24, 2017)

A Beam Position Monitor (BPM) system is essential to beam diagnostics for almost all particleaccelerators, both linear and circular types. It is able to non-destructively and accurately detectthe centroid position and the charge of a passing beam. Too often, however, a typical BPM systemcontains customized hardware and specialized processing electronics. This results in a higher fab-rication cost and a barrier to creating electronics standards. For small accelerators such as R&Dlinacs, university accelerators (for research), medical and industrial accelerators (for business), strictconstraints are placed on compactness and cost-efficiency. Thus, Argonne Wakefield Accelerator fa-cility (AWA) aims to prototype a cheap, compact and universal BPM system via mass-producedhardware, fast integrated circuits, and noise-protected Wi-Fi communication. This month at AWA,we focused on developing the processing electronics and characterizing the BPM.

I. INTRODUCTION

A. Beam Position Monitor (BPM)

A Beam Position Monitor (BPM) detects the centroidposition of a beam non-destructively. Our in-flange typeBPM hardware has four pickup electrodes–up, down, leftand right–and everywhere else grounded. When a beampasses by, an image current of the same magnitude butopposite polarity is induced on the wall. The strengthof the signal picked up by an electrode depends on itsdistance away from the beam. Therefore, by developingthe processing electronics to analyze the pickup signals,one can deduced the beam position at a correspondingearlier time.

FIG. 1. Hardware for the BPM prototype

∗ Email me at chuanyin@uchicago.edu

B. AWA Witness Beamline

This experiment is done solely on the witness beamlineof the Argonne Wakefield Accelerator facility (AWA), op-erating in the single bunch mode with a typical chargevolume of 1 nC, an energy of about 13 MeV and a beamcurrent about 10 kA. The operating principle of the wit-ness beamline is the following: the laser beam from thelaser injector is reflected off a mirror to strike the semi-conducting photocathode of the RF-gun, emitting elec-trons which are then initially accelerated and focused bythe magnetic solenoid to about 8 MeV. After passingthrough the linear accelerating cavity (linac), the beampossesses an energy of about 13 MeV, and is further fo-cused by three quadrupoles. The diagnostic system ofthe witness beamline so far only consists of Yttrium Alu-minum Garnet (YAG) fluorescent screens, a destructivemethod of detecting the positions of each beam particle.Our prototype BPM system will be inserted after all ofthe quadrupoles.

FIG. 2. Labeled AWA witness beamline photo. Credit toJohn Power.

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II. MOTIVATION

The design of a BPM system should adapt to the func-tionalities and constraints of an accelerator. In otherwords, it is difficult and discouraged to simply apply theBPM designs used for first-class scientific experiments orhuge commercial light sources to small accelerators. Toooften, those BPM systems for big accelerators containcustomized hardware and specialized processing electron-ics, sometimes developed and maintained by a specialgroup of experts. This results in a higher fabricationcost and a barrier to creating electronics standards, bothof which are disadvantageous to obtaining greater marketshare in the small accelerator economy, with main play-ers being the R&D linacs and university accelerators onthe research side, as well as the medical and industrialaccelerators on the business side. For the small acceler-ators, strict constraints are placed on the compactnessand cost-efficiency for each component. In light of this,Argonne Wakefield Accelerator facility (AWA) aims toprototype a cheap, compact and universal BPM systemvia mass-produced hardware, fast integrated circuits, andnoise-protected Wi-Fi communication.

III. CURRENT PROGRESS

So far, the BPM system at AWA includes a button-type hardware installed on the beamline with four pick-up wires, but without further processing electronics.AWA has designed and fabricated a new in-flange button-type BPM hardware soon replacing the current one, witha cost of $1000, at least ten times cheaper than an oth-erwise customized hardware thanks to mass-production.More tests and calibration on the new hardware are pend-ing. For developing the processing electronics system,we performed a few sanity tests on the already-installedBPM hardware, to verify that it behaves the way as ex-pected. For an ideal BPM hardware, the signal pulsesshould have linear dependence on both the beam posi-tions and charge.

A. Beam-Position Dependence of the Signal Pulse

Qualitatively, the electrode that is the closest to thebeam centroid position picks up the largest signal ampli-tude, and the farthest one picks up the smallest. In ourtesting setup, we adjusted the upstream horizontal andvertical correctors to steer the beam, observed the beamposition on a downstream YAG screen, and recorded thescope traces for the four BPM pickup electrodes. Whilekeeping the beam fully inside the inner rim of the YAGscreen, we evenly divided the distance across and took13 data points on the horizontal axis and 13 on the verti-cal one (of course, the origin was an overlapping point).We recorded the positions in pixels then converted themto centimeters using a calibration scale. For each beam

position, we take 50 sets of scope traces to understandthe extent of jitter in beam positions. For example, FIG,3 shows one of the 50 traces when the beam is steeredto the very left position. As expected, the left electrodepicks up the largest signal, the right electrode the small-est, and the other two relatively the same.

FIG. 3. The scope traces from the four pickup electrodes andthe YAG screen image (center) with beam on the very left.

Since the main source of error to the signal strengthand the beam size is the fluctuation in the laser intensity,we employed a charge cut between two standard devia-tions of the charge scanned from the upstream ICT. Atypical charge signal from the ICT is displayed in FIG. 4.Then, the average amplitude for each of the four pickupsignals after the charge cut is plotted against each of thebeam positions, as shown in FIGs. 5 and 6.

FIG. 4. A typical charge pulse.

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FIG. 5. Amplitude of the four pickup signals as a function ofthe beam positions when steered horizontally.

FIG. 6. Amplitude of the four pickup signals as a function ofthe beam positions when steered vertically.

The reason why each of the trends is not very linearwith the beam positions might be due to the beam notcentered longitudinally. Therefore, the signal amplitudedepends on the angle between the passing beam and anelectrode [1]. To eliminate this confounding variable, wetake the difference in the signal amplitudes of the elec-trodes on the opposite ends, and plot that against thehorizontal and vertical beam positions, in FIGs 7 and 8.As expected, we observe a highly linear trend in the di-rection that the beam is steered, and a rather flat trendfor the other direction.

FIG. 7. The difference in signal amplitudes of the oppositeelectrodes as a function of the horizontal beam positions.

FIG. 8. The difference in signal amplitudes of the oppositeelectrodes as a function of the vertical beam positions.

Furthermore, a more accurate way of determining thebeam positions would be to use image processing soft-ware such as Matlab or Python to calculate the averagecenter position weighted by intensity, assuming that thenumber of particles hitting the YAG screen on a pixel isproportional to the intensity of the pixel. Such study willalso be important in determining the size of error in thebeam positions.

B. Charge Dependence of the Signal Pulse

The amplitude of the all four signals summed togethershould also linearly depend on the beam charge. To testthis, we performed a charge scan by applying five filtersto the injected laser, resulting in 78%, 63%, 32%, 16%,and less than 1% transparency. A combiner (FIG. 9) is

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inserted into the circuit taking the four BPM electrodesas its inputs, and it outputs to the scope as shown inFIG. 14. For each filter setup, we took 50 sets of signaldata and recorded the ICT waveform. The charge iscalculated by integrating the corresponding ICT pulse,up to a unit conversion factor and a DC backgroundsubtraction. We plotted the peak of the combineroutput against the integrated charge in FIG. 11. Due toinherent fluctuation of the laser intensity, the chargesproduced by five distinct filter settings become some-what continuous. Nevertheless, the linearity betweenthe summed signal amplitude and the beam charge isconfirmed with a r squared value of 0.98.

FIG. 9. A photo of the combiner.

FIG. 10. An example of the combiner output.

FIG. 11. Combiner signal amplitude as a function of charge.

In summary, the current BPM hardware satisfies thegeneral requirements that the differences in the signalamplitude of the opposite electrodes is linear with thebeam position in that direction, and that the sum of allfour signal amplitude is linear with the beam charge.

IV. WORKFLOW OF THE BPM PROTOTYPE

Although the pickup signals from the BPM hardwarebehave well, they are about 0.4 ns long that can onlybe seen by a scope with a sampling rate greater than atleast 2 GHz. For one, it is expensive and inconvenientfor small facilities to obtain fast oscilloscopes. On theother hand, displaying analog waveform in a commer-cial daily basis is an overkill since the only informationneeded from the waveform is its peak value, let alonethat analog circuits are susceptible to noise. Hence, wedecide to employ clever processing electronics to digitizethe signal amplitude. However, it is a challenging task tokeep the price of the design low. For a reasonably pricedanalog-to-digital converter (ADC), such as our ADS7951chip, its sampling rate is only 1 MHz. Furthermore, sincethe ADS7951 is mounted on the Intel-Edison board, thespeed is also limited by any constraints from the inter-face, resulting in an actual sampling rate of merely onthe order of kHz, which obviously cannot see the 0.4 nssignal. Therefore, in order to pass the signal amplitudeinformation to further electronics, either the samplingrate needs to be multiplied by 7 orders of magnitudes,or the short pulse needs to be elongated by 7 orders ofmagnitudes. Because the former approach requires muchhigher budgets, as experienced by larger accelerator facil-ities, we resort to the latter approach, by including basicelectronics component such as four envelope detectors,four one-shot multi-vibrators, and four sample-and-holdchips.

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FIG. 12. Workflow of the BPM system.

A. Envelope Detector

The ADL5511 chip, displayed in FIG. 13, outputs avoltage that is proportional to the envelope of the inputsignal, and can operate from dc to 6 GHz on signals withenvelope bandwidths up to 130 MHz, suitable for ourusage on the 0.4 ns pulse.

FIG. 13. A photo of the envelope detector chip.

FIG. 14. A pickup signal.

FIG. 15. A signal after the envelope detector.

As shown in FIGs 14 and 15, the envelope detectorelongates a 0.4 ns-long BPM signal to an exponentiallydecay analog pulse with a sharp rising edge. The lengthof the output pulse is about 400 ns, and supposedly theamplitudes of the input and the output are proportional.More direct testing of the proportional relationshipis needed, but if so, we would be able to achieve athree-orders-of-magnitude improvement on the dutycycle. The rest of the signal elongation is done by asample-and-hold circuit.

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B. Sample-and-Hold Amplifier

A sample-and-hold amplifier (SHA), or sample-and-hold for short, is a common companion to an ADC,which triggers at one point of time of the input pulseand holds the signal voltage for longer. As demonstratedin FIG. 16, the SHA takes an analog 400 ns signal pulseand digital 100 ms pulse as an enable (EN). When theenable pulse is LOW, the SHA chip follows the signal;when the enable is HIGH, the SHA chip holds theinstantaneous voltage multiplied by the amplificationgain for the time the signal stays HIGH, i.e. 100ms in our case. We decided upon a holding time of100 ms due to the following constraints. The ADClater in the circuit has a sampling frequency of a fewkHz, so in order for our pulse to be stably visible, thewidth of the SHA enable pulse has to be longer than 1ms–and the longer the duty cycle the better. On theother end, the ADC takes only serial input and ouraccelerated bunch operates with a 500 ms period, soto allow enough time for us to combine all four analogSHA outputs into one and feed it to the ADC withinone cycle, the width of the SHA enable pulse needs tobe shorter than at least 125 ms. We also decided ontriggering on the downward side of the signal becauseit would have less voltage error given the same time jitter.

FIG. 16. A function diagram showing how the SHA circuitshould work on the output of the envelope detector.

We chose AD783 as our unity gain SHA device witha typical acquisition time of 250 ns. A photo of thechip is displayed in FIG. 17. The chip has an internalhold capacitor, and retains the held value with a drooprate of 0.02 µV/ µs. Its aperture jitter is said to be50 ps maximum, making it excellent for us to triggeraccurately.

FIG. 17. A photo of AD783 chip.

FIG. 18. Connection diagram for the AD783 chip.

The connection diagram for the chip is displayed inFIG. 18. With that, we soldered four chips (for all fourchannels) to a breadboard as displayed in FIG. 19 and20. A positive 5V dc power supply is connected to VCC ,a negative 5V dc power supply is connected to VEE . TheIN pin takes the input from the envelope detector, andthe OUT pin is connected to the ADC module mountedon the Edison board.

FIG. 19. The front side of the 4-channel S/HA board.

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FIG. 20. The back side of the 4-channel S/HA board.

In terms of the SHA enable pulse, clearly one desiresan delay-adjustable, low-jitter digital pulse. At first,we attempted to use the Intel-Edison board to generatethe digital pulse. A picture of the Edison board, whichrequires a 12 V DC power supply, is shown in FIG.21. We programmed in the Arduino IDE software andcompiled it to the Windows port of the Edison board,i.e. the one closer to the power supply.

FIG. 21. A photo of the Intel-Edison board.

However, the problem with using a mini pc like theEdison board to generate a fast digital pulse is a longdelay time and a huge jitter in time. We performed abench test on the sample-and-hold module to determinewhat is the shortest possible signal width that thesystem can hold, with two function generators: oneproducing a 2 Hz 1-ms-long square pulse to emulate thetrigger signal from the control room, the other producinga width-adjustable sub-microsecond pulse with a knowndelay from the first one to emulate the BPM signalpulse after the envelope detector. The sample-and-holdfunctionality is achieved when the rising edge of theEdison digital pulse lies within the short signal pulse, i.e.the delay between the two function generators matcheswith the digital pulse from Edison. As it turned out,the sample-and-hold module is not able to stably holdany signal narrower than 2.5 µs, or any delayed byless than 80 µs from the trigger pulse. Both problemsare due to the shortcomings of the digital pulse fromEdison. In particular, the long delay time might amountto Edison tackling other tasks first; and the high jittermight be because Edison’s CPU sending an interruptsignal whenever a task arrives, which becomes especiallyproblematic when it samples fast.As a remedy, the fast digital pulse is instead generatedby a hardware chip, as will be introduced below in theDual One-shot Multivibrator section.

FIG. 22. A photo of the cold test setup.

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C. Dual One-shot Multivibrator

FIG. 23. A photo of the DM74LS221 chip.

FIG. 24. The connection diagram for the DM74LS221 chip.

FIG. 25. The function diagram for the DM74LS221 chip.

Our choice of the delayed digital pulse generator isa 16-lead highly stable dual non-retriggerable one-shotchip DM74LS221N, or one-shot for short. Its outputpulse width ranges from 30 ns to 70 s, suitable for ourusage of generating a 100 ms long digital pulse. Wesoldereded the chip to a breadboard as shown in FIGs.26 and 27 according to the connection diagram (FIG.24) and the function diagram (FIG. 25).

Pin General Customized1 A1 GND2 B1 Trigger IN3 CLR1 Vcc4 Q1 Q15 Q2 NC6 Cext2 R2-C2-Vcc7 Rext/Cext2 R2-Vcc8 GND GND9 A2 GND10 B2 Q111 CLR2 Vcc12 Q2 OUT13 Q1 NC14 Cext1 R1-C1-Vcc15 Rext/Cext1 R1-Vcc16 Vcc Vcc

TABLE I. Summary of pinout for our DM74LS221N chip.

The usage of each pin is summarized in TABLE I.A 5V dc power supply is used as both Vcc and digitalHIGH. By setting A1 to LOW, CLR1 to HIGH, and B1to the trigger IN, at the rising edge of the input, the firstRC circuit outputs a square pulse with an adjustablewidth as Q1 and an inverted pulse with an adjustablewidth as Q1. The length of the first output signal issimply controlled by the time constant of the first RCcircuit, resistor R1 and capacitor C1. Then, we feed thisQ1 output to pin 10, i.e. B2. By also setting A2 to LOW,CLR2 to HIGH, the second RC circuit outputs a squarepulse with an adjustable width as Q2 and an invertedpulse with an adjustable width as Q2. The length of thesecond output signal is simply controlled by the timeconstant of the second RC circuit, R2 and C2. Hence, inthe context of us producing a delayed digital signal, thefirst RC circuit determines its delay (with respect to thetrigger pulse), and the second RC circuit determines itswidth. More specifically, to aim for a 10 µs delay anda 100 ms long pulse, we fixed C1 to be 1.40 nF and C2to be 2.90 µF, and adjusted the resistances of two vari-able resistors to be about 10 kΩ for R1 and 50 kΩ for R2.

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FIG. 26. The front side of the one-shot board.

FIG. 27. The back side of the one-shot board.

Overall, according to our cold test, the one-shot chiptogether with the sample-and-hold circuit can stably holdany signal such that its width is greater than 70 ns, andit is delayed from the trigger pulse by more than 600 ns.Please refer to FIG. 28 for the lower limits, namely theshortest signal width and closest signal delay, for the SHAand one-shot system. The fast speed of the circuit per-mits its usage on elongating the 100 ns pulse outputtedfrom the envelope detector, supposedly. Moreover, nojitter above 1 ns was observed in the one-shot output.

One-shot characteristics Minimum MaximumOutput Delay 600 ns 17.5 µsOutput Width 1 ms ∞ (>450 ms)

TABLE II. A summary for SHA using the DM74LS221N chip.

FIG. 28. The lower limit in the signal pulse width that theSHA system can hold.

FIG. 29. A zoomed in view of the SHA circuit holding a 400ns pulse.

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FIG. 30. A zoomed out view of the SHA circuit holding a 400ns pulse.

FIGs. 29 and 30 display different views for holdinga 400 ns pulse, emulating the elongation of the BPMsignals from the envelope detector. While the emulationcan be exact in the timescale, their pulse shapes aredifferent, so a better cold test can be conducted. As acounterexample, FIG. 31 represents the scenario suchthat the SHA doesnt hold.

FIG. 31. A picture where the SHA circuit does not hold.

Previously, Edison was only able to generate a digitalpulse whose signal width is greater than 2.5 mus andsignal delay is greater than 85 mus. And its outputdelay has a significant jitter of about 5 us. Thus, wehave made an about 1000 fold improvement, thanks toreplacing a CPU device with a hardware piece.

V. CONCLUSION

Overall, we devised a method to integrate multiplecheap components to process the four original BPMpickup signals, which involves an envelope detector,a peak detection and digitization system, and Wi-Fisendout. The project conducted a beam test thatconfirms the linear relationship between the raw signalwith respect to the beam charge and beam position.As for the bench test on the envelope detector, itbehaves linearly with charge, but is not sensitive enoughto position. Currently, we are examining whether thesignal is inundated by noise, and striving to increase thesignal-to-noise ratio by a band-pass or a low-pass filter.The cheap peak detection system was separately builtand cold-tested. Given that the envelope detector workswell, i.e. stretching the original signal to above 400ns long while having its amplitude proportional to theraw signal, the following peak detection system shouldcooperate, because it can hold any signal longer than70 ns in a test with functional generators emulatingthe beam signals. Furthermore, in the cold test, theanalog output from the SHA chip is long enough forthe analog-to-digital converter. However, more beamtests and integrated tests need to be done on the peakdetector.In terms of the Wi-Fi sendout module, we have managedto use a router to connect a computer to the Edisonboard (also plugged into it) wirelessly. The next step isto send simple signals between the Edison board and aremote computer.

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[1] Peter Forck, Piotr Kowina, and Dmitry Liakin. BeamPosition Monitors. Gesellschaft fur SchwerionenforschungGSI, Darmstadt, Germany.

[2] H. Koziol. Beam Diagnostics for Accelerators. CERN,Geneva, Swizterland.

[3] Analog Devices. DC to 6 GHz Envelope and TruPwr RMSDetector. ADL5511 datasheet. Last revised Feb. 23, 2017.

[4] Analog Devices. Complete Very High Speed Sample-and-Hold Amplifier. AD783 datasheet. Last revised Feb. 23,2017.

[5] Texas Instruments. ADS79xx 12/10/8-Bit, 1 MSPS,16/12/8/4-Channel, Single-Ended, MicroPower, SerialInterface ADC. ADS7951 datasheet. Jun. 2008. RevisedJul. 2015.

[6] Fairchild Semiconductor. DM74LS221 Dual Non-Retriggerable One-Shot with Clear and ComplementaryOutputs. DM74LS221N datasheet. Aug. 1986. RevisedApr. 2000.

[7] Intel Edison. Intel Edison Kit for Arduino. HardwareGuide. Sep. 2014. Revision 002.

[8] Intel Edison. Intel-Edison Compute Module. HardwareGuide. Jan. 2015. Revision 004.

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Listing 1. Arduino code for Elongating a Digital Signal through Edison

/∗D i g i t a l 2 Hz , 25 ms input ( ac t as t r i g g e r )D i g i t a l 2 Hz , 100 ms output ( ac t as S/H input )

Read the 25 ms square p u l s e from f u n c t i o n genera tor to d i g i t a l inputPrint the v a l u e to c o n s o l e 0−1023 to the s e r i a l monitorWhen the p u l s e a r r i v e s , d e l a y f o r 0 .2 ms , then produce d i g i t a l output t h a t l a s t s f o r 100 msPrint d i g i t a l output to s e r i a l monitor too

The c i r c u i t :∗ Function genera tor connected to d i g i t a l I /O pin 0 and ground as input .∗ Scope connected to d i g i t a l pin 1 and gronnd as output .

c r e a t e d 21 Ju l . 2017∗/

int outPin = 3 ;int inPin = 2 ;int va l = 0 ; // v a r i a b l e to s t o r e the read v a l u e

void setup ( )

S e r i a l . begin (200000 ) ;pinMode ( outPin , OUTPUT) ; // s e t s the d i g i t a l pin 3 as outputpinMode ( inPin , INPUT) ; // s e t s the d i g i t a l pin 2 as input

void loop ( )i f ( d i g i t a lRead ( inPin ) == 1)

delayMicroseconds ( 2 0 0 ) ;d i g i t a l W r i t e ( outPin , LOW) ;de layMicroseconds (100000 ) ;d i g i t a l W r i t e ( outPin , HIGH) ;de layMicroseconds (500 00 ) ;

else

d i g i t a l W r i t e ( outPin , HIGH) ;

va l = d ig i t a lRead ( outPin ) ;S e r i a l . p r i n t ( va l ) ;

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Listing 2. UDP Wi-Fi Setup by Edison (credit to Jiahang Shao).

#include <SPI . h>#include <WiFi . h>#include <WiFiUdp . h>

// d e c l a r a t i o n sint inPin = 2 ;int va l = 0 ; // v a r i a b l e to s t o r e the read v a l u e

int s t a t u s = WL IDLE STATUS;char s s i d [ ] = ”Wiboard” ; // your network SSID (name)char pass [ ] = ” 123456789 ” ; // your network password ( use f o r WPA, or use as key f o r WEP)int keyIndex = 0 ; // your network key Index number ( needed only f o r WEP)

unsigned int LocalPort = 22222; // l o c a l por t to l i s t e n onunsigned int Port = 12344 ; // l o c a l por t to l i s t e n onIPAddress remoteIp (192 , 168 , 253 , 1 ) ;

char SendBuffer [ 1 5 ] ;unsigned long measuretime =0;int measuremax=0;int measuretemp=0;int count =0;int k temp=0;

WiFiUDP Udp ;

// se tupvoid setup ( )

S e r i a l . begin (200000 ) ;pinMode ( inPin , INPUT) ; // s e t s the d i g i t a l pin 7 as input// I n i t i a l i z e s e r i a l and wai t f o r por t to open :S e r i a l . begin (115200 ) ;// S e r i a l . beg in ( 9 6 0 0 ) ;while ( ! S e r i a l )

; // wai t f o r s e r i a l por t to connect .

pinMode (A0 , INPUT PULLUP) ;

// check f o r the presence o f the s h i e l d :i f (WiFi . s t a t u s ( ) == WL NO SHIELD)

S e r i a l . p r i n t l n ( ”WiFi s h i e l d not pre sent ” ) ;// don ’ t cont inue :while ( true ) ;

// at tempt to connect to Wifi network :while ( s t a t u s != WL CONNECTED)

S e r i a l . p r i n t ( ”Attempting to connect to SSID : ” ) ;S e r i a l . p r i n t l n ( s s i d ) ;// Connect to WPA/WPA2 network . Change t h i s l i n e i f us ing open or WEP network :s t a t u s = WiFi . begin ( s s id , pass ) ;

// wai t 10 seconds f o r connect ion :delay (10000 ) ;

S e r i a l . p r i n t l n ( ”Connected to w i f i ” ) ;p r in tWi f i S ta tu s ( ) ;

S e r i a l . p r i n t l n ( ”\ nStar t ing connect ion to s e r v e r . . . ” ) ;// i f you g e t a connect ion , r e p o r t back v i a s e r i a l :Udp . begin ( LocalPort ) ;

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void loop ( )va l = d ig i t a lRead ( inPin ) ;S e r i a l . p r i n t l n ( va l ) ;Udp . wr i t e ( va l ) ;

void pr in tWi f i S ta tu s ( ) // p r i n t the SSID of the network you ’ re a t t a c h e d to :S e r i a l . p r i n t ( ”SSID : ” ) ;S e r i a l . p r i n t l n ( WiFi . SSID ( ) ) ;

// p r i n t your WiFi s h i e l d ’ s IP address :IPAddress ip = WiFi . l o c a l I P ( ) ;S e r i a l . p r i n t ( ”IP Address : ” ) ;S e r i a l . p r i n t l n ( ip ) ;

// p r i n t the r e c e i v e d s i g n a l s t r e n g t h :long r s s i = WiFi . RSSI ( ) ;S e r i a l . p r i n t ( ” s i g n a l s t r ength ( RSSI ) : ” ) ;S e r i a l . p r i n t ( r s s i ) ;S e r i a l . p r i n t l n ( ” dBm” ) ;