Dev Sys Ref Guide

8/8/2019 Dev Sys Ref Guide

1/535

Development System Reference Guide ISE 4 Printed in U.S.A .

Development Syst em

Reference Guide


2/535

Development System Reference Guide

ii Xilinx Development System

The Xilinx logo shown above is a registered trademark of Xilinx, Inc.

CoolRunner, RocketChips, RocketIP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XILINX, XC2064,XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc.

The shadow X shown above is a trademark of Xilinx, Inc.

ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, ConfigurableLogic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap,Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA,LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze,PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, Rocket I/O, Select I/O, SelectRAM, SelectRAM+, Silicon

Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap,UIM, VectorMaze, VersaBlock, VersaRing, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL,XACTstep Advanced, XACTstep Foundry, XACT-Floorplanner, XACT-Performance, XAM, XAPP, X-BLOX +,XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP, all XC designatedproducts, and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company is a service mark of Xilinx,Inc.

All other trademarks are the property of their respective owners.

Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shownherein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others.Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design andto supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry describedherein other than circuitry entirely embodied in its products. Xilinx, Inc. devices and products are protected underone or more of the following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155;

4,758,985; 4,820,937; 4,821,233; 4,835,418; 4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135;5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238;5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181;5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,355,035;5,357,153; 5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,397,943; 5,399,924;5,399,925; 5,406,133; 5,410,189; 5,410,194; 5,414,377; 5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719;5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,455,525; 5,466,117; 5,469,003; 5,475,253; 5,477,414;5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196; 5,497,108;5,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; 5,504,439; 5,504,440; 5,506,518;5,506,523; 5,506,878; 5,513,124; 5,517,135; 5,521,835; 5,521,837; 5,523,963; 5,523,971; 5,524,097; 5,526,322;5,528,169; 5,528,176; 5,530,378; 5,530,384; 5,546,018; 5,550,839; 5,550,843; 5,552,722; 5,553,001; 5,559,751;5,561,367; 5,561,629; 5,561,631; 5,563,527; 5,563,528; 5,563,529; 5,563,827; 5,565,792; 5,566,123; 5,570,051;5,570,059; 5,574,634; 5,574,655; 5,578,946; 5,581,198; 5,581,199; 5,581,738; 5,583,450; 5,583,452; 5,592,105;5,594,367; 5,598,424; 5,600,263; 5,600,264; 5,600,271; 5,600,597; 5,608,342; 5,610,536; 5,610,790; 5,610,829;

5,612,633; 5,614,844; 5,617,021; 5,617,041; 5,617,327; 5,617,573; 5,623,387; 5,627,480; 5,629,637; 5,629,886;5,631,577; 5,631,583; 5,635,851; 5,636,368; 5,640,106; 5,642,058; 5,646,545; 5,646,547; 5,646,564; 5,646,903;5,648,732; 5,648,913; 5,650,672; 5,650,946; 5,652,904; 5,654,631; 5,654,665; 5,656,950; 5,657,290; 5,659,484;5,661,660; 5,661,685; 5,668,495; 5,670,896; 5,670,897; 5,672,966; 5,673,198; 5,675,262; 5,675,270; 5,675,589;5,677,638; 5,682,107; 5,684,413; 5,689,133; 5,689,516; 5,691,907; 5,691,912; 5,694,047; 5,694,055; 5,694,056;5,694,399; 5,696,454; 5,701,091; 5,701,441; 5,703,759; 5,705,932; 5,705,938; 5,708,597; 5,712,579; 5,714,890;5,715,197; 5,717,340; 5,719,506; 5,719,507; 5,724,276; 5,726,484; 5,726,584; 5,734,866; 5,734,868; 5,737,234;5,737,235; 5,737,631; 5,742,178; 5,742,179; 5,742,531; 5,744,974; 5,744,979; 5,744,981; 5,744,995; 5,748,942;

R


3/535

Development System Reference Guide iii

5,748,979; 5,752,006; 5,752,035; 5,754,459; 5,758,192; 5,760,603; 5,760,604; 5,760,607; 5,761,483; 5,764,076;5,764,534; 5,764,564; 5,768,179; 5,770,951; 5,773,993; 5,778,439; 5,781,756; 5,784,313; 5,784,577; 5,786,240;5,787,007; 5,789,938; 5,790,479; 5,790,882; 5,795,068; 5,796,269; 5,798,656; 5,801,546; 5,801,547; 5,801,548;5,808,479; 5,811,985; 5,815,004; 5,815,016; 5,815,404; 5,815,405; 5,818,255; 5,818,730; 5,821,772; 5,821,774;5,825,202; 5,825,662; 5,825,787; 5,828,230; 5,828,231; 5,828,236; 5,828,608; 5,831,448; 5,831,460; 5,831,845;5,831,907; 5,835,402; 5,838,167; 5,838,901; 5,838,954; 5,841,296; 5,841,867; 5,844,422; 5,844,424; 5,844,829;

5,844,844; 5,847,577; 5,847,579; 5,847,580; 5,847,993; 5,852,323; 5,861,761; 5,862,082; 5,867,396; 5,870,309;5,870,327; 5,870,586; 5,874,834; 5,875,111; 5,877,632; 5,877,979; 5,880,492; 5,880,598; 5,880,620; 5,883,525;5,883,852; 5,886,538; 5,889,411; 5,889,412; 5,889,413; 5,889,701; 5,892,681; 5,892,961; 5,894,420; 5,896,047;5,896,329; 5,898,319; 5,898,320; 5,898,602; 5,898,618; 5,898,893; 5,907,245; 5,907,248; 5,909,125; 5,909,453;5,910,732; 5,912,937; 5,914,514; 5,914,616; 5,920,201; 5,920,202; 5,920,223; 5,923,185; 5,923,602; 5,923,614;5,928,338; 5,931,962; 5,933,023; 5,933,025; 5,933,369; 5,936,415; 5,936,424; 5,939,930; 5,940,606; 5,942,913;5,944,813; 5,945,837; 5,946,478; 5,949,690; 5,949,712; 5,949,983; 5,949,987; 5,952,839; 5,952,846; 5,955,888;5,956,748; 5,958,026; 5,959,821; 5,959,881; 5,959,885; 5,961,576; 5,962,881; 5,963,048; 5,963,050; 5,969,539;5,969,543; 5,970,142; 5,970,372; 5,971,595; 5,973,506; 5,978,260; 5,986,958; 5,990,704; 5,991,523; 5,991,788;5,991,880; 5,991,908; 5,995,419; 5,995,744; 5,995,988; 5,999,014; 5,999,025; 6,002,268; 6,002,282; 6,002,991;6,005,423; 6,005,829; 6,008,666; 6,011,407; 6,011,740; 6,016,063; 6,018,250; 6,018,624; 6,020,633; 6,020,756;6,020,757; 6,020,776; 6,021,423; 6,023,564; 6,023,565; 6,025,736; 6,026,481; 6,028,445; 6,028,450; 6,033,938;6,034,542; 6,034,548; 6,034,557; 6,035,106; 6,037,800; 6,038,386; 6,041,340; 6,043,692; 6,044,012; 6,044,025;6,046,603; 6,047,115; 6,049,222; 6,049,227; 6,051,992; 6,054,871; 6,055,205; 6,057,589; 6,057,704; 6,057,708;

6,061,417; 6,061,418; 6,067,508; 6,069,488; 6,069,489; 6,069,490; 6,069,849; 6,070,260; 6,071,314; 6,072,348;6,073,154; 6,074,432; 6,075,418; 6,078,201; 6,078,209; 6,078,528; 6,078,735; 6,078,736; 6,081,914; 6,084,429;6,086,629; 6,086,631; 6,091,262; 6,091,263; 6,091,892; 6,094,063; 6,094,065; 6,094,385; 6,097,210; 6,097,238;6,099,583; 6,100,705; 6,101,132; 6,101,143; 6,104,211; 6,105,105; 6,107,821; 6,107,826; 6,107,827; 6,112,322;6,114,843; 6,118,286; 6,118,298; 6,118,300; 6,118,324; 6,118,869; 6,118,938; 6,120,549; 6,120,551; 6,121,795;6,124,724; 6,124,731; 6,130,550; 6,133,751; 6,134,191; 6,134,517; 6,137,307; 6,137,714; 6,144,220; 6,144,225;6,144,262; 6,144,933; 6,150,838; 6,150,839; 6,150,863; 6,154,048; 6,154,049; 6,154,052; 6,154,053; 6,157,209;6,157,211; 6,157,213; 6,160,418; 6,160,431; 6,163,167; 6,167,001; 6,167,416; 6,167,545; 6,167,558; 6,167,560;6,172,518; 6,172,519; 6,172,520; 6,173,241; 6,175,246; 6,175,530; 6,177,819; 6,177,830; 6,181,158; 6,181,164;6,184,708; 6,184,709; 6,184,712; 6,185,724; 6,188,091; 6,191,610; 6,191,613; 6,191,614; 6,192,436; 6,195,774;6,199,192; 6,201,406; 6,201,410; 6,201,411; and 6,202,106; Re. 34,363, Re. 34,444, and Re. 34,808. Other U.S.and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein arefree from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct anyerrors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not

assume any liability for the accuracy or correctness of any engineering or software support or assistance providedto a user.

Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product insuch applications without the written consent of the appropriate Xilinx officer is prohibited.

Copyright 1991-2001 Xilinx, Inc. All Rights Reserved.


4/535


iv Xilinx Development System


5/535

Development System Reference Guide v

About This Manual

The Development System Reference Guide contains information about

the command line software programs in the Xilinx Developm ent

System. Most chapters are organized as follows:

A brief summary of program functions

A syntax statement

A description of the inpu t files used and the ou tpu t files

generated by th e program

A listing of the command s, options, or parameters used by the

program

Examples of how you can u se the program

For an overv iew of the Xilinx Developm ent System describing how

these programs are u sed in the d esign flow, see the Design Flow

chapter.


6/535


vi Xilinx Development System

Manual Contents

TheDevelopment System Reference Guide provides detailed information

about converting, imp lementing, and verifying d esigns w ith the

Xilinx command line tools. Check the program chapters forinformation on w hat p rogram works with each family of Field

Programmable Gate Array (FPGA) or Complex Programm able Logic

Device (CPLD). Following is a brief overview of the contents and

organization of theDevelopment System Reference Guide:

Note For information on timing constraints, UCF files, and PCF files,see the Constraints Guide.

Chapter 1, IntroductionThis chap ter d escribes some basics

that a re common to the d ifferent Xilinx Development System

modules.

Chapter 2, Design FlowThis chap ter d escribes the basic

design processes: design entry, synthesis, implemen tation, and

verification.

Chapter 3, Modular DesignThis chapter provides an

overview of Modu lar Design and describes how to run the

Modular Design flow.

Chapter 4, PARTGenPARTGen allow s you to obtain

information abou t installed d evices and families.

Chapter 5, NGDBuildNGDBuild p erforms all of the stepsnecessary to read a netlist file in XNF or EDIF format an d create

an NGD (Native Generic Database) file describing the logical

design redu ced to Xilinx primitives.

Chapter 6, Logical Design Rule CheckThe logical Design

Rule Check (DRC) comp rises a series of tests run to ver ify the

logical design d escribed by th e Native Generic Database (NGD)

file.

Chapter 7, MAPMAP maps the logic defined by an N GD file

into FPGA elemen ts such as CLBs, IOBs, and TBUFs.

Chapter 8, Physical Design Rule CheckThe physical Design

Rule Check (DRC) comp rises a series of tests run to d iscover

physical errors in your d esign.

Chapter 9, PARPAR places and rou tes FPGA designs.


7/535

About This Manual

Development System Reference Guide vii

Chap ter 10, PIN2UCFPIN2UCF generates pin-locking

constraints in a UCF file by reading a a p laced NCD file for

FPGAs or GYD file for CPLDs.

Chapter 11, TRACETiming Reporter and Circuit Evaluator

(TRACE) performs static timing analysis of the physical designbased on input timing constraints.

Chap ter 12, Speedprint Speed pr int lists block d elays for a

specified dev ice and its speed grades.

Chap ter 13, BitGenBitGen creates a configuration bitstream

for an FPGA design.

Chap ter 14, PROMGenPROMGen converts a configuration

bitstream (BIT) file into a file that can be d ownloaded to a PROM.

PROMGen also combines multiple BIT files for u se in a daisy

chain of FPGA d evices.

Chap ter 15, IBISWriterIBISWriter creates a list of pins u sed

by the d esign, the signals inside the d evice that connect those

pins, and the IBIS buffer m odel that ap plies to the IOB connected

to the pins.

Chap ter 16, NGDAnnoNGDAnno annotates timing

information found in th e physical NCD design file back to the

logical NGD file.

Chap ter 17, NGD2EDIFNGD2EDIF converts an NGD file to

an EDIF file for use in simu lation.

Chap ter 18, NGD2VERNGD2VER conver ts an N GD file to a

Verilog HDL file for u se in simu lation.

Chap ter 19, NGD2VHDLNGD2VHDL converts an N GD file

to a VHDL file for u se in simu lation.

Chap ter 20, XFLOWXFLOW au tomates the run ning of Xilinx

implementation and simu lation flows.


8/535


viii Xilinx Development System

App endix A, Xilinx Developm ent System FilesThis append ix

gives an alphabetic listing of the files used by th e Xilinx

Development System.

App end ix B, EDIF2NGD, XNF2NGD, and NGDBuildThis

appendix describes the netlist readers (EDIF2NGD andXNF2NGD) and how they interact with NGDBuild.

Additional Resources

For add itional information, go to http:/ / support.xilinx.com. The

following table lists some of the resources you can access from this

Web site. You can also d irectly access these resources using the

provided URLs.

Resource Description/URLTutorials Tutorials covering Xilinx design flows, from design entry to verification

and d ebugging

http:/ / support.xilinx.com/ support/ techsup/ tutorials/ index.htm

Answers

Database

Current listing of solution records for the Xilinx software tools

Search this database u sing the search function at

http:/ / support.xilinx.com/ support/ searchtd.htm

Application

Notes

Descriptions of device-specific design techniques and app roaches

http:/ / support.xilinx.com/ apps/ appsweb.htm

Data Book Pages from The Programmable Logic Data Book, which contains d evice-specific inform ation on Xilinx device characteristics, includ ing read back,

bound ary scan, configuration, length count, and debugging

http:/ / supp ort.xilinx.com/ partinfo/ databook.htm

Xcell Journals Quarterly journals for Xilinx programmable logic users

http:/ / support.xilinx.com/ xcell/ xcell.htm

Technical Tips Latest news, design tips, and patch information for the Xilinx design

environment

http:/ / support.xilinx.com/ support/ techsup/ journals/ index.htm
http://support.xilinx.com/http://support.xilinx.com/support/techsup/tutorials/index.htmhttp://support.xilinx.com/support/searchtd.htmhttp://support.xilinx.com/apps/appsweb.htmhttp://support.xilinx.com/partinfo/databook.htmhttp://support.xilinx.com/xcell/xcell.htmhttp://support.xilinx.com/support/techsup/journals/index.htmhttp://support.xilinx.com/support/techsup/journals/index.htmhttp://support.xilinx.com/xcell/xcell.htmhttp://support.xilinx.com/partinfo/databook.htmhttp://support.xilinx.com/apps/appsweb.htmhttp://support.xilinx.com/support/searchtd.htmhttp://support.xilinx.com/support/techsup/tutorials/index.htmhttp://support.xilinx.com/


9/535

Development System Reference Guide ix

Conventions

This manu al uses the following conventions. An examp le illustrates

most conventions.

Typographical

The following conventions are used for all docum ents.

Courier font ind icates messages, prom pts, and program files

that the system d isplays.

speed grade: - 100

Courier bold ind icates literal command s that you enter in a

syntactical statement. How ever, braces { } in Courier bold are

not literal and square brackets [ ] in Cour ier bold are literalonly in the case of bus sp ecifications, such as bu s [7:0].

rpt_del_net=

Courier bold also ind icates comm and s that you select from a

menu.

File Open

Italic fontden otes the following items.

Variables in a syntax statement for which you m ust supp ly

values

edif2ngddesign_name

References to other manu als

See theDevelopment System Reference Guide for more

information.


10/535


x Xilinx Development System

Emph asis in text

If a wire is draw n so that it overlaps the pin of a symbol, the

two nets are notconnected.

Square brackets [ ] indicate an optional entry or param eter.However, in bus specifications, such as bu s [7:0], they are

required.

edif2ngd [option_name] design_name

Braces { } enclose a list of items from w hich you m ust choose

one or more.

lowpwr ={on|off}

A vertical bar | separates items in a list of choices.

lowpwr ={on|off}

A vertical ellipsis ind icates repetitive material that has been

omitted.

IOB #1: Name = QOUT

IOB #2: Name = CLKIN

.

.

.

A horizontal ellipsis indicates that an item can be repeated

one or m ore times.

allow block block_name loc1 loc2 locn;

Online Document

The following conventions are used for online documents.

Blue text ind icates cross-references w ithin a book. Red text

ind icates cross-references to other books. Click the colored text to

jump to the sp ecified cross-reference.

Blue, underlined text ind icates a Web site. Click the link to op en

the specified Web site. You mu st have a Web browser and internet

connection to use th is feature.


11/535

Development System Reference Guide xi

Contents

About This Manual

Manual Contents ...........................................................................viAdditional Resources ....................................................................viii

ConventionsTypographical ................................................................................ixOnline Document ..........................................................................x

Chapter 1 Introduction

Command Line Program Overview ...............................................1-1Command Line Syntax ..................................................................1-2Command Line Options ................................................................1-3

f (Execute Commands File) ...................................................1-3p (Part Number) .....................................................................1-4h (Help) ..................................................................................1-7

Invoking Command Line Programs ...............................................1-8

Reading NCD Files with NCDRead ...............................................1-8

Chapter 2 Design Flow

Design Flow Overview ..................................................................2-2Design Entry and Synthesis ..........................................................2-5

Hierarchical Design ..................................................................2-6Schematic Entry Overview .......................................................2-7

Library Elements .................................................................2-7CORE Generator Tool (FPGAs Only) .................................2-8LogiBLOX Tool ...................................................................2-8

HDL Entry and Synthesis .........................................................2-9Functional Simulation ...............................................................2-9

Constraints ...............................................................................2-10Mapping Constraints (FPGAs Only) ...................................2-10Block Placement .................................................................2-10Timing Specifications ..........................................................2-10

Netlist Translation Programs ....................................................2-10Design Implementation .................................................................2-11

Mapping (FPGAs Only) ............................................................2-14


12/535


xii Xilinx Development System

Placing and Routing (FPGAs Only) .........................................2-14Bitstream Generation (FPGAs Only) ........................................2-14

Design Verification ........................................................................2-15Simulation ................................................................................2-17

Back-Annotation .................................................................2-18

Schematic-Based Simulation ..............................................2-21HDL-Based Simulation .......................................................2-23

Static Timing Analysis (FPGAs Only) ......................................2-26In-Circuit Verification ................................................................2-27

Design Rule Checker (FPGAs Only) ..................................2-27Xilinx Design Download Cables ..........................................2-27

FPGA Design Tips ........................................................................2-28Design Size and Performance .................................................2-28Global Clock Distribution ..........................................................2-29Data Feedback and Clock Enable ...........................................2-30Counters ..................................................................................2-32Other Synchronous Design Considerations .............................2-33

Chapter 3 Modular DesignModular Design Overview .............................................................3-1Modular Design Entry and Synthesis ............................................3-4Modular Design Implementation ...................................................3-5

Initial Budgeting Phase ............................................................3-5Active Module Implementation Phase ......................................3-9Final Assembly Phase .............................................................3-10

Setting Up Modular Design Directories .........................................3-12Running the Standard Modular Design Flow ................................3-13

Entering the Design .................................................................3-13General Coding Guidelines .................................................3-13Top-Level Design Coding Guidelines .................................3-13Module Coding Guidelines ..................................................3-15

Synthesizing your Designs .......................................................3-16Running Initial Budgeting .........................................................3-17Implementing an Active Module ...............................................3-19Assembling the Modules ..........................................................3-23Simulating an Active Module ....................................................3-24

Running Simulation with Top-Level Designas Context ...........................................................................3-25Running Independent Module Simulation ...........................3-26

Running the Sequential Modular Design Flow ..............................3-26Running the Partial Design Assembly Flow .............................3-26Running the Incremental Guide Flow .......................................3-29

Modular Design Tips .....................................................................3-34Constraints ...............................................................................3-34Design Size and Performance .................................................3-36PCI Logic .................................................................................3-37MAP Report .............................................................................3-37PAR Reports ............................................................................3-37XFLOW Automation of Modular Design ...................................3-38


13/535

Contents

Development System Reference Guide xiii

Modular Design Troubleshooting ..................................................3-39Multiple Output Ports MAP Error ..............................................3-39Part Type Specification ............................................................3-41Constraints Not Working in Active ModuleImplementation ........................................................................3-42

Resource Contention or Timing Constraints NotMet in Final Assembly ..............................................................3-42Windows 98 Command Line Limitation ....................................3-43

Vendor Specific Notes for Synthesis .............................................3-43Synplify or FPGA Express/FPGA Compiler II,version 3.3.1 or earlier .............................................................3-43

Creating a Netlist for Each Module (Synplify or FPGAExpress/FPGA Compiler II, version 3.3.1 or earlier) ...........3-43Disabling I/O Insertion for a Module (Synplify or FPGAExpress/FPGA Compiler II, version 3.3.1 or earlier) ...........3-43Instantiating Primitives (Synplify or FPGA Express/FPGACompiler II, version 3.3.1 or earlier) ...................................3-44

FPGA Express/FPGA Compiler II, version 3.4 or later ............3-44Creating a Netlist for Each Module (FPGA Express/FPGACompiler II, version 3.4 or later) .........................................3-44Disabling I/O Insertion for a Module (FPGA Express/FPGACompiler II, version 3.4 or later) .........................................3-44Instantiating Primitives (FPGA Express/FPGACompiler II, version 3.4 or later) .........................................3-45

LeonardoSpectrum ..................................................................3-45Creating a Netlist for Each Module(LeonardoSpectrum) ...........................................................3-45Disabling I/O Insertion for a Module(LeonardoSpectrum) ...........................................................3-46Instantiating Primitives (LeonardoSpectrum) ......................3-46

XST ..........................................................................................3-47Creating a Netlist for Each Module (XST) ...........................3-47Disabling I/O Insertion for a Module (XST) .........................3-47Instantiating Primitives (XST) .............................................3-47

HDL Code Examples .....................................................................3-48Top-Level Design .....................................................................3-48

VHDL Example: Top-Level Design .....................................3-48Verilog Example: Top-Level Design ...................................3-52

External I/Os in a Module .........................................................3-55VHDL Example: Module Design with Inserted I/Os ............3-55Verilog Example: Module Design with Inserted I/Os ...........3-56

Chapter 4 PARTGen

PARTGen Overview ......................................................................4-1PARTGen Syntax ..........................................................................4-2PARTGen Input Files ....................................................................4-2PARTGen Output Files .................................................................4-2PARTGen Options ........................................................................4-2

arch (Print Information for Specified architecture) .................4-2


14/535


xiv Xilinx Development System

i (Print a List of Devices, Packages, and Speeds) .................4-4p (Creates Package file and Partlist.xct File) .........................4-4v (Creates Packages and Partlist.xct File) .............................4-6

Partlist.xct File ...............................................................................4-7Header .....................................................................................4-7

Device Attributes ......................................................................4-8PKG File ........................................................................................4-10

Chapter 5 NGDBuild

NGDBuild Overview ......................................................................5-1Converting a Netlist to an NGD File .........................................5-3

NGDBuild Syntax ..........................................................................5-3NGDBuild Input Files .....................................................................5-4NGDBuild Output Files ..................................................................5-7NGDBuild Intermediate Files .........................................................5-8NGDBuild Options .........................................................................5-8

a (Add PADs to Top-Level Port Signals) ................................5-8

aul (Allow Unmatched LOCs) .................................................5-9dd (Destination Directory) ......................................................5-9f (Execute Commands File) ...................................................5-9i (Ignore UCF File) .................................................................5-10l (Libraries to Search) .............................................................5-10modular assemble (Module Assembly) ..................................5-10modular initial (Initial Budgeting of Modular Design) ..............5-11modular module (Active Module Implementation) ..................5-12nt (Netlist Translation Type) ...................................................5-12p (Part Number) .....................................................................5-13quiet (Report Warnings and Errors Only) ...............................5-13r (Ignore LOC Constraints) .....................................................5-14sd (Search Specified Directory) .............................................5-14u (Allow Unexpanded Blocks) ................................................5-14uc (User Constraints File) ......................................................5-15ur (Read User Rules File) ......................................................5-15verbose (Report All Messages) ..............................................5-16

Chapter 6 Logical Design Rule Check

Logical DRC Overview ..................................................................6-1Logical DRC Checks .....................................................................6-2

Block Check .............................................................................6-2Net Check ................................................................................6-2Pad Check ...............................................................................6-3Clock Buffer Check ..................................................................6-4Name Check ............................................................................6-5Primitive Pin Check ..................................................................6-5

Chapter 7 MAP

MAP Overview ..............................................................................7-1MAP Syntax ..................................................................................7-2


15/535

Contents

Development System Reference Guide xv

MAP Input Files .............................................................................7-3MAP Output Files ..........................................................................7-4MAP Options .................................................................................7-5

b (Convert Clock Buffers) .......................................................7-6bp (Map Slice Logic) ..............................................................7-7

c (Pack CLBs) ........................................................................7-7cm (Cover Mode) ...................................................................7-8detail (Write Out Detailed MAP Report) .................................7-9f (Execute Commands File) ...................................................7-9fp (Floorplanner) ....................................................................7-9gf (Guide NCD File) ...............................................................7-9gm (Guide Mode) ...................................................................7-9ir (Do Not Use RLOCs to Generate RPMs) ...........................7-10k (Map to Input Functions) .....................................................7-10l (No logic replication) ............................................................7-11o (Output File Name) .............................................................7-12oe (Logic Optimization Effort) ................................................7-12os (Logic Optimization Style) .................................................7-13p (Part Number) .....................................................................7-14pr (Pack Registers in I/O) .......................................................7-14quiet (Report Warnings and Errors Only) ...............................7-15r (No Register Ordering) ........................................................7-15timing (Timing-Driven Packing) ..............................................7-15tx (Transform Buses) .............................................................7-15u (Do Not Remove Unused Logic) .........................................7-16

MAP Process ................................................................................7-17Register Ordering ..........................................................................7-19Guided Mapping ............................................................................7-21Simulating Map Results ................................................................7-23MAP Report (MRP) File ................................................................7-25

Halting MAP ..................................................................................7-31Chapter 8 Physical Design Rule Check

DRC Overview ..............................................................................8-1DRC Syntax ..................................................................................8-2DRC Input File ...............................................................................8-2DRC Output File ............................................................................8-2DRC Options .................................................................................8-2

e (Error Report) ......................................................................8-2f (Execute Commands File) ...................................................8-3o (Output file) .........................................................................8-3s (Summary Report) ...............................................................8-3

v (Verbose Report) .................................................................8-3z (Report Incomplete Programming) ......................................8-3DRC Checks .................................................................................8-4DRC Errors and Warnings ............................................................8-4


16/535


xvi Xilinx Development System

Chapter 9 PAR

PAR Overview ...............................................................................9-2PAR Syntax ...................................................................................9-3PAR Input Files .............................................................................9-4

PAR Output Files ..........................................................................9-4PAR Options .................................................................................9-5c (Number of Cost-Based Router Cleanup Passes) ..............9-6d (Number of Delay-Based Router Cleanup Passes) ............9-7detail (Write Out Detailed PAR Report) .................................9-7dfs (Thorough Timing Analysis of Paths) ...............................9-8e (Delay-based Cleanup PassesCompletelyRouted Designs) ......................................................................9-8

f (Execute Commands File) ...................................................9-8gf (Guide NCD File) ...............................................................9-8gm (Guide Mode) ...................................................................9-9guide (Guide File) ..................................................................9-9i (Number of Router Iterations) ..............................................9-9k (Re-Entrant Routing) ...........................................................9-10kpaths (Faster Analysis of Paths) ..........................................9-10l (Overall Effort Level) ............................................................9-12m (Multi-Tasking Mode) .........................................................9-12n (Number of PAR Iterations) .................................................9-12ol (Overall Effort Level) ..........................................................9-12p (No Placement) ...................................................................9-13pl (Placer Effort Level) ...........................................................9-13r (No Routing) ........................................................................9-14rl (Router Effort Level) ............................................................9-14s (Number of Results to Save) ...............................................9-14t (Starting Placer Cost Table) .................................................9-14

ub (Use Bonded I/Os) ............................................................9-15w (Overwrite Existing Files) ...................................................9-15x (Ignore Timing Constraints) .................................................9-15xe (Extra Effort Level) ............................................................9-15

PAR Process .................................................................................9-16Placing .....................................................................................9-16Routing .....................................................................................9-16Timing-driven PAR ...................................................................9-17Automatic Timespecing ............................................................9-18Command Line Examples ........................................................9-19

Guided PAR ..................................................................................9-21Incremental Designs ................................................................9-21PCI Cores ................................................................................9-23

PAR Reports .................................................................................9-24Intermediate Failing Timespec Summary ................................9-28Place and Route (PAR) Report File .........................................9-28

Summary of Report .............................................................9-31Select I/O Utilization and Usage Summary .........................9-33

Delay (DLY) File .......................................................................9-33PAD File ...................................................................................9-34


17/535

Contents

Development System Reference Guide xvii

Guide Reporting .......................................................................9-35Turns Engine (PAR Multi-Tasking Option) ....................................9-35

Turns Engine Overview ............................................................9-35Turns Engine Syntax ................................................................9-36Turns Engine Input Files ..........................................................9-37

Turns Engine Output Files .......................................................9-38Homogeneous and Heterogeneous Networks .........................9-38Limitations ................................................................................9-38System Requirements ..............................................................9-39Turns Engine Environment Variables ......................................9-39Debugging ................................................................................9-41Screen Output ..........................................................................9-42

Halting PAR ...................................................................................9-45

Chapter 10 PIN2UCF

PIN2UCF Overview .......................................................................10-1PIN2UCF Syntax ...........................................................................10-4

PIN2UCF Input Files .....................................................................10-4PIN2UCF Output Files ..................................................................10-4PIN2UCF Options .........................................................................10-5

f (Execute Commands File) ...................................................10-5o (Output File Name) .............................................................10-5r (Write to a Report File) ........................................................10-5

PIN2UCF Scenarios ......................................................................10-6

Chapter 11 TRACE

TRACE Overview ..........................................................................11-1TRACE Syntax ..............................................................................11-2TRACE Input Files ........................................................................11-2

TRACE Output Files ......................................................................11-3TRACE Options .............................................................................11-4

a (Advanced Analysis) ...........................................................11-4e (Generate an Error Report) .................................................11-4f (Execute Commands File) ...................................................11-4l (Limit Timing Report) ............................................................11-5o (Output File Name) .............................................................11-5s (Change Speed) ..................................................................11-5skew (Analyze Clock Skew for All Clocks) .............................11-5stamp (Generates STAMP timing model files) .......................11-6tsi (Generate a Timespec Interaction Report) ........................11-6u (Report Uncovered Paths) ..................................................11-6v (Generate a Verbose Report) ..............................................11-7xml (XML Output File Name) .................................................11-8

TRACE Command Line Examples ................................................11-8TRACE Reports ............................................................................11-9

Timing Verification with TRACE ...............................................11-10Net Delay Constraints .........................................................11-10Net Skew Constraints .........................................................11-10Path Delay Constraints .......................................................11-11


18/535


xviii Xilinx Development System

Clock Skew and Setup Checking ........................................11-11Reporting with TRACE .............................................................11-14Data Sheet Reports .................................................................11-17Guaranteed Setup and Hold Reporting ....................................11-20

Setup Times ........................................................................11-21

Hold Times ..........................................................................11-21Summary Report ......................................................................11-21Summary Report (Without a Physical ConstraintsFile Specified) .....................................................................11-22Summary Report (With a Physical ConstraintsFile Specified) .....................................................................11-24

Error Report .............................................................................11-26Verbose Report ........................................................................11-29TSI Report ................................................................................11-34

Extracted Coverage TSI Report Example ...........................11-35Duplicate Coverage TSI Report Example ...........................11-39

Halting TRACE ..............................................................................11-43

Chapter 12 SpeedprintSpeedprint Overview .....................................................................12-1Speedprint Syntax .........................................................................12-2Speedprint Options .......................................................................12-2

min (Display Minimum Speed Data) ......................................12-2s (Speed Grade) ....................................................................12-2t (Specify Temperature) .........................................................12-3v (Specify Voltage) .................................................................12-3

Speedprint Example Commands ..................................................12-3Speedprint Example Reports ........................................................12-3

Chapter 13 BitGen

BitGen Overview ...........................................................................13-1BitGen Syntax ...............................................................................13-2BitGen Input Files ..........................................................................13-3BitGen Output Files .......................................................................13-4BitGen Options ..............................................................................13-5

a (Tie All Interconnect) ...........................................................13-5b (Create Rawbits File) ..........................................................13-5d (Do Not Run DRC) ..............................................................13-5f (Execute Commands File) ...................................................13-6g (Set Configuration) ..............................................................13-6g (Set ConfigurationXC4000 and Spartan/XL) ...................13-6

Cclk_Nosync .......................................................................13-7Cclk_Sync ...........................................................................13-7Uclk_Nosync .......................................................................13-8Uclk_Sync ...........................................................................13-8AddressLines ......................................................................13-9Binary ..................................................................................13-9BSCAN_Config ...................................................................13-9BSCAN_Status ...................................................................13-10


19/535

Contents

Development System Reference Guide xix

5V_Tolerant_IO ..................................................................13-10ConfigRate ..........................................................................13-10CRC ....................................................................................13-11DoneActive .........................................................................13-11DonePin ..............................................................................13-12

ExpressMode ......................................................................13-12GSRInactive ........................................................................13-12Input ....................................................................................13-14LC_Alignment .....................................................................13-14M0Pin ..................................................................................13-14M1 Pin .................................................................................13-15M2Pin ..................................................................................13-15Output .................................................................................13-15OutputsActive .....................................................................13-15PowerDown ........................................................................13-17ReadAbort ...........................................................................13-17ReadCapture ......................................................................13-17ReadClk ..............................................................................13-17StartupClk ...........................................................................13-18SyncToDone .......................................................................13-18TdoPin ................................................................................13-18

g (Set ConfigurationVirtex/-E/-II/-II PRO andSpartan-II/-IIE Devices) ............................................................13-19

Binary ..................................................................................13-19CclkPin ................................................................................13-19Compress ...........................................................................13-19ConfigRate ..........................................................................13-20DCMShutdown ....................................................................13-20DebugBitstream ..................................................................13-20DisableBandgap .................................................................13-21

DONE_cycle .......................................................................13-21DonePin ..............................................................................13-21DonePipe ............................................................................13-21DriveDone ...........................................................................13-22Encrypt ................................................................................13-22Gclkdel0, Gclkdel1, Gclkdel2, Gclkdel3 ..............................13-22GSR_cycle ..........................................................................13-23GWE_cycle .........................................................................13-23GTS_cycle ..........................................................................13-23HswapenPin ........................................................................13-24Key0, Key1, Key2, Key3, Key4, Key5 .................................13-24KeyFile ................................................................................13-24Keyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4,

Keyseq5 ..............................................................................13-24LCK_cycle ...........................................................................13-25M0Pin ..................................................................................13-25M1Pin ..................................................................................13-25M2Pin ..................................................................................13-26Match_cycle ........................................................................13-26Persist .................................................................................13-26


20/535


xx Xilinx Development System

ProgPin ...............................................................................13-27ReadBack ...........................................................................13-27Security ...............................................................................13-27StartCBC .............................................................................13-27StartKey ..............................................................................13-28

StartupClk ...........................................................................13-28TckPin .................................................................................13-28TdiPin ..................................................................................13-29TdoPin ................................................................................13-29TmsPin ................................................................................13-29UnusedPin ..........................................................................13-30UserID .................................................................................13-30

j (No BIT File) .........................................................................13-30l (Create a Logic Allocation File) ............................................13-30m (Generate a Mask File) ......................................................13-31n (Save a Tied design) ...........................................................13-31t (Tie Unused Interconnect) ...................................................13-31u (Use Critical Nets Last) .......................................................13-33w (Overwrite Existing Output File) .........................................13-33

Chapter 14 PROMGen

PROMGen Overview .....................................................................14-1PROMGen Syntax .........................................................................14-3PROMGen Input Files ...................................................................14-3PROMGen Output Files ................................................................14-3PROMGen Options .......................................................................14-3

b (Disable Bit SwappingHEX Format Only) ........................14-3c (Checksum) .........................................................................14-4d (Load Downward) ................................................................14-4f (Execute Commands File) ...................................................14-4l (Disable Length Count) ........................................................14-4n (Add BIT FIles) ....................................................................14-5o (Output File Name) .............................................................14-5p (PROM Format) ..................................................................14-5r (Load PROM File) ................................................................14-6s (PROM Size) .......................................................................14-6u (Load Upward) ....................................................................14-6w (Overwrite Existing Output File) .........................................14-7x (Specify Xilinx PROM) .........................................................14-7

Bit Swapping in PROM Files .........................................................14-7PROMGen Examples ....................................................................14-8

Chapter 15 IBISWriterIBISWriter Overview ......................................................................15-1IBISWriter Syntax ..........................................................................15-3IBISWriter Input Files ....................................................................15-3IBISWriter Output Files .................................................................15-3IBISWriter Options ........................................................................15-3

g (Set Reference Voltage) .....................................................15-4


21/535

Contents

Development System Reference Guide xxi

Chapter 16 NGDAnno

NGDAnno Overview ......................................................................16-2NGDAnno Syntax ..........................................................................16-4NGDAnno Input Files ....................................................................16-4

NGDAnno Output Files .................................................................16-5NGDAnno Options ........................................................................16-6f (Execute Commands File) ...................................................16-6module (Simulation of Active Module) ...................................16-6o (Output File Name) .............................................................16-7p (PCF File) ............................................................................16-7quiet (Report Warnings and Errors Only) ...............................16-7report (Generate Hierarchy Loss Report) ..............................16-8s (Change Speed) ..................................................................16-8

Dedicated Global Signals in Back-Annotation Simulation .............16-9XC4000E/L/EX/XL/XLA and Spartan/XL ..................................16-9Virtex/-II/-E and Spartan-II .......................................................16-9

Hierarchy Changes in Annotated Designs ....................................16-10External Setup and Hold Check ....................................................16-11

Chapter 17 NGD2EDIF

NGD2EDIF Overview ....................................................................17-2NGD2EDIF Syntax ........................................................................17-3NGD2EDIF Input Files ..................................................................17-4NGD2EDIF Output Files ................................................................17-4NGD2EDIF Options .......................................................................17-4

a (Write All Properties) ...........................................................17-4b (Use Buffers to Model Delays) ............................................17-4c (Reference Design Name as SpecifiedMentor) ...............17-5f (Execute Commands File) ...................................................17-5hpn (Set HDL Pin Names) .....................................................17-5i (Annotate Timing Properties to Instances) ...........................17-5l (Local Scope) .......................................................................17-6n (Generate Flattened Netlist) ................................................17-6v (Vendor) ..............................................................................17-6vpt (Mentor Graphics Viewpoint) ............................................17-6w (Overwrite Output) ..............................................................17-7

XMM (RAM Initialization) File ........................................................17-7Generic File Format for XMM File ............................................17-7

Generic Initialization File Example ......................................17-8EDIF Identifier Naming Conventions .............................................17-9

Chapter 18 NGD2VERNGD2VER Overview .....................................................................18-2NGD2VER Syntax .........................................................................18-3NGD2VER Input Files ...................................................................18-4NGD2VER Output Files ................................................................18-4NGD2VER Options .......................................................................18-5

10ps (Set Time Precision to be 10ps) ....................................18-5


22/535


xxii Xilinx Development System

aka (Write Also-Known-As Names as Comments) ................18-5cd (Include `celldefine\`endcelldefine in Verilog File) .............18-5f (Execute Commands File) ...................................................18-6gp (Bring Out Global Reset Net as Port) ................................18-6ism (Include SimPrim Modules in Verilog File) ......................18-6

log (Rename the Log File) .....................................................18-7ne (No Name Escaping) .........................................................18-7op (Specify the Period for Oscillator) .....................................18-7pf (Generate Pin File) .............................................................18-7pms (Port Names Match Child Signal Names) ......................18-8r (Retain Hierarchy) ................................................................18-8sdf_path (Full Path to SDF File) .............................................18-8shm (Write $shm Statements in Test Fixture File) .................18-9tf (Generate Test Fixture File) ................................................18-9ti (Top Instance Name) ..........................................................18-9tm (Top Module Name) ..........................................................18-9tp (Bring Out Global 3-State Net as Port) ..............................18-9ul (Write uselib Directive) ......................................................18-10verbose (Report All Messages) ..............................................18-10w (Overwrite Existing Files) ...................................................18-10

Setting Global Set/Reset, 3-State, and PRLD ...............................18-10Test Fixture File ............................................................................18-11Bus Order in Verilog Files .............................................................18-11Verilog Identifier Naming Conventions ..........................................18-12Compile Scripts for Verilog Libraries .............................................18-12

Chapter 19 NGD2VHDL

NGD2VHDL Overview ...................................................................19-1NGD2VHDL Syntax .......................................................................19-3NGD2VHDL Input Files .................................................................19-4NGD2VHDL Output Files ..............................................................19-4NGD2VHDL Options .....................................................................19-5

a (Architecture Only) ..............................................................19-5aka (Write Also-Known-As Names as Comments) ................19-5ar (Rename Architecture Name) ............................................19-5f (Execute Commands File) ...................................................19-5gp (Bring Out Global Reset Net as Port) ................................19-5log (Specify the Log File) .......................................................19-6op (Specify the Period for Oscillator) .....................................19-6pf (Generate PIN File) ............................................................19-6pms (Port Names Match Child Signal Names) ......................19-6r (Retain Hierarchy) ................................................................19-7

rpw (Specify the Pulse Width for ROC) ..................................19-7tb (Generate Testbench File) .................................................19-7te (Top Entity Name) ..............................................................19-7ti (Top Instance Name) ..........................................................19-8tp (Bring Out Global 3-State Net as Port) ..............................19-8tpw (Specify the Pulse Width for TOC) ..................................19-8verbose (Report All Messages) ..............................................19-8


23/535

Contents

Development System Reference Guide xxiii

w (Overwrite Existing Files) ...................................................19-9xon (Select Output Behavior for Timing Violations) ...............19-9

VHDL Global Set/Reset Emulation ...............................................19-9VHDL Only STARTUP Block ...................................................19-10VHDL Only STARTBUF Cell ....................................................19-10

VHDL Only STARTUP_VIRTEX Block andSTARTBUF_VIRTEX Cell ........................................................19-11VHDL Only RESET-ON-CONFIGURATION (ROC) Cell .........19-11VHDL Only ROCBUF Cell ........................................................19-13VHDL Only 3-State-On-Configuration (TOC) Cell ....................19-13VHDL Only TOCBUF ...............................................................19-14VHDL Only Oscillators .............................................................19-15

Example 1: Oscillator VHDL ...............................................19-15Example 2: Oscillator Test Bench .......................................19-16

Bus Order in VHDL Files ...............................................................19-18VHDL Identifier Naming Conventions ...........................................19-19Compile Scripts for VHDL Libraries ..............................................19-19

Chapter 20 XFLOWXFLOW Overview .........................................................................20-2XFLOW Syntax .............................................................................20-4XFLOW Input Files ........................................................................20-5XFLOW Output Files .....................................................................20-6XFLOW Flow Types ......................................................................20-11

assemble (Module Assembly) ................................................20-12config (Create a BIT File for FPGAs) .....................................20-13fit (Fit a CPLD) .......................................................................20-13fsim (Create a File for Functional Simulation) ........................20-14implement (Implement an FPGA) ..........................................20-15initial (Initial Budgeting of Modular Design) ............................20-16module (Active Module Implementation) ................................20-17mppr (Multi-Pass Place and Route for FPGAs) .....................20-19synth (XST Synthesis) ...........................................................20-20tsim (Create a File for Timing Simulation) ..............................20-21Flow Files .................................................................................20-23

Flow File Format .................................................................20-25User Command Blocks .......................................................20-28

XFLOW Option Files .....................................................................20-28Option File Format ...................................................................20-29

XFLOW Options ............................................................................20-30ed (Copy Files to Export Directory) ........................................20-30f (Execute Commands File) ...................................................20-30

g (Specify a Global Variable) .................................................20-31log (Specify Log File) .............................................................20-31norun (Creates a Script File Only) .........................................20-31o (Change Output File Name) ................................................20-32p (Part Number) .....................................................................20-33rd (Copy Report Files) ............................................................20-33wd (Specify a Working Directory) ...........................................20-34


24/535


xxiv Xilinx Development System

Running XFLOW ...........................................................................20-35Using XFLOW Flow Types in Combination ..............................20-35Running Smart XFLOW .........................................................20-35Using the SCR or BAT File ......................................................20-36Using the XIL_XFLOW_PATH Environment Variable ..............20-36

Halting XFLOW .............................................................................20-37Appendix A Xilinx Development System Files

Appendix B EDIF2NGD, XNF2NGD, and NGDBuild

EDIF2NGD ....................................................................................B-1EDIF2NGD Syntax ...................................................................B-3EDIF2NGD Input Files .............................................................B-4EDIF2NGD Output Files ..........................................................B-4EDIF2NGD Options .................................................................B-4

a (Add PADs to Top-Level Port Signals) ..........................B-4aul (Allow Unmatched LOCs) ...........................................B-5

f (Execute Commands File) ..............................................B-5l (Libraries to Search) .......................................................B-5p (Part Number) ................................................................B-6quiet (Report Warnings and Errors Only) .........................B-6r (Ignore LOC Constraints) ...............................................B-6

XNF2NGD .....................................................................................B-7XNF2NGD Syntax ....................................................................B-9XNF2NGD Input Files ..............................................................B-9XNF2NGD Output Files ...........................................................B-10XNF2NGD Options ..................................................................B-10

f (Execute Commands File) ..............................................B-10l (Libraries to Search) .......................................................B-10p (Part Number) ................................................................B-11

r (Ignore LOC Constraints) ...............................................B-11u (Top-Level XNF Netlist) .................................................B-11

NGDBuild ......................................................................................B-12Converting a Netlist to an NGD File .........................................B-12Bus Matching ...........................................................................B-14

Netlister Launcher .........................................................................B-16Netlister Launcher Rules Files .................................................B-18User Rules File ........................................................................B-18

User Rules and System Rules ............................................B-18User Rules Format ..............................................................B-19Value Types in Key Statements ..........................................B-21

System Rules File ....................................................................B-22

Rules File Examples ................................................................B-25Example 1: EDF_RULE System Rule .................................B-25Example 2: User Rule .........................................................B-26Example 3: User Rule .........................................................B-26Example 4: User Rule .........................................................B-27

NGDBuild File Names and Locations ............................................B-27


25/535

Development System Reference Guide 1-1

Chapter 1

Introduction

This chap ter d escribes the basics of the d ifferent Xilinx Developm ent

System comm and line p rograms. The chapter contains the following

sections:

Command Line Program Overview

Command Line Syntax

Command Line Options

Invoking Comm and Line Programs

Reading N CD Files with NCDRead

Command Line Program Overview

Xilinx comm and line programs allow you to imp lement and verify

your design. The following table lists which programs you can usefor each step in the d esign flow. For d etailed information, see the

Design Flow chapter.

Table 1-1 Command Line Programs in the Design Flow

Design Flow Step Command LIne Program

Design Im plem entation N GDBu ild , MAP, PAR, BitGen

Timing Simulation

(Design Verification)

NGDAnno, NGD2EDIF,

NGD2VER, NGD2VHDL

Static Timing An alysis(Design Verification) TRACE

Back Annotation

(Design Verification)

NGDAnno, NGD2EDIF,

NGD2VER, NGD2VHDL


26/535


1-2 Xilinx Development System

Each p rogram h as mu ltiple options, which allow you to control how

a program is executed . For example, you can set options to change

outp ut file names, to set a part nu mber for your d esign, or to specify

certain files to read in wh en executing the program .

You can ru n these programs in the standard design flow or usespecial options to run the program s in a Modu lar Design flow, as

described in the Modu lar Design chapter.

Note The comm and line p rograms described in this manual underliemany of the Xilinx Graphical User Inter faces (GUIs). The GUIs can be

used in conjun ction with th e comm and line p rograms. For

information on the GUIs, see the online Help provid ed w ith each

tool.

Command Line SyntaxComman d line syntax always begins with the comm and line

program name. The program name is followed by any op tions and

then file names. Use the following ru les when specifying comm and

line op tions:

Enter options in any ord er.

Precede options with a hyphen () and separate them with

spaces. In som e cases, you can p recede op tions by a plu s sign (+).

Be consistent with u pp er and lower case.

When an option requires a parameter, separate the p arameter

from the op tion by spaces or tabs.

Correct: par -l 5

Incorrect: par-l5

When specifying op tions that can be specified m ultiple times,

precede the param eter with the option letter.

Correct: l xilinxun -l synopsys

Incorrect: l xilinxun synopsys

Enter param eters that are bound to a particular option afterthe

option.

Correct: fcommand_file

Incorrect: command_filef


27/535

Introduction


Use the following ru les when specifying file nam es:

Enter file names in th e order specified in the chapter that

describes the p rogram.

Correct: par input.ncd output.ncd freq.pcf Incorrect: par input.ncd freq.pcf output.ncd

Use lower case for all file extensions (for examp le, .ncd).

Command Line Options

The following op tions are comm on to man y of the command line

programs in the Xilinx Developm ent System.

f (Execute Commands File)For any Xilinx Development System p rogram, you can store

comm and line program options and file names in a comman d file.

You can then execute the argumen ts by entering the program n ame

with the f option followed by the name of the comm and file. This is

useful if you frequen tly execute the same argu men ts each time you

execute a program or if the command line command becomes too

long.

You can use the file in th e following w ays:

To supply all the command options and file names for theprogram, as in the following example:

par fcommand_file

command_file is the name of the file that contains the command

options and file nam es.

To insert certain command options and file names within the

comman d line, as in the following example:

par i 33 f placeoptions s 4 f routeoptions

design_i.ncd design_o.ncd

placeoptions is the nam e of a file containing placement

command parameters.

routeoptions is the name of a file containing rou ting command

parameters.


28/535



You create the comm and file in ASCII format. Use the following rules

wh en creating the comm and file:

Separate program options and file names with spaces.

Precede comments w ith the p ound sign (#). Put n ew lines or tabs anywhere white space is allowed on the

UNIX or DOS comm and line.

Put all arguments on the same line, one argument per line, or a

combination of these.

All carriage return s and o ther non -printable characters are

treated as sp aces and ignored.

No line length limitation exists within the file.

Following is an examp le of a command file.#command line options for par for design mine.ncd

-a -n 10

-w

-l 5

-s 2 #will save the two best results

/home/yourname/designs/xilinx/mine.ncd

#directory for output designs

/home/yourname/designs/xilinx/output.dir

#use timing constraints file

/home/yourname/designs/xilinx/mine.pcf

p (Part Number)

You can u se the p option with the EDIF2NGD, XNF2NGD,

NGDBuild , MAP, and XFLOW p rograms to specify the part into

wh ich you r design w ill be implemented . You can sp ecify a par t

number at the following d ifferent points in the design flow:

In the inpu t netlist (does not requ ire the p option)

In a N etlist Constra ints File (NCF) (does not require the p

option)

With th e p op tion when you ru n a netlist reader (EDIF2NGD or

XNF2NGD)

In a User Constraints File (UCF) (does not require the p option)


29/535

Introduction


With th e p op tion w hen you run NGDBuild

By the time you run NGDBuild , you must have already specified

a d evice architecture.

With th e p option when you run MAPWhen you ru n MAP, an architecture, device, and p ackage must

be specified, either on the MAP comm and line or earlier in the

design flow. If you do not sp ecify a sp eed, MAP selects a d efau lt

speed. You can only run MAP using a part nu mber from the

architecture you specified w hen you ran N GDBuild.

Note Part nu mbers sp ecified in a later step of the d esign flowoverride a p art nu mber sp ecified in an earlier step. For example, a

part sp ecified wh en you run MAP overrides a part sp ecified in the

input netlist.

A complete Xilinx part num ber consists of the following elements:

Architecture (for exam ple, xc4000ex)

Device (for example, xc4028ex)

Package (for examp le, pq208)

Speed (for example, -3)


30/535


31/535

Introduction


h (Help)

When you enter a program name followed by

help or h, a message d isplays that lists all the available options and

their par ameters as w ell as the legal file types for use w ith theprogram. The message also explains each of the options.

Following are descriptions for the symbols used in the help m essage:

Following are examples of syntax u sed for file nam es:

ind icates that the .ncd extension is optiona l but thatthe extension must be .ncd.

indicates that the .edn extension is optiona l and is

appended only if there is no other extension in the file name.

For architecture-specific program s, such as BitGen, you can enter the

following to get a verbose help message for the specified architecture:

program_nameh architecture_name

Note On the UNIX command line, you can red irect the help m essageto a file to read later or to p rint ou t by entering the following:

program_nameh >&filename

Symbol Description

[ ] Encloses items that are optional

{ } Encloses items that may be repeated

< > Encloses a variable nam e or num ber for w hich you

mu st substitute information

, Ind icates a range for an integer variable Indicates the start of an option nam e

+ Indicates the start of an option name

: Binds a variable name to a range

| Logical OR to indicate a choice of one out of many

items. The OR operator may only separate logical

groups or literal keyword s.

( ) Encloses a logical grou ping for a choice betw een

subformats


32/535



Invoking Command Line Programs

You star t Xilinx Developm ent System command line p rogram s by

entering a command at the UNIXor DOS command line. See the

chapters in this book for the approp riate syntax.In ad dition, Xilinx offers the XFLOW p rogram , which a llows you to

au tomate the running of several program s at one time. See the

XFLOW chapter for more information.

Reading NCD Files with NCDRead

A N ative Circuit Description (NCD) file contains a p hysical

description of your design in terms of the components in the target

architecture. NCDRead enables you to qu ickly generate an ASCII

(text) file based on the data found in one or m ore NCD files.To start N CDRead from the UN IX or DOS comm and line, type the

following.

ncdread [ooutfile_name] filename1.ncd

{filename2.ncd ...}

Note Standard output goes to your screen if you d o not u se theo option to wr ite the outpu t to a file.


33/535


Chapter 2

Design Flow

This chap ter describes the process for creating, imp lementing,

verifying, and d own loading d esigns for FPGA and CPLD devices.

For a comp lete description of FPGAs and CPLDs, refer to The

Programmable Logic Data Book.

This chap ter contains the following sections:

Design Flow Overview

Design Entry an d Synthesis

Design Implementation

Design Verification

FPGA Design Tips


34/535



Design Flow Overview

The standard design flow consists of the following steps:

Design Entry and Synth esisIn this step of the design flow, you

create you r design u sing a Xilinx-sup por ted schematic editor, aHardw are Description Language (HDL) for text-based entry, or

both. If you use an HDL for text-based en try, you must syn thesize

the H DL file into an EDIF or XNF file or, if you a re using th e

Xilinx Synthesis Technology (XST) GUI, into an NGC file.

Design ImplementationBy implemen ting to a sp ecific Xilinx

architecture, you convert the logical design file format, such as

EDIF, that you created in the d esign entry or synth esis stage into

a physical file format. The physical information is contained in

the N ative Circuit Description (NCD) file for FPGAs and the

VM6 file for CPLDs. Then you create a bitstream file from thesefiles and opt ionally program a PROM or EPROM for subsequent

programm ing of your Xilinx device.

Design VerificationUsing a gate-level simu lator or cable, you

ensure that your d esign m eets your timing requirements and

functions properly. See the iMPACT User Guide for information

about Xilinx d ownload cables and demonstration board s.

Note In add ition to the stand ard d esign flow described in th issection, you can break your design into m odules for team-based

design and ru n the Mod ular Design flow. See the Modu lar Designchapter for d etails.


35/535

Design Flow


The following figure shows the Xilinx design flow.

Figure 2-1 Xilinx Design Flow Overview

The fu ll design flow is an iterative process of entering, imp lementing,

and verifying you r d esign until it is correct and complete. The Xilinx

Developmen t System allows quick design iterations through the

design flow cycle. Because Xilinx devices permit un limited

reprogramming, you do not need to d iscard d evices when d ebugging

your design in circuit.

X9537

DesignImplementation

Optimization

FPGAsMapping

Placement

Routing

CPLDs

Fitting

BitstreamGeneration

DesignSynthesis

DesignEntry

Download to aXilinx Device

Design Verification

FunctionalSimulation

Static TimingAnalysis

TimingSimulation

BackAnnotation

In-CircuitVerification


36/535



The following figure shows the Xilinx software flow chart for FPGA

designs.

Figure 2-2 Xilinx Software Design Flow (FPGAs)

X9491

V &SDF 2.1

VHD &SDF 2.1

SimulationLibraries

CORE Generator LogiBLOX

Schematic Capture

Constraints Editor NGD

UCF

MEM

HDL

NGCSymbol

Symbol

NGDAnnoNGM & PCF

EDIF2 0 0

MAPFloorplanner

VEO

EDN

VHO VEI VHI

TRACE &Timing Analyzer

PAR

BitGen

Synthesis Simulation

EDIF 2 0 0 &Constraints/NCF

NGC(XST Netlist)

XNF v6 &Constraints

NGA

NGD2VER, NGD2VHDL, NGD2EDIF

TestbenchStimulus

NCD & PCF

NCD

NGDBuild NGDBuildNGDBuild

SynthesisLibraries

SchematicLibraries

BIT

iMPACT

PROM File FormatterPROMGen


37/535

Design Flow


The following figure show s the Xilinx software flow chart for CPLD

designs.

Figure 2-3 Xilinx Software Design Flow (CPLDs)

Design Entry and SynthesisYou can enter a design with a schematic editor or a text-based tool.

Design entry begins with a design concept, expressed as a d raw ing or

functional description. From the original d esign, a netlist is created,

then syn thesi

Dev Sys Ref Guide

Documents

Transcript of Dev Sys Ref Guide