Detector Data Link (DDL)
-
Upload
sydney-beard -
Category
Documents
-
view
30 -
download
0
description
Transcript of Detector Data Link (DDL)
![Page 1: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/1.jpg)
DDL hardware, DATE training 1
Detector Data Link (DDL)
DDL hardware
Csaba SOOS
![Page 2: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/2.jpg)
DDL hardware, DATE training 2
Readout system
Front-end electronicsFront-end electronics
DetectorData Links
DDL SIUDDL SIU
DDL DIUDDL DIU
RORCRORC
SourceInterfaceUnit
DestinationInterfaceUnit
ReadOutReceiver Card
LDCLDCLocalDataConcentrator
Front-EndDigitalCrate/Computer
P2 Cavern
P2 Accessshaft
Optical Fibre~200 meters
![Page 3: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/3.jpg)
DDL hardware, DATE training 3
DDL architecture
• Source Interface Unit (SIU) (1)
– Interface to the Front-end Electronics (2)
• Destination Interface Unit (DIU) (3)
– Interface to the Readout Receiver Card (4)
• Full duplex optical link (5)
– Multimode optical cable of up to 200 m
1
2
3
4
5
![Page 4: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/4.jpg)
DDL hardware, DATE training 4
DDL hardware
![Page 5: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/5.jpg)
DDL hardware, DATE training 5
DDL interfaces
• SIU-FEE interface– 3.3V (LVTTL) interface
– 32-bit wide half-duplex data bus (bi-directional bus)
– Bi-directional flow control
– User defined clock (synchronous interface)
– JTAG interface
• DIU-RORC interface– 3.3V (LVTTL) interface
– 32-bit wide full-duplex data bus
– Bi-directional flow control
– User defined clock (synchronous interface)
![Page 6: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/6.jpg)
DDL hardware, DATE training 6
SIU-FEE interface
fbD(31..0) - data lines (bi-directional)fbTEN_N - data enable (bi-directional)fbCTRL_N - data qualifier (bi-directional)fiDIR - bus direction (FEE input)fiBEN_N - bus enable (FEE input)fiLF_N - link full (FEE input)foBSY_N - front-end busy (SIU input)foCLK - interface clock (SIU input)TAP_TCK - JTAG clock (FEE input)TAP_TDI - JTAG data in (FEE input)TAP_TDO - JTAG data out (SIU input)TAP_TMS - JTAG mode select (FEE input)TAP_TRST - JTAG reset (FEE input)
![Page 7: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/7.jpg)
DDL hardware, DATE training 7
DIU-RORC interface
riD(31..0) - data lines (RORC input)
riTEN_N - transfer enable (RORC input)
riSTS_N - data qualifier (RORC input)
riLF_N - link full (RORC input)
riLD_N - link down (RORC input)
roD(31..0) - data lines (DIU input)
roTEN_N - transfer enable (DIU input)
roCMD_N - data qualifier (DIU input)
roBSY_N - RORC busy (DIU input)
roRST_N - DIU reset (DIU input)
roCLK - interface clock (DIU input)
![Page 8: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/8.jpg)
DDL hardware, DATE training 8
Link management
idle
off-lineoff-line
on-line on-line
DIU SIURORC
Power-on
Power-onSIU resetReset
Link up
SIU reset
Offline
Online
Offline
Onlineon-line
on-line
![Page 9: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/9.jpg)
DDL hardware, DATE training 9
Front-end control
on-line on-line
FECTRL
CTSTW
on-line on-line
DIU SIURORCOnlineOnline
FEE command
Report
FEE
FEE control
idle
foCLK
fiBEN_N
fiDIR
FECTRLfbD
fbTEN_N
fbCTRL_N
![Page 10: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/10.jpg)
DDL hardware, DATE training 10
Front-end status read
on-line on-line
FECTRL
FESTW
on-line on-line
on-line
DIU SIURORCOnlineOnline
FEE command
Status and report
FEE
FEE status read
CTSTW
foCLK
fiBEN_N
fiDIR
FESTRDfbD
fbTEN_N
fbCTRL_N
HiZ
HiZ
HiZ
foCLK
fiBEN_N
fiDIR
FESTWfbD
fbTEN_N
fbCTRL_N
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
![Page 11: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/11.jpg)
DDL hardware, DATE training 11
Event read
on-line on-line
RDYRX
CTSTW
DIU SIURORCOnlineOnline
FEE command
Report
FEE
RDYRXCTSTW
FEE data
EOBTR
data blocks
Event data
FEE command
Report
EOBTR
Flow control
foCLK
fiBEN_N
fiDIR
RDYRXfbD
fbTEN_N
fbCTRL_N
HiZ
HiZ
HiZ
foCLK
fiBEN_N
fiDIR
D0fbD
fbTEN_N
fbCTRL_N
HiZ
HiZ
HiZ
fiLF_N
D1 D2 D4 D5
foCLK
fiBEN_N
fiDIR
fbD
fbTEN_N
fbCTRL_N
fiLF_N
FESTWDn-1 Dn D0min. 16 cycles
foCLK
fiBEN_N
fiDIR
fbD
fbTEN_N
fbCTRL_N
fiLF_N
FESTWDn-1 Dn HiZ
HiZ
HiZ
foCLK
fiBEN_N
fiDIR
EOBTRfbD
fbTEN_N
fbCTRL_N
HiZ
HiZ
HiZ
![Page 12: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/12.jpg)
DDL hardware, DATE training 12
Block write
on-line on-line
STBWR
CTSTW
DIU SIURORCOnlineOnline
FEE command
Report
FEE
STBWRCTSTW
FEE data
EOBTRFEE command
Report
EOBTR
Flow control
Block data data block
foCLK
fiBEN_N
fiDIR
D0fbD
fbTEN_N
fbCTRL_N
foBSY_N
D1 D2 D4 D5STBWR
foCLK
fiBEN_N
fiDIR
fbD
fbTEN_N
fbCTRL_N
foBSY_N
EOBTRDn-1 Dn
![Page 13: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/13.jpg)
DDL hardware, DATE training 13
Block read
on-line on-line
STBRD
CTSTW
DIU SIURORCOnlineOnline
FEE command
Report
FEE
STBRDCTSTW
FEE data
EOBTR
data block
Block data
FEE command
Report
EOBTR
Flow control
foCLK
fiBEN_N
fiDIR
STBRDfbD
fbTEN_N
fbCTRL_N
HiZ
HiZ
HiZ
foCLK
fiBEN_N
fiDIR
D0fbD
fbTEN_N
fbCTRL_N
HiZ
HiZ
HiZ
fiLF_N
D1 D2 D4 D5
foCLK
fiBEN_N
fiDIR
fbD
fbTEN_N
fbCTRL_N
fiLF_N
FESTWDn-1 Dn HiZ
HiZ
HiZ
foCLK
fiBEN_N
fiDIR
EOBTRfbD
fbTEN_N
fbCTRL_N
HiZ
HiZ
HiZ
![Page 14: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/14.jpg)
DDL hardware, DATE training 14
PCI RORC
![Page 15: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/15.jpg)
DDL hardware, DATE training 15
D-RORC
![Page 16: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/16.jpg)
DDL hardware, DATE training 16
RORC features
• Interface between the DIU and PCI local bus– pRORC: 32 bit/33 MHz PCI version, max. throughput 132 MB/s– D-RORC: 64 bit/66 MHz PCI version, max. throughput 528 MB/s
• PCI master capability, data push architecture– Autonomous operation with little software assistance– Supports multi-paged memory management
• Direct data transfer to the PC memory– No local memory on the board– Small elasticity buffers between different clock domains
• Built-in test capability– Internal pattern generator can produce formatted data
![Page 17: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/17.jpg)
DDL hardware, DATE training 17
The Free FIFO
PRORC PC memory bankFirmware
readout
page address
page address
page address
Free FIFO
PC CPU
Allocation of free pages
![Page 18: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/18.jpg)
DDL hardware, DATE training 18
Direct Memory Access
PRORCFirmware
PC memory bank
DDL
No involvement
PC CPU
![Page 19: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/19.jpg)
DDL hardware, DATE training 19
The Ready FIFO
PRORC PC memory bank
readout
DDL
Ready FIFOFirmware
addresspage status
addresspage status
addresspage status
Delivery of filled pages
PC CPU
![Page 20: Detector Data Link (DDL)](https://reader034.fdocuments.in/reader034/viewer/2022051315/56812c4e550346895d90d611/html5/thumbnails/20.jpg)
DDL hardware, DATE training 20
Test equipments
• Front-end Emulator Interface Card (FEIC)– Fully functional hardware to emulate the detector front-ends
– Formatted data block generation
– Internal (free running) or external (pulse) triggering capabilities
– Adjustable parameters (using front-end control)
– Operates at the nominal speed of the DDL
• Source Interface Unit Simulator (SIMU)– Simulates the behavior of the DDL without any additional
hardware
– Eases the development and the hardware debugging
– Size is similar to the real SIU