Microelectronics Reliability xxx (2015) xxx–xxx

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Microelectronics Reliability

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Destruction failure analysis and international reliability test standard for power devices

Takashi Setoya ⁎, Tsuneo Ogura, Wataru Saito, Tomoko Matsudai, Koichi EndoToshiba Corp. Semiconductor & Storage Products Company, 1-1-1 Shibaura, Tokyo 105-8001, Japan

⁎ Corresponding author.E-mail address: takashi.setoya@toshiba.co.jp (T. Setoy

http://dx.doi.org/10.1016/j.microrel.2015.07.0420026-2714/© 2015 Published by Elsevier Ltd.

Please cite this article as: T. Setoya, et al., Desics Reliability (2015), http://dx.doi.org/10.10

a b s t r a c t

a r t i c l e i n f o

Article history:Received 18 June 2015Received in revised form 23 July 2015Accepted 23 July 2015Available online xxxx

Keywords:Failure analysisMathematical analysis of reliabilityPhoto emissionPower device degradation

The demand of power devices such as IGBT is expected to continue to increase in the future for Electric Vehicles(EV), Hybrid Electric Vehicles (HEV), and industrial applications. Power devices are affected by stresses, such aslarge current and abrupt temperature changes,which differ from those of normal semiconductor devices, so howto ensure the reliability is an important issue. Especially in practical use, the comprehension of destruction,whichcomprises the great majority of failures, and the control approach, are key points.Wewould like to explain somemeasures to reduce the number of destruction failures.To ensure the power device quality and reliability, the special evaluation and qualification methods are impor-tant; however, if we follow the international standards for testing, a large amount of evaluation samples areneeded. So in Japan Electronics and Information Technology Industries Association (JEITA), activities such asstandardizing of the power device reliability testmethod andmaking a qualification guideline for automotive ap-plications are being performed. In this lecture, wewillfirst explain the trend of power devices and the state of themeasures for the destruction failures. Then we will describe the outline of the reliability standard of the powerdevices, the qualification guideline formulation state for high reliability applications in Japan and the issues ofquality and reliability for compound semiconductors.

© 2015 Published by Elsevier Ltd.

1. History of TOSHIBA power devices

TOSHIBA developed transistors in 1951, and continuously developsand mass-produced semiconductors since then. Particularly, the devel-opment of Insulated Gate Bipolar Transistor (IGBT) was started when apatent of the basic structure was obtained by RCA in 1980. IGBT with anon-latch-up type and stripe gate structure was developed in 1984 [1],and was then mass-produced and released in 1985. After this, InjectionEnhanced Gate Transistor (IEGT) was developed and mass-produced in1993.

As for power metal-oxide-semiconductor field-effect transistors(MOSFETs), hexagonal shape MOSFET (HEXMOSFET) with a basicdouble-diffused MOSFET (D-MOS) structure was mass-produced by IRin 1980. At around the same time, TOSHIBA released power MOSFETswith mesh patterned gate, and started to develop and mass-producepower MOSFETs with 900 V and 1200 V in 1988. Then, DTMOS with aSupper Junction (SJ) structure was mass-produced in 2007, and thesingle epitaxial process (deep trench filling with epitaxial growth Siprocess) was adopted and the minimum on-resistance products atthat time were mass-produced in 2012. Moreover, these were expand-ed to make the line up with 650 V and 800 V [2].

As mentioned above, TOSHIBA has the history of power devices forover 35 years, and is leading the world in their development. In low

a).

truction failure analysis and in16/j.microrel.2015.07.042

voltage power MOFETS, the on resistance has been reduced to 1/10 bytrench gate structure and miniaturization in these 15 years. In highvoltage power MOSFET, the on resistance has been reduced 1/10 by SJstructure and miniaturization in these 20 years.

Fig. 1 shows the history and chronological table of the IGBT develop-ment. In IGBT, the Punch Through structure that the expanse controlledof the depletion layer with n-base buffer layer was developed.

Next, the Non-Punch Through structure to control positive holeinjection from p + collector, and to plan switching loss reduction wasdeveloped. For trench gate structure, IGBT (IEGT: Injection EnhancedGate Transistor) which made structure to thin out some channeldomains with promoted electronic injection was developed.

TOSHIBAwill continue to develop them in order to lower power lossand to ensure a high voltage in a small chip size.

2. Prospects and challenges

Fig. 2 shows an estimation of the market scale growth of the powerdevices [3]. The power devices are expected to be expanded for EV, HEV,trains and power conversions of renewable energy. The power devicesare required to operate under high temperature condition, becausethe inverter system is requested to be installed in the engine room forHEV. The simplified water cooling system is also needed in higheroperating temperatures. In order to achieve this, power devices usinga wide-bandgap semiconductor material, such as SiC, which can be op-erated at higher temperatures, are being developed. SiC power devicesare actually adopted in the inverters of commuter trains as shown in

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Fig. 1. Development history of IGBT.

Fig. 2. Market size of the power device.

Fig. 4.Main market failure modes classification of the power devices.

Fig. 5. Example of melted destruction failure.

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Fig. 3. They have already contributed to energy saving by reducing theelectric power consumption by a maximum of 36% [4]. In this way, theapplications of power devices have been expanded for EV, HEV, trains,etc. However, the quality requirements are stricter and a longer lifeneeds to be achieved for automotive applications and industrialproducts.

Fig. 3. The commuter train which adopted full SiC inverter.

Please cite this article as: T. Setoya, et al., Destruction failure analysis and inics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.042

3. Approach to destruction failures

First of all, the approach to destruction failures is indispensable forthe quality assurance of Si power devices. Fig. 4 shows the investigationresults of the failuresmodes in the power device field. According to this,75% of failures are caused by destruction. Reducing the destruction fail-ure is the most important step in improving quality in the field [5].

Most of the destruction failures are caused by overstress, which ex-ceeds the rating of the products; however, it is also required to reducethe defects in the power devices considering their field operations andto reject those defectswith low tolerance screening. Although the inves-tigation of destruction failures is important for the reduction of thenumber of failures that occur, the analysis of actual broken products

Fig. 6. Test circuit for avalanche breakdown in a power MOS FET.

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Fig. 7. System conception diagram of transient thermal response measurement of PowerMOSFET avalanche breakdown by equivalent time sampling technique.

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on the field has proven difficult due to melted destruction point, asshown in Fig. 5.

Thus, TOSHIBAhas carried out three approaches: observing the actualoperation in the destruction process, analyzing the defects and evaluat-ing the ruggedness of the actual products in the field, and analyzingthe destruction process with technology CAD (TCAD) simulation. Fromthere, TOSHIBA proceeded with the investigation into the cause of lowruggedness, the process control, and the feedback to the design section.

To begin with, as an observation of the actual device operationmode, in a test circuit causing an avalanche breakdown in a powerMOSFET, with no regeneration current circuit to release energy withthe inductive load as shown in Fig. 6, the power devices are consideredto be broken with lack of balanced operation by variations ofmanufacturing or something defects. In the circuit of Fig. 6, when the

Fig. 8.Measurement resu

Please cite this article as: T. Setoya, et al., Destruction failure analysis and inics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.042

MOSFET is switched from ON to OFF, drain current flows due to an ava-lanche breakdown caused by the energy charged in the inductance. Atthe time of this avalanche breakdown, it is known that a wide wave-length emission occurs in Si [5].

Due to this, we have observed the temperature distribution by lock-in thermography (LIT) and the current induced photo-emission by timeresolved emission (TRE) microscopy. It is difficult to perform continu-ous observation of the switching operation since insufficiency of thedata transfer time of camera in LIT, so we used the equivalent timesampling method. Fig. 7 shows the equivalent time samplings systemdiagram, and Fig. 8 shows the data composition images. When we ob-serve multiple operation waveforms, we record the infrared intensityinformation obtained from the camera, while extending the delaytime (tdelay) from the trigger signal by the integer multiples of eachfixed delay time (Δt). Then, by putting it in order of every measuredtime, one excessive heat response waveform can be acquired. Therecomposed data will become time dependent two dimensional data,and by comparing the temperature changes in the samples from thisdata set, we can check if an unexpected temperature distribution exists.Fig. 8 shows exemplary data to using this method [7].

Fig. 9 shows the samples for observing the avalanche breakdownphenomenon of the power MOSFET using TRE [6]. As a result, we canconfirm the linking state of the counter-electromotive force from induc-tive load and the 100 ns current vibrations under avalanche breakdowncondition, so we can make use of it for observing the current densityvariation in the chip at the time of a high-speed turn-off. TRE is a deviceto observe the emission in the power device as well as EMS/PEM(photo-emission microscope), and its feature is to acquire the highS/N ratio of photon measurements and the time resolution in dozensof pico-second levels for the photon observation time. It has been con-sidered that performing an observation the emission is difficult becauseof the existence of electrode metal all over the power device surface;however, the noise level is small in TRE, so the S/N ratio is high forweak emission and even a slight photon can be observed through themetal [6].

lt of each chip area.

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Fig. 9. Current distribution measurement with TRE [6].

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In both observations using LIT for a heat-generating operation andusing TRE for a high-speed current distribution, the observation datais acquired by repeating the device operation and accumulating. Unfor-tunately, the moment of the destruction cannot be observed in thesemethods. But these data can help to construct physical models, to im-prove the comprehensions of the destruction phenomenon and to de-termine whether or not the operation before the failure is causeddiffers from the design value or the lack of operating balance, etc.

In the physical analysis, as a way of detecting the defects in thepower devices, two methods are proposed. One method is generatingmulti-photon excitation in an area in the Si substrate so that the space

Fig. 10. TCAD simulation of the current co

Please cite this article as: T. Setoya, et al., Destruction failure analysis and inics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.042

charge in that area can be detected, visualizing it as an increasing partof the avalanche gain, and visualizing the electric field concentrationpart which can be the cause in the condition in which the current caus-ing the destruction does not flow [8]. The other method is to detect thecontact or trench defects in IGBT by the Nano Electrostatic Field ProbeSensor (NEPS). The damaged area can be inferred by making imagesof the carrier signal changes which are generated when a laser beamis irradiated to the samples in the non-bias state without probes beingapplied electrically [9].

Next approach is the TCAD simulation. Fig. 10 shows the TCAD sim-ulation results on the electric concentration of IGBTwhen it is turned off

ncentration in the turn-off of SCSOA.

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Table 1Dissection item in the reliability of SiC device.

(1) Defect of SiC crystal.(2) Dislocation by forward current.(3) Reliability of the oxidation film on SiC(4) Vth degradation by bias applying.(5) A high electric field hangs to the material of the Chip terminal part.(6) Influence of cosmic rays.(7) Are the reliability acceleration characteristics same as Si devices?(8) Reliability in the super high temperature state and reliability guarantee.(9) Process control method(10) System feedback in anticipation of characteristic degradation.

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in short-circuit safe operating area (SCSOA) depending on the gate re-sistance. In the slow turn-off mode with a large gate resistance, no cur-rentfilamentation occurs in the bulk. However, in the fast turn-offmodewith small gate resistance, the current filamentation occurs in the bulk.We can estimate that the dynamic avalanche occurs since the electricfield is over 3e5 V/cm locally in its distribution in a vertical direction[10,11].

According to the combination of the observation of the actual oper-ation, the physical analysis of the power devices [12], simulations andanalyzing the destruction phenomenon in detail is effective for under-standing its phenomenon and improving the ruggedness.

4. Trend of power device international standard and introduction ofJEITA activities

The purpose of JEITA, a Japanese industrial group, is mainly tostandardize the reliability test standards of semiconductor devices. Inthe individual semiconductor (power-related) reliability test knownas PG (Project Group), the test method for repeated heat stress wasnot standardized in the large power devices for EV and HEV. Due to anexpected increase and expansion in use, the reliability test standard(power cycle testmethod) of power devices for automotive applicationsand industrial products was established and issued as ED-4701/600 in2013.

Since the defects caused by the repeated heat stress determine thepower device life, this is an extremely important test. The defect modediffers depending on the repeated operation conditions, so three typesof repeated heat stress tests (power cycle) were established and issuedas tests for detecting each defect mode. This standard (ED-4701/600)can be browsed in the following URL [13].

URL:http://www.jeita.or.jp/cgi-bin/standard_e/list. cgi?cateid =5&subcateid = 34.

Fig. 11 shows a part of the document describing the differenceamong the three types of test methods. In the non-mold type powercycle, there are two defective modes: one in which DBC board and thechip mount solder have deteriorated because the whole case is heated,and the other in which the temperature of the junction area on the chipsurface rises drastically in a short time of a few seconds, and due to thestress difference between Si and A1 because of this heat, the Al bondingjunction area is peeled off and an open failure occurs [14]. It is therefore,a requirement to perform the acceleration test in which each defectivemode can be detected and to estimate the actual life in actual use. JEITAED4701/600 has provided two test methods: One is the power cyclelong time test method (603) to evaluate the deterioration of the solder

Fig. 11. New test metho

Please cite this article as: T. Setoya, et al., Destruction failure analysis and inics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.042

material between the Cu base and the DBC board, and the chip and theDBC board. The other is the power cycle short time test method (602).This is used to evaluate the defects in which the Al bonding junctionarea is peeled and an open failure occurs due to the stress difference be-tween Si and A1 [13].

Currently, the establishment of a qualification guide of the individualsemiconductors for automotive applications, in which high quality isdemanded, is ongoing. The standard including (1) screening method,(2) avalanche screening, (3) gate screening method and (4) samplesize guide, is to be issued as JEITA EDR-4711 in 2015.

5. Reliability of compound power semiconductor elements

In SiC and GaN power devices, the switching dissipation and power-on dissipation are expected to be drastically reduced in comparisonwith Si devices; however for the reliability, there is a problem in charac-teristic variation such as Current Collapse, so a testmethod to ensure thereliability urgently needs to be established. The reliability of the com-pound semiconductors is still being reviewed in academic society, so itmay take time for it to be actually used in a wide and safe manner. Butfor now, we need to establish a new test method with the samestandard and the members concerned have to discuss this matter in apositive way.

Table 1 shows the issues of quality and reliability for compoundsemiconductors. Since a test method to evaluate these issues has notyet been developed, JEITA created a project group for the compoundpower device reliability test method in 2015, and will proceed withthe standardization of its reliability test method and the assurancemethod of the compound power semiconductor, obtaining the testdata from each company.

d: power cycle test.

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6. Conclusion

The use of power devices are projected to expand in the future.Withthis expansion, comes the expectation of an increase in types of use inwhich higher quality and greater reliability are needed in comparisonwith household sectors, such as EV, HEV, and trains. The main problemin actual use is destruction failure. In this report, we have describedsome measures to deal with this failure. Moreover, as an analysis ofthe process causing destruction,we have also explained the observationof the heat variation using both LIT and the equivalent time samplingmethod at the time of turning-off, the observation using TRE forhigher-speed operation by emission penetrating through the A1 elec-trode at the time of switching, and the observation of defects. Further-more we have described the current measures for a comprehensiveunderstanding of the destruction phenomenon by checking the destruc-tion operation by TCAD simulation and to improve the ruggedness.

As a means of confirming the long-term reliability of power devices,integrating the test method is an important issue. So we have intro-duced the power cycle test method being performed in JEITA and thecontents being discussed in the qualification guide line of the power de-vices for automotive applications. These need to be standardized in thefuture after open discussions and wewill proceed to perform this in co-operation with other countries.

Acknowledgment

We greatly appreciate the co-operation of Professor Nakamae fromOsaka University and Professor Wolfgang, who gave us the opportunity

Please cite this article as: T. Setoya, et al., Destruction failure analysis and inics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.042

to explain the quality, reliability, and standardization activities ofJapanese power semiconductors in ESREF.

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