Designing VLSI Circuits and Systems

with Nano Electro-Mechanical Relays

Vladimir Stojanović (MIT)

in collaboration with

Tsu-Jae King Liu, Elad Alon (UC Berkeley)

Dejan Marković (UCLA)

CMOS ET Workshop 2011

June 16, 2011

2

Subthreshold Leakage: Game Over for CMOS

Leakage and sub-threshold slope define minimum

energy/op for CMOS

Parallelism cannot reduce power/throughput if already

operating at minimum energy

Eleakage

Edynamic

Etotal

0.1 0.2 0.3 0.4 0.5

5

10

15

20

25

VDD (V)

Norm

aliz

ed E

nerg

y/op

0 1 2 3 41/throughput

5 6

8

9

10

11

Norm

aliz

ed E

nerg

y/op

1x

2x8x

More parallelism

does not help

3

NEM Relays to the Rescue

NEM relays show zero leakage & sharp sub-threshold slope

Could potentially enable reduced E/op with scaling

Emin set by contact bond energy

~2aJ/switch (50x better than 90nm CMOS)

Measured MEM Relay I-V Curve MEM Relay Energy vs. VDD

3R. Nathanael et al., “4-Terminal Relay Technology for Complementary Logic,” IEDM 2009

Etotal=Edynamic

4

NEM Relay Structure and Operation

ON Relay:

|Vgb| > Vpi (pull-in voltage)

OFF Relay:

|Vgb| < Vpo (pull-out voltage)

Poly-SiGe Anchor

Poly-SiGe Beam

/Flexure

Tungsten Body

Tungsten Source/Drain

Tungsten Channel Poly-SiGe Gate

5

Power-gating CMOS with NEM Relays

S D

B

GG

G G

55

μm

85μm

0

0.4

0.8

1.2

VD

D (

V)

-0.1 -0.05 0 0.05 0.10

1

2

3

0.15

Time (s)

Syn

c CM

OS (

V)

5

6

7

8

VG (

V)

DV

G =

2V

Vb

VH

R OSC

COSCR1

R2

C1

C2 External pulse gen

VG

VDD

to CMOS logic

A

VEXT,R

Power gate

Self-driven pulse generator

0 0.5 1 1.5 2 2.5 3 3.50

2

4

6

8

Time (s)

Vol

tage

(V)

3% Duty Cycle

Power-gating input (VOSC)

Gated CMOS VDDH. Fariborzi et al.

CICC 2010

6

Energy Gain Over CMOS Limited to Large Toff

Energy gain G

Large Toff

Switching overhead negligible

32 45 65 90 130 180 25010

1

102

103

104

105

106

107

108

Technology node (nm)

To

ff (s)

1

2

5

10

VIO=VEXT,MVIO=VNOM

Energy gain

,on M off offM

R DD on

kR I TEG

E V T

CMOS LOGIC

VEXT,M

sleep VIO

VEXT,R

sleep VG

CMOS LOGIC

(a) (b)

VDDVDD

βCL βCLp L, , f ,C

p L, , f ,C

eCRγCM

CM CR

VEXT,M

7

Area Savings More Significant

10-2

10-1

100

101

102

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

I on [

A/m

m2]

Relay 10s 10k

Relay 1ms 10k

Relay 10s 1k

Relay 1ms 1k

Ton Ron,R

MOS 10s 1%

MOS 1ms 1%

MOS 10s 10%

MOS 1ms 10%

Ton overhead

MOS technology node and relay device pitch [m]

Current

Relay

Scaled

Relay

90nm

CMOS

Peak

Current

density

Relays fabricated in metal backend - no area overhead

Today: 1 mA/mm2 (ready for low-power apps)

Scaled: 10-100 mA/mm2 (ready for high-power apps)

8

NEM Relay as a Logic Element

Simple model

Mechanical – spring, mass, damper

Electrical – RC

4-terminal relay mimics MOSFET switch

Electrostatic actuation is ambipolar

Non-inverting logic is possible

Actuation independent of source/drain voltages

Spring k Damper bMass m

Cgb

G

S D

Rcs Rcd

B

Cgc

CdbCsb

Anchor

Mechanical

Model

Rs Rd

9

Digital Circuit Design with NEM Relays

CMOS: delay set by electrical time constant

Quadratic delay penalty for stacking devices

Buffer & distribute logical/electrical effort over many stages

NEMS: delay dominated by mechanical movement

Can stack ~100-200 devices before td,elec ≈ td,mech

So, want all to switch simultaneously

Implement logic as a single complex gate

NEMS: 12 switches

10

Need to Compare at Block Level

Delay Comparison vs. CMOS

Single mechanical delay vs. several electrical gate delays

For reasonable load, NEMS delay unaffected by fan-out/fan-in

Area Comparison vs. CMOS

Larger individual devices

But often need fewer devices to implement same function

4 gate delays 1 mechanical delay

F. Chen et al., “Integrated Circuit Design with NEM Relays,” ICCAD 2008

NEMS: 12 relays

11

Example: 32-bit NEMS Adder

Ripple carry configuration

Cascade full adder cells to

create larger complex gate

Stack 32 NEMS, but still

single mechanical delay

12

Compare vs Sklansky

CMOS adder*

90nm technology

30x less capacitance

Lower device Cg, Cd

Fewer devices

2.4x lower Vdd

No leakage energy

Scaled NEMS vs. CMOS Adders

*D. Patil et. al., “Robust Energy-Efficient Adder Topologies,” in Proc. 18th IEEE Symp.

on Computer Arithmetic (ARITH'07).

For similar area: >9x lower E/op, >10x greater delay

9x

10x

Energy/op vs. Delay/op across Vdd

13

Can extend energy

benefit up to GOP/s

throughput

As long as parallelism

is available

Area overhead bounded

CMOS needs to be

parallelized at some

point too

Parallelism: Trade Area for Performance

Energy/op vs. Delay/op across Vdd & CL

14

Low contact R not

critical

Good news for

reliability…

Relays with W

contacts lived through

65 B cycles

Contact Resistance

Energy/op vs. Delay/op across Vdd & CL

15

NEM Relay Circuit Technology PlatformISSCC 2010 – TD Award

F. Chen et al, ISSCC2010

M. Spencer et al, JSSC Jan’11

16

Verilog-A model and Logic Synthesis created for NEMS technology

The flow supports multiple device designs and foundries

NEMS VLSI design infrastructure

Device

Verilog-A

Model

DRC

B B

Vout

A A

Schematic

Layout

P-cell

Verilog

Spectre

Place & Route

LVS

SynthesisLogic

Synthesis

Place & Route

Verilog-A

Model

17

Toward full systems - NEM Relay scaling

1um litho

Scaled Relay size

20um x 20um

Sematech

Relay size

120um x 150um

0.25um litho

18

Conclusions

NEMS unique features enable energy scaling beyond-CMOS

Nearly ideal Ion/Ioff

Switching delay largely independent of electrical

Need to adapt circuit design style

Reliability improving

Circuit level insights critical (contact R)

Demonstrated simple circuits

Started building more complex and scaled systems

Potentially order of magnitude lower E/op than CMOS

Next steps: Large scale demonstration >10k relay uC block with

scaled relays

19

Acknowledgements

Circuit design

Fred Chen, Hossein Fariborzi

Matthew Spencer, Abhinav Gupta

Cheng Wang, Kevin Dwan

Device design

Hei Kam, Rhesa Nathanael, Vincent Pott, Jaeseok Jeon

Sponsors

DARPA NEMS program

FCRP (C2S2, MSD)

MIT CICS

Berkeley Wireless Research Center

NSF

20

Higher contact R, hard contact (W) improves reliability

Limits power dissipation, material flow

Current endurance record: 65 billion cycles

Theory/experiments predict >1015 cycles @ 1V VDD

Contact Reliability Experiments

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+0 1.E+3 1.E+6 1.E+9

No. of on/off cycles

Co

nta

ct re

sis

tan

ce

[Ω

]

100k specification

L=25m

Measured in ambient

H. Kam et al., “Design and Reliability of a Micro-Relay Technology…,” IEDM 2009

H. Kam et al., “A Predictive Contact Reliability Model for MEM Logic Switches,” IEDM 2010