Designing the 8086/8088 Microcomputer System

Typical Microprocessor Based System

CPU Memory/IO

Control

Address

Data

8086/8088 Busses• Address Bus

– 20 address lines so a 220 byte address space.– Pins A0-A19 provide the address– For 8086, A0-A15 are multiplexed with D0-D15 to form AD0-AD15– For 8088, A0-A7 are multiplexed with D0-D7 to form AD0-AD7

• Data Bus– For 8086, 16 bit data bus D0-D15 (multiplexed as AD0-AD15)– For 8088, 8 bit data bus D0-D7 (multiplexed as AD0-AD7)

• Control Bus– For memory access, the following pins are used:RD’, WR’, M/IO’, DT/R’, DEN’, ALE, BHE’

– Other input signals to control 8086 performance:clk ,reset , ready , hold , test’, intr , nmi ,mn’/mx

- The intr and hold are acknowledged through intra and holda respectively.

8086/8088 Pin Configuration

8086 Control Pins

8284A

Clock Generator

Ready logic (adding wait states)

8086/8088 Detailed Memory Interface

8086/8

Control

Multiplexed

Addr/Data

Latches

Buffers

Demultiplexing

Control

Address

Data

Address Decoding

Unique per device

MEMORY

Partial

Address

CS’,WE’,OE’

8088 Bus Structure

8086 maximum & minimum modes• The mode is controlled by MN/MX.

• Maximum mode is obtained by connecting MN/MX to high and minimum mode is by connecting it to high.

• Having two different modes (minimum and maximum) is used only 8088/8086.

• Each mode enables a different control structure.

• Minimum mode operation and control signals are very similar to those of 8085.

• So 8085 8-bit peripherals can be used with 8086 without special considerations.

• Easy and least expensive way to build single processor systems

8086/8088 Pin Configuration Differences

Maximum mode• Maximum mode is designed to be used with a coprocessor exists in

the system.

• All the control signals (except RD ) are not generated by the microprocessor.

• But we still need those control signals.

• Solution:

• 8288.

S2 S1 S0 operation signal

0 0 0 Interrupt Acknowledge INTA

0 0 1 Read I/O port IORC

0 1 0 Write I/O port IOWC, AIOWC

0 1 1 Halt none

1 0 0 Instruction Fetch MRDC

1 0 1 Read Memory MRDC

1 1 0 Write Memory MWTC, AMWC

1 1 1 Passive none

QS1 QS0 0 0 No instruction taken from queue. 0 1 First byte of current instruction taken from queue. 1 0 Queue flushed. 1 1 Byte other than first byte taken from queue.