Power Electronics Technology October 2005 www.powerelectronics.com October 2005 www.powerelectronics.com38

refl ected in the primary as IP=I

ON

S/N

P, where N

S is the

number of secondary turns and NP is the number of primary

turns. Output voltage is VO

turns. Output voltage is VO

turns. Output voltage is V =VIN

DNS/N

P, where D=T

ON/

TS and 1/T

S is the switching frequency. Magnetizing current

in the transformer primary just before turnoff is VIN

TON

/L

M. When Q1 turns off, the transformer voltage tends to

reverse. Voltage on the DTR cathode keeps decreasing until DTR turns on.

For typical applications, the NP/N

R turns ratio is 1, where

R turns ratio is 1, where

R

NR is the number of turns in the primary reset winding.

The transformer magnetizing current now decreases from I

M to zero. When it reaches zero, the transformer is fully

reset and voltage across the transformer remains at zero until the start of the next switching cycle. The maximum duty cycle (D

MAX) in these applications is limited to 50%.

On the other hand, single-switch, resonant-reset forward converters (Fig. 1) are characterized by the absence of a reset winding. During the off time, the transformer resets (without loss) through a resonant circuit consisting of the magnetizing inductance and the combined capacitance of the switch (C

S), primary winding (C

P) and all refl ected

secondary capacitances (CRS

), including the rectifying-diode capacitance.

Description of Operation

Assumptions are made in the following circuit analysis:

● The circuit has reached steady-state operation.

● LO and C

O (fairly

large) can be considered infi nite.

● Leakage induc-tance is neglected.

● Drops due to the

Designing Single-Switch Forward ConvertersOften used in dc-dc converter modules for power levels below 100 W, single-transistor, resonant-reset forward converters are also useful for dc-dc converters with adjustable output voltages.

By Suresh Hariharan, Senior Corporate Applications Engineer, and David Schie, Director of IC Design, Maxim Integrated Products Inc., Sunnyvale, Calif.

Among power-converter topologies, the single-transistor forward converter is one of the most common for power levels below 100 W. This article, however, focuses on the improvements to the circuit known as the

single-transistor, resonant-reset forward converter, which eliminates the reset winding and a diode (DTR) while offering several other advantages.

Its duty cycle can exceed 50%, making it suitable for low-cost dc-dc converters that operate from a wide range of input voltages and deliver widely varying outputs. The absence of a reset winding reduces costs by simplifying the transformer, especially for the planar transformers widely used in high-density dc-dc converter modules. Finally, the resonant-reset circuit’s sinusoidal reset voltage reduces EMI.

To properly appreciate the resonant-reset topology, we must fi rst understand the conventional single-switch forward converter (Fig. 1). When switch Q1 turns on, the transformer current rises from zero and the diode DTR is reverse biased. Transformer magnetizing current builds up to a value I

M=V

INT

ON/L

M, where T

ON is the on time per

switching cycle and LM

is the magnetizing inductance.During the switch’s on period, the load current I

O is

Fig. 1. A conventional single-transistor forward converter (a). A single-switch, resonant-reset forward converter (b).

VININ

CIN

TR

Q1

IO

VVOVOVDDRR LOO

DD

GG S

DDF

CCCCO

DDDDTRTRTRTRTRTRTR

IN

PP RSRSRS

TRTRTRTRTR

RO

V

CCCC

Q1

DDD

S

IN

C CCCC

CGGG

S

DD

CD

C

IOO

LOO OOOVOVO

(a) (b)

www.powerelectronics.com Power Electronics Technology October 2005www.powerelectronics.com Power Electronics Technology 39

FORWARD CONVERTERS

Fig. 2. From Fig. 1b, an equivalent circuit for the voltage on Q1 and the primary magnetizing-current waveform during Interval 1—not to scale (a). From Fig. 1b, an equivalent circuit for the voltage on Q1 and the primary magnetizing-current waveform during Interval 2—not to scale (b). From Fig. 1b, an equivalent circuit for the voltage on Q1 and the primary magnetizing-current waveform during Interval 3—not to scale (c).

VIN

CIN

IOO

DR

LOO

DD

G

SS

DDF CO

ONTTONTON

INV

I1=-I2

I2

RTTTT

STTSTS

TT=O

O

MAGI

DSV INVVVVV + I L + I L + I L + I L + I L C2+ I L 2+ I L M+ I L M+ I L R

–––

++NSNP

ISSIP = P = 00

IMAG

LM

++++

++

CD

–– ++

//+ I L /+ I L + I L /+ I L

VIN

CIN

IOO

DR

LOO

DD

GSS

D F CO

ONTTONTON

INV

I1=-I=-I2

I2

RTTTT

T

T=O

O

MAGI

DSV ININVVVVVV + I L + I L C2+ I L 2+ I L M+ I L M+ I L R

––

+N SNNNP

IIISSS

IIIPP

IMAG

LM

++++++

++++

CCT

––+++CCS

CCR

III RRRRR

/+ I L /+ I L

CD

VININVINV

CIN

IOO

DR

LOO

DD

GSS

DDDFF

CO

ONTONTON

INV

I2

TT=O

O

MAGI

DSV

–

+++N SN P

ISSIPP

IMAGMAG

LM

++++++

++

CDD

–– ++

T

ONTTTONTON

I1

IR

(b)

(c)

(a)

diode and switch on-resistance are neglected.Steady-state operation for the circuit comprises three

intervals in each switching cycle:Interval 1. Initially, t=0 and Q1 is on (Fig. 2a). The transformer is magnetized with a ramp current during this interval, defi ned as T

ON. Secondary current fl ows through

the secondary diode DR, and the voltage across capacitance C

D is approximately zero. C

D includes the internal diode

capacitance and the external capacitance added across diode DR. The primary magnetizing current has a value of I

1 at the

start of this interval and I2 at the end of the interval:

I I

V T

LINV TINV TONV TONV T

M

2 1I I2 1I I= +I I= +I I2 1= +2 1I I2 1I I= +I I2 1I IV T×V T

(Eq. 1)The primary current I

P

is the sum of the refl ected current I

R (equal to I

R (equal to I

R ON

S/

NP) and the pr imar y

magnetizing current IMAG

.Inte r va l 2 . When the switch is turned off, the switch Q1 drain-to-source voltage begins to r ise (Fig. 2b). When that voltage exceeds V

IN, the polarity

across the secondar y winding is reversed. Then the secondary diode DR turns off and the freewheeling diode DF turns on. A sinusoidal demagnetization current star ts to f low through the resonant circuit formed by the parallel combination of transformer magnetizing inductance L

M and the capacitance

CR reflected across the

transformer primary. The capacitance C

R is the sum

of all capacitances across the primary including the reflected capacitance C

D,

the internal plus external capacitance across diode DR (internal diode capacitance of DR<<C

D):

C C

N N

NC CR DC CR DC C S

P

S TC CS TC CC C=C C

+ +C C+ +C CC CS TC C+ +C CS TC C

2

(Eq. 2)where C

S is the primary

switch capacitance and CT

is the transformer primary capacitance. Interval 2 equals T

ON + T

R, where T

R

is one-half of a resonant interval:

fL C

RE RE fREf S S M RL CM RL C

=L C×L CL CM RL C×L CM RL C

1

2π

Power Electronics Technology October 2005 www.powerelectronics.com October 2005 www.powerelectronics.com40

FORWARD CONVERTERS

Fig. 3. Resonant-reset forward converter with an input range of ground to –48 VOUT

Resonant-reset forward converter with an input range of ground to –48 VOUT

Resonant-reset forward converter with an input range of ground to –48 V (36 V to 56 V) and output range 4 V to 18 V.OUT

(36 V to 56 V) and output range 4 V to 18 V.OUT

T LT L CR MR MT LR MT LT LR MT L R= ×T L= ×T LT L= ×T LR M= ×R MT LR MT L= ×T LR MT LT LR MT L= ×T LR MT LR MπR MT LR MT LπT LR MT LT L= ×T LπT L= ×T LT LR MT L= ×T LR MT LπT LR MT L= ×T LR MT L (Eq. 4)

The external capacitance CR charges from zero to a peak

R charges from zero to a peak

R

value of:

IL

CM

R

2

during this interval, and then discharges back to zero. The magnetizing current I

1 at the end of the interval should

therefore equal –I2. The drain-to-source voltage (V

DS) on

the primary switch Q1 at the end of this interval is VIN

, but reaches a peak of:

halfway through Interval 2.V

IN +

halfway through Interval 2.I+ I+

L halfway through Interval 2.L halfway through Interval 2.

CM

halfway through Interval 2.M

halfway through Interval 2.

R

2

halfway through Interval 2. halfway through Interval 2.

halfway through Interval 2. halfway through Interval 2.

Interval 3. During this interval, diodes DR and DF are both on, and the primary switch is off (Fig. 2c). Voltage across the transformer primary is held to zero by the refl ected virtual short across diode DF, and the magnetizing current is held to -I

2 for the entire interval. The end of Interval 3

defi nes the end of a switching cycle, and because the circuit is at steady state, the current I

1 equals -I

2. Substituting for I

1

in Eq. 1, we see that the primary magnetizing current at the start of each switching cycle is:

(Eq. 5) (Eq. 5)I (Eq. 5)I (Eq. 5)L

(Eq. 5)L

(Eq. 5) (Eq. 5)IN (Eq. 5) (Eq. 5)ON (Eq. 5)M

(Eq. 5)1 (Eq. 5)2

(Eq. 5)2

(Eq. 5) (Eq. 5)= (Eq. 5)( )

(Eq. 5)( )

(Eq. 5)( )

(Eq. 5)( )

(Eq. 5)V T( )V TIN( )IN (Eq. 5)IN (Eq. 5)

( ) (Eq. 5)IN (Eq. 5)

V TINV T( )V TINV TON( )ON (Eq. 5)ON (Eq. 5)( )

(Eq. 5)ON (Eq. 5)V TONV T( )V TONV TV T×V T( )V T×V T

During the entirety of Interval 3, the voltage across the transformer primary is held at 0 V, so the primary switch voltage VDS remains at VIN. Note that at the end of TS, I2≠I1

is possible if π L C TM RL CM RL C RTRT× >L C× >L CM R× >M RL CM RL C× >L CM RL C . In that case, a full half-cycle of resonance has not been completed before the next switching cycle begins, and therefore the voltage across the primary switch exceeds V

IN at the start of each switching cycle. That

condition increases the switching loss.

Transient OperationTransient stresses on the primary switch and secondary

output diodes can vary greatly depending on the type of controller used in the application. If the design is not optimal, transients can cause failure in the primary switches or the secondary diodes.

Consider operation with a current-mode PWM controller. Initially, the power supply operates at no-load and high-line voltage. A load transient is applied (minimum load to full load), which causes an immediate duty-cycle step to maximum duty cycle. In turn, that event causes a large increase in the transformer’s magnetizing current and may saturate the transformer unless its design accounted for such transients. The resonant-reset voltage is much higher than that during steady-state operation and may cause failure in the forward diode or the primary switch.

To combat this problem, we introduce a volt-sec clamp. Consider the controller above with a maximum duty-cycle clamp that is inversely proportional to the input voltage. That arrangement limits the maximum fl ux excursion along the B-H loop of the transformer during a transient, which allows the use of a smaller transformer. Transient-voltage stress on the forward diode and the primary switch is

Primary PWMControl CircuitVVIN

-48 VVOUTOUTOUT

1N4148 WD20D20D20

757575

NDRVNDRVNDRVNDRV R49R491000 pF1000 pF1000 pF1000 pF

C53C53C53

-48 -48 VVOUT

.1.1 �F,F, 16 V

C41C41C41 VVVCC

-48 -48 -48 VVOUT

Q9Q9Q9Q9Q9Q9CMLCMLT3946ET3946ET3946ECMLT3946ECML

R5122

T4T4T4

PO368

11

2222

3333

444444

6677

88

9

1034

1 121212

15T15T

15T15T

19T19T

6T6T

3T3T

D23

T5 PWRAMP_TRNT5 PWRAMP_TRNT5 PWRAMP_TRNT5 PWRAMP_TRNT5 PWRAMP_TRNT5 PWRAMP_TRNSS

ISENSE Circuit

-48 VOUTOUT

-48 VVOUTOUT

PAO184

NDRVNDRVC40C40C40C40C40

11

88

T3

0.1 �F, 16 V

R37R37

22220.1 �F. 16 V

44

55

C42C42GateGateGate

R40R4010 10 k�

D17D17D17D17D17D17D17B0520B0520B0520

1

2

VCCVCC

/OUT/OUT

GND

PS9121

U9U9

AN

CA

44

5

33IN4148 IN4148 W

C640.1 �FFFFFF

-48 VOUT D24D24D24D24D24

R59R59R59R59R59R594.99 4.99 k��

REG5REG5REG5REG5

SOURCEQSOURCEQ9R60R60

.47

Secondary VSENSE and Feedback and Control VREREFF

D22D22D22

1N4148 1N4148 1N4148 WGatGatGate

1515151515 R62R62R62R62R62R62R62R62R62R62Q1Q15INDS351ANINDS351ANINDS351AN

D21D21D21D21

1N4148 1N4148 1N4148 W

1N41

48

1N41

48

1N41

48 WWW

R52R52R52R52R52R522222 Si3440DVSi3440DVSi3440DVSi3440DVSi3440DV

Q1Q1Q1Q1Q1Q1Q100C54C54C54C54

100

pF ,

200

100

pF ,

200

100

pF ,

200

100

pF ,

200

100

pF ,

200

VV

Q1Q1Q1Q1Q1Q1Q1Q1Q1Q1Q111Si3458DVSi3458DVSi3458DVSi3458DVSi3458DVSi3458DVSi3458DV

L4L4L4 47���H

474747 R53R53R53 C56220 pF220 pF, 100 , 100 220 pF, 100 220 pF220 pF, 100 220 pF VV

C552.2 nF2.2 nF2.2 nF, 250 2.2 nF, 250 2.2 nF Vaccc

-48 -48 VVOUT

Q1Q1Q1Q1Q1Q144FQD4N25FQD4N25FQD4N25

4.7 4.7 �F, 25 VV

4.7 4.7 �F, 25 VV 4.7 4.7 �F, 25 VV

C59C59C59 C60C60C60C60 C61C61C61C61 C62C62C620.1 0.1 0.1 0.1 �F, 16 V

VOUT

www.powerelectronics.com Power Electronics Technology October 2005www.powerelectronics.com Power Electronics Technology 41

signifi cantly less, but is still higher than during steady-state operation.

Now consider the operation of this converter type with a very light load using diodes for rectifi cation. Magnetizing current is very close to zero during this mode of operation, and the duty cycle is low. If we now apply a load transient (from no load to full load), the duty cycle immediately increases to the maximum value allowed by the adaptive duty-cycle clamp. Before application of the transient, the magnetizing current is zero. The transient peak duty cycle at high-line voltage is:

V D

VINV DINV DMAXtr

INVINVmiV DmiV DnV DnV D

max

V D×V D

where VINmin

is the low-line input voltage, DMAXtr

is the maximum duty cycle at low-line voltage set by the adaptive duty-cycle clamp, and V

INmax is the input voltage at high-line

INmax is the input voltage at high-line

INmax

voltage. When a transient occurs, the magnetizing current increases from zero to:

V D

L fINV DINV DMAXtr

M SL fM SL fmiV DmiV DnV DnV DV D×V D

L f×L fL fM SL f×L fM SL f

in the fi rst switch-on cycle after the transient, where LM

is the primary magnetizing inductance and f

Sthe primary magnetizing inductance and f

Sthe primary magnetizing inductance and f is the switching frequency. After the switch turns off, the magnetizing current reverses in a sinusoidal fashion set by the magnetizing inductance L

M and capacitance C

R. Peak voltage on the

switch is:

V VV D

L f

L

CP TV VP TV VR IV VR IV V NINV DINV DMAXtr

M SL fM SL fM

R

maP TmaP TV VP TV VmaV VP TV Vx mV Vx mV VP Tx mP TV VP TV Vx mV VP TV VR Ix mR IV VR IV Vx mV VR IV V Nx mN axmiV DmiV DnV DnV D

= +V V= +V VR I= +R IV VR IV V= +V VR IV V N= +Nx m= +x mR Ix mR I= +R Ix mR IV VR IV Vx mV VR IV V= +V VR IV Vx mV VR IV V Nx mN= +Nx mN ax= +ax

V D×V D

L f×L fL fM SL f×L fM SL f (Eq. 6)

For steady-state operation at full-load and high-line voltage, the peak steady-state voltage on the switch is:

(Eq. 7) (Eq. 7) (Eq. 7)V V (Eq. 7)V V (Eq. 7)V D

L f (Eq. 7)

L f (Eq. 7)

L

C (Eq. 7)

C (Eq. 7) (Eq. 7)P S (Eq. 7) (Eq. 7)V V (Eq. 7)P S (Eq. 7)V V (Eq. 7) (Eq. 7)IN (Eq. 7)

IN (Eq. 7)

IN (Eq. 7)

V DINV DMAXs (Eq. 7)

MAXs (Eq. 7)

M SL fM SL fM

(Eq. 7)M

(Eq. 7)R

(Eq. 7)P S (Eq. 7)ma (Eq. 7)P S (Eq. 7) (Eq. 7)V V (Eq. 7)P S (Eq. 7)V V (Eq. 7)ma (Eq. 7)V V (Eq. 7)P S (Eq. 7)V V (Eq. 7) (Eq. 7)x m (Eq. 7) (Eq. 7)V V (Eq. 7)x m (Eq. 7)V V (Eq. 7) (Eq. 7)P S (Eq. 7)x m (Eq. 7)P S (Eq. 7) (Eq. 7)V V (Eq. 7)P S (Eq. 7)V V (Eq. 7)x m (Eq. 7)V V (Eq. 7)P S (Eq. 7)V V (Eq. 7) (Eq. 7)IN (Eq. 7)x m (Eq. 7)IN (Eq. 7) (Eq. 7)V V (Eq. 7)IN (Eq. 7)V V (Eq. 7)x m (Eq. 7)V V (Eq. 7)IN (Eq. 7)V V (Eq. 7) (Eq. 7)ax (Eq. 7)mi

(Eq. 7)mi

(Eq. 7)V DmiV Dn

(Eq. 7)n

(Eq. 7)V DnV D

= + (Eq. 7)= + (Eq. 7)V V= +V V (Eq. 7)V V (Eq. 7)= + (Eq. 7)V V (Eq. 7) (Eq. 7)IN (Eq. 7)= + (Eq. 7)IN (Eq. 7) (Eq. 7)V V (Eq. 7)IN (Eq. 7)V V (Eq. 7)= + (Eq. 7)V V (Eq. 7)IN (Eq. 7)V V (Eq. 7) (Eq. 7)x m (Eq. 7)= + (Eq. 7)x m (Eq. 7) (Eq. 7)V V (Eq. 7)x m (Eq. 7)V V (Eq. 7)= + (Eq. 7)V V (Eq. 7)x m (Eq. 7)V V (Eq. 7) (Eq. 7)IN (Eq. 7)x m (Eq. 7)IN (Eq. 7)= + (Eq. 7)IN (Eq. 7)x m (Eq. 7)IN (Eq. 7) (Eq. 7)V V (Eq. 7)IN (Eq. 7)V V (Eq. 7)x m (Eq. 7)V V (Eq. 7)IN (Eq. 7)V V (Eq. 7)= + (Eq. 7)V V (Eq. 7)IN (Eq. 7)V V (Eq. 7)x m (Eq. 7)V V (Eq. 7)IN (Eq. 7)V V (Eq. 7) (Eq. 7)ax (Eq. 7)= + (Eq. 7)ax (Eq. 7)V D×V D

L f×L f (Eq. 7)

L f (Eq. 7)× (Eq. 7)

L f (Eq. 7)

L fM SL f×L fM SL f2 (Eq. 7)

2 (Eq. 7)

where DMAXs

is the steady-state duty cycle at full load and low line. In practical applications, we try to set D

MAXtr slightly

higher than DMAXs

. We also see that the peak transient reverse voltage on the diode DF is more than twice as high as the peak steady-state reverse voltage with this type of pulse-width modulated (PWM) controller. For PWM controllers without the volt-sec clamp, the transient voltage can be even higher.

If the circuit includes synchronous rectifi ers, the inductor current does not become discontinuous, and the magnetizing currents at light load and at full load are almost the same. For PWM current-mode controllers with volt-sec clamps, the transient-voltage stress on the primary switch and the secondary diode DF is closer to the peak steady-state voltage stress.

The behavior of voltage-mode controllers is similar to that of current-mode PWM controllers. Again, the use of an adaptive volt-sec clamp can reduce stress. These converter types often include a duty-cycle soft-start that ramps up the

duty cycle, controlling any buildup of magnetizing energy while alleviating voltage stress.

Design ExampleThe working power supply of Fig. 3 accepts dc input

voltages in the range 36 V to 56 V, and produces an isolated variable output voltage in the range of 4 V to 18 V, controlled by an adjustable external reference. The maximum output current is 0.4 A and the switching frequency is 500 kHz.

The resonant-reset forward converter is most suitable for this design because it lets us maximize the duty cycle. That capability is necessary if the output voltage is to be properly controlled from high levels all the way down to 4 V. Otherwise, the PWM controller’s minimum on time is a limitation that could introduce problems. Synchronous rectifi ers should be included to maximize effi ciency and enable the PWM controller to control the output voltage down to 4 V at light loads. The current-mode PWM controller shown also includes an adaptive volt-sec clamp.

Because the power supply must turn on at 36 V and provide full power at 36 V, we set its turn-on point at 34.2 V. That value of turn-on voltage includes a 5% margin to compensate for component tolerances. We then set the maximum duty cycle corresponding to the turn-on point (set by the adaptive duty cycle) at 75%. That leaves 25% of

FORWARD CONVERTERS

Power Electronics Technology October 2005 www.powerelectronics.com October 2005 www.powerelectronics.com42

FORWARD CONVERTERS

Fig. 4. From Fig. 3, VDS

From Fig. 3, VDS

From Fig. 3, V on Q14 at an input of 48 Vdc, with output voltage at 4 V (a) and at 8 V (b).

the switching time available for resetting the transformer at the converter’s lowest operating voltage.

At the lowest operating voltage, the maximum-available reset time for the transformer is:

(Eq. 8) (Eq. 8)T (Eq. 8)T (Eq. 8)

f (Eq. 8)

f (Eq. 8) (Eq. 8)R (Eq. 8) (Eq. 8)T (Eq. 8)R (Eq. 8)T (Eq. 8) (Eq. 8)MA (Eq. 8) (Eq. 8)X (Eq. 8) (Eq. 8)MA (Eq. 8)X (Eq. 8)MA (Eq. 8)

SfSf (Eq. 8)= (Eq. 8)

( ) ( ) (Eq. 8)

( ) (Eq. 8)

D( )D D ( ) D MA( )MA (Eq. 8)MA (Eq. 8)

( ) (Eq. 8)MA (Eq. 8)X( )X (Eq. 8)X (Eq. 8)

( ) (Eq. 8)X (Eq. 8)MAXMA( )MAXMA (Eq. 8)MA (Eq. 8)X (Eq. 8)MA (Eq. 8)

( ) (Eq. 8)MA (Eq. 8)X (Eq. 8)MA (Eq. 8)

−( )−( )1( ) ( ) 1 ( )

where D

MAX=0.75 and f

S=0.75 and f

S=0.75 and f =5105. These values yield

a reset time of 0.5 s. To minimize switching loss, the magnetizing current should complete one half-cycle of sinusoidal “resonant ringing” as given by Eq. 4. Therefore, sinusoidal “resonant ringing” as given by Eq. 4. Therefore, π L CM RL CM RL C× =L C× =L CM R× =M RL CM RL C× =L CM RL C × −0 5 10 6. ×. ×0 5. 0 5 10. 10 sec , and the peak steady-state voltage stress on the primary switch (obtained by substituting values in Eq. 7) is 217.2 V. Thus, for this design we choose a switch rated at 250 V.

Primary-to-secondary turns ratio for the transformer is: n

V D V D

VINV DINV DMAXMAXMA

OUVOUV T

≤V D×V D V D × V D

miV DmiV DnV DnV D(Eq. 9)

We choose a transformer with an EFD15 core of 3F3 material, and obtain n 1.35 by substituting values in Eq. 9. The actual primary turns (30) and secondary turns (24) yield a turns ratio of 1.25. The magnetizing inductance for this transformer, wound using ungapped cores, is 702 H ± 25%. Tolerance in the magnetizing inductance could produce a tolerance of (+11%)/(–13.4%) in the transformer’s self-resonant frequency, not accounting for tolerance in the total capacitance appearing across the primary in the actual circuit. The measured self-resonant frequency of a sample transformer was lower than 1 MHz.

We must guarantee that the actual circuit’s demagnetizing self-resonant frequency is higher than f

Sself-resonant frequency is higher than f

Sself-resonant frequency is higher than f /(1-D

MAX). We

therefore gap the core, both to reduce the transformer’s measured self-resonant frequency and to reduce the variation in magnetizing inductance. Using a gapped core with A

lmagnetizing inductance. Using a gapped core with A

lmagnetizing inductance. Using a gapped core with A tolerance

l tolerance

l

of 10% yields a magnetizing inductance of 144 H.The self-resonant frequency measured for the new trans-

former sample is 4 MHz, and the transformer capacitance calculated from the expression for self-resonant frequency

is 11 pF. Based on the available reset time, the maximum allowable primary capacitance is 176 pF. That value allows a maximum of 165 pF for the sum of switch capacitance and refl ected diode capacitance (C

R). Because MOSFET

capacitance is not easily determined, we must build the circuit and adjust the value of added capacitance across the synchronous MOSFET (QR) to get the appropriate reset time. In the actual power supply, the added capacitance across MOSFET QR is 100 pF.

The output inductor and capacitor are chosen to optimize effi ciency and ensure compliance with the output-ripple specifi cation. Thus, the inductor value is 47 H, and C

O is

formed by connecting three ceramic capacitors in parallel, each rated 4.7 F and 25 V.

For the primary MOSFET Q1 (voltage rating of 250 V), we choose an FQD4N25 from Fairchild Semiconductor (South Portland, Maine) for its low inherent capacitance and low on-resistance. This MOSFET also minimizes the gate-drive loss, conduction loss and switching loss.

Peak stress on the synchronous rectifi er QR is:

(Eq. 10) (Eq. 10)V (Eq. 10)V (Eq. 10)D V

QR (Eq. 10)QR (Eq. 10) (Eq. 10)V (Eq. 10)QR (Eq. 10)V (Eq. 10)MA (Eq. 10)MA (Eq. 10)D VMAD VX I (Eq. 10)X I (Eq. 10)D VX ID VMAX IMA (Eq. 10)MA (Eq. 10)X I (Eq. 10)MA (Eq. 10)D VMAD VX ID VMAD V N (Eq. 10)N (Eq. 10)

MAXMAXMA

≥ (Eq. 10)≥ (Eq. 10)× ×D V× ×D VX I× ×X ID VX ID V× ×D VX ID V N× ×N mi (Eq. 10)mi (Eq. 10)× ×mi× ×n (Eq. 10)n (Eq. 10)× ×n× ×( )

(Eq. 10)( )

(Eq. 10)D( )D

(Eq. 10)D

(Eq. 10)( )

(Eq. 10)D

(Eq. 10)MA( )MAX( )XMAXMA( )MAXMA−( )−

π2 1

(Eq. 10)2 1

(Eq. 10)( )2 1( )

(Eq. 10)( )

(Eq. 10)2 1

(Eq. 10)( )

(Eq. 10)2 1n2 1

(Eq. 10)2 1

(Eq. 10)n

(Eq. 10)2 1

(Eq. 10)A2 1A2 1

where nA is the power transformer’s actual primary-to-

secondary turns ratio. In this case, nA is 1.25 and the calculated

A is 1.25 and the calculated

A

value of VQR

value of VQR

value of V is 122 V. Therefore, we choose a 150-V MOSFET QR

is 122 V. Therefore, we choose a 150-V MOSFET QR

for QR. The peak voltage stress on the freewheeling MOSFET QF is:

(Eq. 11) (Eq. 11) V (Eq. 11) V (Eq. 11) V

n (Eq. 11)

n (Eq. 11) QF (Eq. 11) QF (Eq. 11) (Eq. 11) V (Eq. 11) QF (Eq. 11) V (Eq. 11) IN (Eq. 11) IN (Eq. 11)

VINV

A

≥ (Eq. 11) ≥ (Eq. 11) ma (Eq. 11) ma (Eq. 11) x (Eq. 11) x (Eq. 11)

where nA is 1.25 and V

INmax is 56 V. The calculated value is

INmax is 56 V. The calculated value is

INmax

44.8 V, so for QF we choose a MOSFET rated at 60 V. (The control circuit and synchronous MOSFET drives are shown in Fig. 3 but not discussed further.)

Experimental ResultsFigs. 4 and 5 show voltage waveforms on the primary

MOSFET of Fig. 3 at different input voltages and various

www.powerelectronics.com Power Electronics Technology October 2005www.powerelectronics.com Power Electronics Technology 43

output voltages, with an output load of 400 mA. The drain-voltage waveforms clearly show that the resonant-reset voltage does not vary with line voltage, but is proportional to the output voltage. Peak voltage on the primary MOSFET is equal to the input voltage plus the resonant-reset voltage.

We conclude that resonant-reset forward converters are quite suitable for power supplies operating from wide-range

dc-voltage inputs. They also are suitable for applications requiring a wide range of adjustable output voltage. In designing resonant-reset forward converters, you should take care to minimize the stress of transient voltages on the devices (the use of synchronous rectifi cation reduces transient-voltage stress on the power semiconductors). For optimum performance, you also should choose an appropriate controller. PETech

Kooler Inductors

P.O. Box 11422 • Pittsburgh, PA 15238-0422Phone 412.696.1333 • Fax 412.696.03331-800-245-3984email: magnetics@spang.com www.mag-inc.com

Inductors made from Magnetics’® Kool Mµ® E coresrun cooler than those made with gapped ferritecores. Eddy currents, caused by the fringing fluxacross the discrete air gaps of a gapped ferrite, canlead to excessive heat due to heavy copper losses.The distributed air gaps inherent in Kool Mµ canprovide a much cooler inductor.

Kool Mµ E cores are available in many industrystandard sizes. Magnetics now offers cores in 14 sizes (from 12 mm to 80 mm) and fourpermeabilities (26µ, 40µ, 60µ, and 90µ).New sizes are being added. Standard bobbins are also available.

If you are using gapped ferrite E cores for inductorapplications, see what Kool Mµ E cores can do foryou. You may even be able to reduce core size inaddition to having a cooler unit. Productionquantities are now in stock. For more information,contact Magnetics.

New Sizes Available!New Sizes Available!

Fig. 5. From Fig. 3, output voltage at 18 V, with VDS

From Fig. 3, output voltage at 18 V, with VDS

From Fig. 3, output voltage at 18 V, with V on Q14 at an input of 36 Vdc (a) and 56 Vdc (b).

FORWARD CONVERTERS