Designing at 2x nanometers Some New Problems Appear & Some Old Ones Remain
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1 © Synopsys 2012 Designing At 2x Nanometers Some New Problems Appear, and Some Old Ones Remain Marco Casale-Rossi Synopsys, Inc.
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Transcript of Designing at 2x nanometers Some New Problems Appear & Some Old Ones Remain
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© Synopsys 2012
Designing At 2x Nanometers
Some New Problems Appear, and�
Some Old Ones Remain
Marco Casale-Rossi
Synopsys, Inc.
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© Synopsys 2012
Designing At 2x NanometersWhat Are the Key Areas of Focus?
(1) SION Dielectric/Polysilicon Gate; (2) High-k Dielectric/Metal Gate; (3) Planar CMOS(1) SION Dielectric/Polysilicon Gate; (2) High-k Dielectric/Metal Gate; (3) Planar CMOS; Source: ITRS 2011, AMSL 2010, IBS 2008
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More Complexity ChallengesSheer Complexity Remains the #1 Challenge
Intel CE4200
45 nanometers (2010)
96mm2, ~ 300M transistors
7-9W
Intel CE3100, 90 nanometers (2008)
208mm2, 150M transistors, 10W
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• The Initial “sub-system”
– Fast synthesis, floorplanning, and placement
– Used for design exploration, constraints clean-up, feasibility
– Findings – e.g. floorplan – will be “shared” with back-end
• The Full “sub-system”
– Takes over once “initial” done
– Full synthesis and place & route
– Heavy use of special “correction” techniques
Gigascale Design Implementation Evolving Into Two, Closely Connected “Sub-Systems”
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RTL Exploration~ 6X Faster Than RTL Synthesis
Slack Distribution Comparison, Correlation ±8%
Slack Histogram Floorplan
-1.3 -0.95 -0.55 -0.15 0.2 0.55 0.95 1.3 1.7 2.1
DC-E DC-T DC-E w/ Floorplan Information
Source: Synopsys Research 2011
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Look-Ahead & Physical GuidanceSame Critical Paths, Correlation ±5%
Synthesis Place & Route
Source: Synopsys Research 2011
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Gigascale Design ImplementationConstraints Analysis, Design Exploration & Block Feasibility
Feasibility Stage Implementation Stage
Design Data
Dirty Clean Final
Chip
Level
Block
Level
Top AssemblyDesign Exploration Design Planning
Block Feasibility Block Implementation
• Final Block Implementation
• Timing and Congestion Clean
• Clean Block Level SDC
• Final Block Level Floorplan
• Initial Floorplan Partitions
• Clean Top Level Routing
• Clean Top Level SDC
• Final Top Level Floorplan
• Block Level Floorplan
• Timing Budgets
• Final Chip Implementation
• Blocks Modeled as ILM/ETM
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Design ExplorationHeading Into the Right Direction ?
Standard Placement (Fully Legalized)
Several Hours
Exploration Placement (Coarser)
27M Instances in 1 Hour
Source: Fujitsu, SNUG Japan 2010
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Block Feasibility45 Nanometers, 4M Instances
0
100
200
10
15
20
25
30
No false paths or multi-cycle paths
identified
17 false paths not identified
17 false paths + 3 multicycle paths not
identified
All false paths and multi-cycle paths
identified
Perf
orm
an
ce (
MH
z)
Ru
ntim
e (H
ou
rs)
FeasibilityRuntime
ImplementationRuntime
Feasibility Performance
ImplementationPerformance
Feasibility
2X Faster Than
Implementation
Feasibility
QOR Same As
Implementation
Implementation
Results Improve w/
Cleaner SDC
Feasibility Runtime
Independent of SDC
Dirtiness
Source: IDM, 2010
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© Synopsys 2012
• Until now :
– Mostly “preserve” the gates
– “Change” placement, and/or routing to close timing, power, L
• Very, very time consuming, and
• Leads to a number of iterations
• In the future :
– Once the objective is “within reach” L
– “Hold” placement and routing
– Systematically “change” the gates
• Same footprint, different timing, power, temperature inversion
point, etc.
• The richness of the library is fundamentally important
Gigascale Design ImplementationLonger Term Evolution
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1st SignOff ECO1 ECO2
Total Hold Slack (ps) 19558 102 34
No. Hold Violations 2382 49 6
WNS (ps) 116 6 15
1
10
100
1000
10000
100000
1000000
TN
S, N
o. o
f V
iola
tio
ns,
WN
SECO Flow32 Nanometers, ~ 3M Instances, ~ 300 Macro Blocks
40 Scenarios, Runtime < 8 Hours, 99% Hold Fix Rate
Source: STMicroelectronics, PrimeTime SIG, 2012
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Leakage = 0.77X, -23%
Leakage Recovery32 Nanometers, ~ 3M Instances, ~ 300 Macro Blocks
Leakage = 1X
Source: Synopsys Research 2011
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X
2X
4X
6X
8X
10X
12X
90 65 45/40 32/28 22/20
Maximum Clock Frequency @ Nominal Voltage, 125°C, 500mW
More Performance ChallengesThe Application Processors Race for “PP&A”
Source: Synopsys Research 2011
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High Speed And Low Power FlowBetter Quality-of-Results, Faster Time-to-Results
Typical flow
HSLP flow
Design-specific
customizationTime
Targets
100%
90%
75%
Faster time-to-results
Typical flow on
standard designsTypical flow on high speed,
low power designs
High speed
and low power
(HSLP) flow
Better quality-of-results
Source: Synopsys Research 2011
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High Speed And Low Power FlowARM Cortex™-A9 MPCore™ Dual Core
80%
90%
100%
110%
Synthesis Placement CTS Routing
Perf
orm
an
ce (%
of
Ta
rget)
Timing Closure Profile
Additional Customization For High Speed
High Speed and Low Power Flow
RM (Baseline) Flow
Source: Global Unichip, SNUG Taiwan 2011
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More Performance ChallengesBesides Digital,� Analog and Mixed-Signal
Digital
Analog & M/S
Source: R. Rutenbar, CMU, ICCAD 2006; H. Hiller, Infineon, DAC 2007
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Much More Than Just InteroperabilityShared Tasks Between Digital and Analog Environments
Source: Synopsys Research 2012
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Analog Pre-RoutingMatched Resistance Routing
Source: Synopsys Research 2012
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Non-planar CMOS
Double patterning
3D-IC
Device
Lithography
Integration
What Else Should We Look At?Three “Revolutions” After Thirty Years of “Evolution”
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The Challenge: Planar CMOSInsufficient Performance, Excessive Power
32 Nanometer Planar Not EnoughB “Headroom”
Source: K. Kuhn, Intel, IDF 2011
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The Solution: Non-Planar CMOSThe First “Revolution”
22 Nanometer Tri-Gate More “Headroom” !!!
Source: K. Kuhn, Intel, IDF 2011
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The SolutionSPICE Simulation, and Parasitic Extraction
Model/Compute Parasitics/Extract
M1
GateContact
Fin FinSource Drain
Source: Synopsys Research 2011
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The Challenge: Single Exposure“Last Pitch With Single Exposure ~ 80 Nanometers�”
We Can Print This,B But We Cannot Print This
Source: M. van den Brink, ASML, ITF 2009; P. Magarshack, STMicroelectronics, 2010
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And Then This!
The Solution: Double PatterningThe Second “Revolution”
We Can Print This,B and This,B
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The SolutionDPT Ready Logic Libraries and Placer
DPT-Aware Placement DPT Compliant Coloring
Source: Synopsys Research 2012
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The SolutionDPT Ready Router and DRC
Source: Synopsys Research 2012
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The Challenge: “> 2D-IC”“More of Moore” Requires “More than Moore”
Memory
“Cube”
(Wide I/O) Memory
“Cube” on Logic
Silicon Interposer
3D Stack
C4
TSV µBump
1 2
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Source: Synopsys Research 2011
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The Solution: 3D-ICThe Third “Revolution”
Source: L. Madden, Xilinx, 2011
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The SolutionSide-by-Side, Passive Silicon Interposer,
Single-Sided (F2F), to Begin with
Source: Synopsys Research 2011
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The SolutionSilicon Interposer with P&G Grid, and
µBumps, TSV, and C4
Source: Synopsys Research 2011
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Leveraging Existing ToolsSilicon Interposer (Detail)
Source: Synopsys Research 2011
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Leveraging Existing ToolsSilicon Interposer (Detail) Routed
Source: Synopsys Research 2011
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© Synopsys 2012
תודהMay 2nd, 2012
Tel Aviv, Israel
