Design, Simulation and Fabrication of · Design, Simulation and Fabrication of ... 4.4 Delay Times...
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Design, Simulation and Fabrication of a Self-Aiigned SiGe Base Heterojunction Bipolar Transistors For Low Power Operation A thesis submitted to the Faculty of Graàuate Studies and Raevfh In partial fulfiIlment of the requirtments for the degree of Master of Engineering in Electronics Ottawa-Carieton Institute for Mectrical and Computer Engineering Department of Electmnics, Faculty of Engineering Carleton University Otîawa, Ontario Canada June 1999 O AA Hussain 1999, Oîiawa, Canada
Transcript of Design, Simulation and Fabrication of · Design, Simulation and Fabrication of ... 4.4 Delay Times...
Design, Simulation and Fabrication of
a Self-Aiigned SiGe Base Heterojunction Bipolar Transistors
For Low Power Operation
A thesis submitted to the
Faculty of Graàuate Studies and R a e v f h
In partial fulfiIlment of the requirtments for the degree of
Master of Engineering
in Electronics
Ottawa-Carieton Institute for Mectrical and Computer Engineering
Department of Electmnics, Faculty of Engineering
Carleton University
Otîawa, Ontario
Canada
June 1999
O AA Hussain 1999, Oîiawa, Canada
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This thesis describes the design, fabrication and electrical characterization of a novel
self-aligned SiGe base heterojunction bipolar transistor optimized for low-power
operation. A theoretical analysis is presented reveahg that the exnitter-base junction
capacitance dominates F, in this operathg regime. Guided by this initiai analytic
modeuing, the device simulator BIPOLE3 was used to optimize doping profiles and other
structurai parameters. A @ed Ge profile with a peak Ge content of 10% was assumecl.
Relatively light base and collecter doping is required to optimize low power performance.
Experimental devices were fabricated by modiving an existing commercial process flow
for silicon BJTs. New process modules were developed for field polysiliwn formation,
SiGe base deposition, and local intercomect formation. The SiGe base was formed by a
UHVKVD process. EIectricai test r d t s on the fmt expeimental devices are very
encouraging. DC characteristics are generally goai, although F, is approxirnately 3096
lower than predicted by BIPOLE3.
Acknowledgements
1 wish to convey sincere and deep appreciation to my thesis supervisor Dr. N.G. Tarr for
his encouragement, support and for many helpful discussions and suggestions during the
course of this work.
1 would also iike to thank the technical staff of the fabrication laboratory at Carleton
University: Mr. Lyaii Bemdt for wafer diffusiodannealing praiessing; Mrs. Carol Adams
for wafer pre-diffusion cleaning: Mr. Christopher Pawlowicz for direct write electron-
beam iithography and etchmg. I would also like to express my gratitude to the professors,
technical staff and students at the department of electronics for their help during the
course of this work Special thanks to Dr. DJ. Walkley for several consultations and help
with difficulties 1 encomterd
Many mernbers of the technical staff at Gemum Corporation certainly deseme
recognition for their help and consultations: Mr. Andrew Cervin-Lawry for his
supervision during the layout of the devices and fabrication; Mrs. Myriam Buchbinder for
her help during fabrication and valuable comments: Dr. J. Kendall for AC measurements
and useful discussions, and Mrs. W. Gustafson for wafer processing. Special thanks goes
to Mr. D. Lynch for his valuable suggestions during the weekly meetings at Gennum.
Most irnportantly, I am deeply indebted to my forbearing wife and children, especially
my daughter Berak and my son Belai during the preparation of this thesis. This work is
dedicated to them.
Finally, I would like to thank, the department of Electronics at Carleton University,
OSAP from the Ministry of Education and Training, Gerinum Corporation of Buriingüm,
Ontario and Micronet for their financial support. 1 extend my thanks to the Canadian
Marconi Company for their bursaries.
Table of Contents
Abstract Acknowledgemcnts Table of Contents List of Figures List of Tables List of Symbols
CHAPTER 1. : INTRODUCTION
1.1 Basics of SiGe HBT Technology 1.2 Objective of the Present Work
CHAPTER 2. : SiGe HBT PHYSICS AND TECHNOLOGY
2.1 Physics of the SiGe HBT 2.2 Growth of SiGe on Si Substrate 2.3 The UHV/CVD Process 2.4 Surface Cleaning 2.5 SiGe Film Growth 2.6 Polycrystalline Silicon 2.7 Transit Times in Bipolar Transistors 2.7.1 One-Dimensional (Vertical) Anaiy sis 2.7.2 Two-Dimensional (Lateral) Analysis
CHAPTER 3, : DEVICE ARCHITECTURE
3.1 Transistor Structures 3.2 Device Layout
CHAPTER 4, : DEVlCE SIMULATIONS AND ANALYSIS
4.1 Introduction 4.2 Electrical Performance Specifications 4.3 Calculation of the Extrinsic Base of the NSA Devices
4.3.1 Model 1 (Overestimates Base Resistance) 4.3.2 Model 2 (Undereshates Base Resistance)
4.4 Delay Times Contributing to the Transition Frequency 4.4.1 Prebinary Calculations 4.4.2 Simulation Results
iv v
vi viii
X
xii
4.4.2.1 Effect of Doping Levels on the Delay Times 4.4.2.1.1 Vertical Analysis 4.4.2.1.2 Lateral Analysis
4.4.2.2 Effect of Transistor Size on the Delay Times 4.4.2.2.1 Vertical Analysis 4.4.2.2-2 Lateral Analysis
4.5 Effect of Doping Levels on the Elecaical Characteristics 4.5.1 Emitter Doping Level 4.5.2 Epitaxial Collecter Doping Level
4.6 Influence of Device Scaling on the Electricai Characteristics 4.7 Simulation Results of an Si-Base Device 4.8 General Tram is tor Characteristics
CHAPTER 5.: DEVICE FABRICATION AND CHARACTERIZATION 69
5.1 Introduction 5.2 Test Wafer Layout 5.3 Short Loop Experirnents 5.4 Field Poly Module 5.5 SiGe Base Deposition Module 5.6 Local Intercomect Module 5.7 Rapid Thermal Emitter Annealing 5.8 Device Characteristics and Discussion
5.8.1 DC Characteristics 5.8.2 AC Characteristics
CHAPTER 6. : CONCLUSIONS AND RECOMMENIDATIONS 96
6.1 Conclusions 6.2 Recomrnendations For Future Work
APPENDIX A. : 102
A. 1 The pn OneSided Step Junction A.2 Depletion Layer Capacitance
APPENDIX B. : 104
B.1 Tables 104
vii
List of Figures
Figure
2.1
2.2
3.1
3.2
3.3
3-4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5.1
5.2
5.3
a:Energy band diagrams of a Si bipolar transistor (solid line)
and SiGe HBT (dotîed Line). b:Doping profde of Ge across
the base region
Representation of the strained and relaxed structures of SiGe
on Si substrate
Cross-sectional view of the self-aiigned HBT structure
Cross-sectionai view of the non-self aligned HBT structure
Self-aligned HBT with twO base contacts
Non-self aligned HBT with two base contacts
Extrinsic base cross-section
Model 1 for the NSA device
Model 2 for the NSA device
Typical simulated impurity profile for SAlX and NSAlX of
SiGe HBT
Typical simulated Gurnmel plots of base and coiiector currents
for SA1 X and NSAlX of SiGe HBT
Typical simulated &-Va characteristics for SAlX and NSAlX
of SiGe HBT
Simulated F, and Fm as a function of I, for SiGe HBT
Schematic cross-section of the field poly process sequene
of the SiGe HBT
Schematic cross-section of the SiGe process sequence
of the SiGe HBT
Schematic cross-section of the LOC-DIT proces sequence
of the SiGe HBT
vüi
Experimental collector and base curtents versus base-emitter
bias for the SiGe HBT 91
Experimental coiiector current versus esnitter-collecter bias
for different base c m n t s for the SiGe HBT 92
Measured transition frequency versus collector currents for
a SiGe HBT 94
Table
4.1
4.2
5.1
5.2
B.l Partl
B. 1 Part2
B.2 Partl
B.2 Part2
B.3 fart1
B.3 Part2
Description
Mask dimensions of the vertical SiGe riBTs
Effect of doping Ievels on the delay times obtained from
vertical anaiysis
Effect of doping leveis on the delay times obtained from
lateral andysis
Effect of a tramistor size on the delay h e s obtained from
vertical anaiysis
Effect of a transistor size on the delay tirnes obtained from
lateral analysis
Heavy emitter doping
Light emitîer doping
Light emitter doping, light EPI doping
Heavy emitîer doping, Iight EPI doping
Delay times for Si-base devices obtauled from vertical
andysis
Delay thes for Si-base devices obtained from lateral
analysis
Summary of the field poly results
Variation of sheet resistance with temperature
Heavy emitter doping, various geometries
Heavy ernitîer doping, various geometries
Light ernitter doping, various geometries
Light emitter doping, various geometries
Light ernitter doping, Iight EPI doping, various geometries
Light emitter doping, Light EPI doping, various geometries
Heavy ernitter doping, light EPI, various geometries
List of symbols
Base-cokctor junction area
Emitter-base junction area
CoUector-emitter breakdown voltage
Diffusion capacitance
Base-coilector junction capacitance
Emitter-base junction capacitance
Substrate capacitance
Electron diffusion constant in the base
Barrier height at a heterojunction
Band gap grading across the neutral base region
Band gap reduction at the emitter-base depietion edge
Band gap reduction at the base-coUector depletion edge
Epitaxial coiiector layer
Grading coefficient
Maximum osciUation frequency
Peak value of the maximum oscillation frequency
Transition tkequency
Peak value of the transition frequency
Transition frequency for Si-base
Transition frequency for SiGe-base
Grading factor
Tramconductance
Base current
Colleetor current
Value of wiiector current giving highest F,
Integrated circuits
Coiiector current density
Boltzmann constant
Ionized acceptor dopant concentration
Effective density of states in conduction band
Ionized donor dopant concentration
Intrinsic canier concentration
Effective density of states in valence band
Electronic charge
Total base resistance
Intrinsic base resistance
Extrinsic base resistance
Undepieted dector resistor
Vertical resistance under the collecter contact
Diffusion resistance
Sheet resistance
Absolute temperature
Epitaxial layer thickness
Delay time due to sidewail injection electron concentration into the base
region outside the active base region
Smail signal delay t h e due to integral of rninoriy carrier charge in the
whole of active region
Base-transit time
Transit t h e for Si-base
Transit time for SiGe-base
Time constant for charging the base-coiiector capaciwce through the
collecter resistance
Basecoiiector junction capacitance charging t h e
Neutrai emitter region charging t h e
xiii
Emitter-base junction chargkg time
Emitter to collecter transit time
Delay time due to minority carrier charge in the emitter-base space charge
layer
Oxide thickness
Heatpulse preset temperatwe
Delay time due to free camer charge in emitter-base space-charge layer
Delay the due to C,= and total series resistance
Delay time due to (kT/q)(CE+CJc)
Collector space charge layer transit cime
Delay tirne due to (C, u p ) Total delay tirne in a tarodimensional analysis
W afer temperame
b l y voltage
Early voltage for Si-base
Early voltage for SiGe-base
Base-collecter voltage
Bdt-in voltage at the base-coilector region
Built-in voltage at the emiüer-base region
Themal voltage
Collecter-emitter voltage
Emitîer-base voltage
Saturateci carrier velocity
Emi tter deph
Collector depletion width
Width of the exnitter-base junction
Metallurigical junction depth at the emitter-base region
Metallurigical juaction depth at the base-collecter region
Permittivity of free space
xiv
Penniîtivity of siiicon
Current gain
Ratio of the position-average density of States product (N, N,) berneen
SiGe-base and Si-base transistors
Base-collecter junction coefficient constant
Emitser-base junction coeffkient wnstant
Wafer sheet resistance
Ratio of the position-average minority carrier mobility in the base of a
SiGe HBT compared to a Si BJT
CHAPTER 1
INTRODUCTION
1.1 Basics of SiGe HBT TechnoIogy
Silicon bipolar transistor technology is abwt a haif century old. For the past five decads,
the speed of silicon bipolar junction transistors (BJTs) has gradually increased as a result
of the decrease in their dimensions. Whether siliwn devices have reached theoretical
lirnits or not, the introduction of SiGe devices illustrates a discontinuity on the path to
faster siiicon [Il. Scientists and engineers at severai institutions [l-31 have been studying
new semiconductor materials for many years. One direction in these studies was to add
srna11 amounts of germanium (Ge) to silicon in order to create a new stable aUoy (Si,.,
G c , where x represents the mole fraction, often writîen SiGe for simplicity). This
material is of considerable interest as it offers the potential to deiiver impmved
performance compared to the conventional si!kru! divices.
The introduction of SiGe into conventional Si technology has attracted much attention
because of the potential to obtain high device perfomance at low cost for many
applications such as optical and WireLess communication system, I d area networks and
high speed digital circuits. High transition frequencies, F,, high maximum oscillation
frequencies Fm and high current gains can be achieved using SiGe heterojunction bipoiar
transistors (KBTs) raîher than Si BJTs. Additional benefits such as bigher Early voltages
and lower sheet resistance can also be achieved when SiGe is introduced in the base of
the transistor. These high performance devices are ideal for meeting the requkements of
the high-speed analog circuits required for RF and microwave applications [4,5].
Several groups have reported the transistor transition frequencies of SiGe-HBTs in excess
of 100 GHz [6-81 with graded, narrow bases. Firnhermote, the maximum oscillation
frequency was increased to 160 GHz by minimizing both the total base resistance RB and
base-coLlector junction capacitance C,, [9]. Minimizing RB and C , is crucial to
mawimizing the Fm. Until recently, these performance levels were only achievable with
the most advanced GaAs technology.
Transistors that are built in silicon gexmanium can run substantiaily faster than their pure
silicon counterparts, and can be made at lower cost with greater opportunity for
integration with standard Si processes than can high speed GaAs devices. GalLium
arsenide processes exhibit excellent performance characteristics but suffer fmm higher
pricing resulting from higher wafer costs, plus costs for epitaxy material and low device
yields. SiGe opens the door to merging logic and RF on one die. and thus cornpetes
favorably with GaAs in performance across the range of frequencies where GaAs is now
dominant. That merger stems from SiGe's ability to let bipolar and CMOS coexist on a
single silicon wafer [IO].
Adding Ge to the base of the transistor influences the band gap energy, band
2
discontinuities, scattering processes d electron-hole recombination processes. Ge
reduces the band gap, lowering the barrier for electron injection into the base, which in
tum aliows heavier base doping to be used, lowering base resistance. Band gap grading
introduces a drift field to aid the transport of electrons across the neutrai base. The
electron mobility in SiGe is about two to three times higher than that in pure Si, allowing
more rapid electron transport across the base.
SiGe has the same crystallographic stn~cture as Si [3] but its latrice constant is larger by
about 4% for pure Ge. When SiGe is grown epitaxiaily on Si substrate in such a way that
the film and substrate adopt a cornmon lattice constant while maintaining perfect
crystailinity across the growth interface* the composite film undergoes strain. One
immediate concem is the effect of s h e d - l a y e r epitaxy . For any given Ge content, there
is a critical thickness of SiGe above which starts to relax toward its bulk latîice spacing
and can generate defects which can devastate device perfomance. One possible solution
to this problem is to prepare SiGe using ultra-high vacuum chernical vapor deposition
UHV/CVD at relatively low temperature. This technique, which was developed by
Meyerson and his coworkers (11 at IBM, was pmven to be a successful technique to
overcoming the above mentioned difficulties. This issue and related ones will be
addressed in chapter two.
1.2 Objective of the -nt Work
The main objective of this thesis is the design, simulation and fabrication of a vertical
3
SiGe base heterojunction bipolar transistor optimized for low power operation. While
previous researchers have concentrated on maximizing the speed of SiGe HBTs
irrespective of power co~lsumption, this wotk attempts to utilize the SiGe base to enhance
performance at low power levels. To realize the goal of high speed operation at low
power, a novel self-aligned device stmcture is introduced.
The work describeci hem is collaborative with Gennum Corporation of Burlington.
Ontario. In partîcuiar, the novel self-aligned SiGe base device was developed by
modifying an existing commercial process developed at Gennum. The author's
contri'bution to the project included design of optimum doping and composition p r o f i
for the new device using the BIPOLE3 slmilaîor, modification of an existing L-Edit
layout environment to include the new layers requirrd for SiGe devices, design of a suite
of test transistors, and development of several key process techniques related to SiGe
base formation, and analysis of electrical characteristics of completed devices. Most
device processing was carried out at Gennum, with some key steps completed at the
National Research Councii and Carleton University. To pmtect the co~~llllercid interests
of Gemurn, no details are given here on îhe baseline proces on which the SiGe base is
grafted-
The thesis is organized as follows. In chapter 2, a bnef introduction to SiGe HBT
technology and theoretical background are given. Chapter 3 presents device architectures.
BIPOLE3 simulation results are presened in chapter 4. In chapter 5, details of the new
developed process flow, fabrication techniques and electrical characterization results for
cornpleted devices are presented. nie conclusions of this study are presented in chapter 6.
CHAPTER 2
SiGe HBT PHYSICS AND TECHNOLOGY
2.1 Physics of the SiGe HBT
The advantage of the SiGe heterojunction bipolar transistor (HBT) lies in the ability to
modify the band gap of ordinary silicon serniconductor material for higher performance.
Band gap engineering is a powerfd tool used for creating faster transistors. Conventional
silicon devices have an effectively fi& band gap of 1.12 eV which b i t s switching
speed, compareci to HBTs fabricated on III-V compound materiab such as GaAs. With
the addition and gnding of the Ge (which has an energy gap of 0.66 eV [Il])
concentration across the base region of a BJT, it is possible to modify the band gap and
consequentl y enhance the performance of the silicon transistor.
The main difference between the SiGe HBT and Si BST is iiiustrated in the energy band
diagram of Fig.2.la of a linearly graded Ge doping profde in Fig.2.lb (121. Figure 2. l a
shows schematic energy band diagrams of Si BIT (soiid iine) and SiGe HBT (dottecl he)
showing a band gap modification [12]. aE, is the band gap difference between Si and
SiGe: ~ S ~ ~ ( x = û ) and nE,,(x=WJ represents the amount of band gap reduction at the
eminer-base and base-cuiiector depletion edges in the neu id base, respectively.
aE,,@de) = AE~,,(X=WJ - aE,,(x=û) represents the band gap grading aaoss the
Base
Figure 2.1 a: Energy band diagrarns of a Si bipolar transistor (solid Line) and SiGe HBT (dotted line). b: Doping profie of Ge across the base region [ l t ]
neutral base region. This band gap grading introduced into the base region of a SiGe HBT
induces a drift field which aids minority carrier transport through the base, d t i n g in
higher frequency operation [12]. This means that the base band gap of SiGe HBTs can be
engineered to enhance device performance? thereby making it suitable for a wide range of
high speed analog and RF applications. Harame et al [12] fomd in SiGe HBTs. the Ge
introduced into the base region duces the base band gap by about 75 meV per 10% Ge
compared to a Si BJT. Ii is this reduced band gap of SiGe strained layers cornpanxi to Si
that is directly exploited in the SiGe heterojunction bipolar transistor. The aE, is
detennined not only by the Ge concentration but dso by the saain creaîed between the
SiGe and Si substratet For identically constructeci devices, the ratio of the current gain P
between a SiGe HBT and Si BIT is given by [12],
a ratio which is larger than unity for finite Ge content. q represents the ratio of the
position-averaged minonty Camer mobility in the base region of a SiGe HBT compared
to a Si BTT, y represents the ratio of position-averaged density of states pduc t ( N, N,)
between the two transistor^, k is B o l t z m a ~ constant, and T is the absolute temperature.
Equation 2.1 indicates that the smaiier base band gap in a SiGe HBT exponentially
increases the number of minority carriers injected into the base, causing an increase in the
coiiector current for the same forward-bias.
As mentioned above, quaiitatively, the grading of the Ge a t m actoss the quasi-neutral
base induces a drift-field in the base which accelerates the electrons injected from the
emitter to the collecter, thereby decreasing the base transit time wmpared to a Si BJT.
Harame et al [12] found for a constant base doping and using the theoretical equation
derived by Kroemer [13] for the base transit time, the ratio of base transit tirne for SiGe
kt:*) and Si (s,,) devices is
which, for finite Ge grading, is les than unity, and thus enhances the transition frequency
F, . Since the basetransit time s, is usually a major component in the F, equation,
An additional benefit of using a graded-Ge profile in a SiGe HBT is an enhancement in
the Early voltage VA - a measure of ease with which the majonty d e r profile in the
base is depleted by an applied base-coiiector bias. Rinz and Sturm [14] developed an
anaïytical mode1 to explain the higher values of the product PV, in Si/SiGe/Si HBTs. The
output conductance (Iience & y voltage) is a rneasure of how much the neutral base
profde can be depleted with reverse bias on the collecter-base junction, and is manifested
in the rise of the coliector current density Jc with collecter bias at fixed base-emitter
voltage. The ratio of Eariy voltage in the SiGe HBT to that of the Si BJT is given by 113)
Equation 2.4 indicates that for f i t e grading across the quasi-neutral base, the
exponential dominates the hmctional dependence on Ge content, and the d o in eq.2.4 is
larger than unity. yieldmg an improvement for a SiGe HBT comparai to a Si BJT. In
other words, the base region becornes harder to deplete than for the comparably doped
silicon transistor. Large Early voltage means the transistor has high output resistance,
which is useful for analog design applications such as RF communications.
From the above discussion, we can see that p, F, and VA are increased significantly when
SiGe is htroduced in the base region of the HBT, and this leads to improvernent in the
device performance.
High transition frequency F, and high oscillation frequency Fm are simultaneously
requued for both digital and analog ICs. The reiationship between F, and Fm is given by
IlSI,
F, = [ F, 1(8 x RB CJ3J", (2.5)
where RB is the total base resistance and Crc is the collecter-base capacitance. SiGe HBTs
have high Fm comparai to Si BJTs since the base in the former transistors can be heaviiy
doped whüe maintainhg a high injection efficiency due to the band gap difference
between silicon and strained SiGe. This means that the high current gain in the SiGe base
of the HBT can be traded off for higher base doping without comprornising device
performance.
2.2 Growth of SiGe on Si Substrate
The nature of the crystal stmcture resulting from the growth of SiGe on the Si &strate
9
plays an important role on the device performance. There is a mismatch between the
lattice constant of the Ge (5.658 A) and Si (5.431 A) (16). which is equal to about 4%. As
a result of the mismatch between the lattice of the SiGe f i h and Si substrate, two
distinct classes of growth are possible: pseudomorphic growth and dislocated growth.
Figure 2.2 shows two dimensional representations of the two classes of growths inchding
the Si substrate and the relaxeci SiGe layer. Below is a qualitative description of the such
growths, and the details can be found in several references [l, 17,181.
In class one pseudomorphic (incornensurate) growth, a compressive strain will be
developed as a result of the lanice mismatch between the epitaxial SiGe and the Si
substrate. Consequently, the la& constant of the SiGe wiii be tetragonaliy rlistorted, to
match the in-plane la& constant as shown in Fig.2.2~. Pseudomorghic growth of SiGe
on Si can continw for a thickness determined primarily by the mismatch of the relaxed
lattice constants of the SiGe and Si, and the substrate temperature. If the SiGe thickness
exceeds a cenain value or the substrate is exposed to sufficiently high temperatures for
long p e n d of tirne, at which the pseudornorphically grown layer is no longer
thermodynamically stable, the iattice constant relaxes to its original value. This means
that the strain in the SiGe layer wiii be relaxed and misfit dislocations will form at the
interface between the silicon and SiGe, as illustrateci in Fig.2.U. One disadvantage of the
shain relaxation in hetemjunction bipolar transistors is that it lowers the band gap
difference between the Si and SiGe resuiting in a degradation in injection efficiency and a
reduction in current gain. as iiiustrated in eq.2.1. Also misfit dislocations that acmmpany
10
(a) Si- Substraie (b) Reiaxed SiGe
Relaxcd SiGe
Misfit dislocation
Fig.2.2 Representation of the strained and relaxed structures of SiGe on Si substrate
strain relaxation can lead to leakage andor recombination at the interfaces where there
are a hi@ density of dislocations [19].
It appears from the above discussion that the SiGe strained layer is thennodynamidly
stable to the formation of unwanted film defects only when the Ge content is kept below a
specific upper bound Increasing the Ge content will decrease the critical thickness of the
SiGe. Shce Ge is rquired oniy in the base region of the transistors, and since many of
the pmperties of bipolar transistors depend exponentially on changes in the band gap,
only a small Ge conceutration is required. In the present work a maximum concentration
of 10% will be used during formation of the transistor base. This means that SiGe
stability constraints are satisfied in the fabricated devices. Since the base thickness is l e s
than lûûû A, the devices are stable under îhe Mathews-Blakeslees criterion [20].
2.3 The UHV/CVD Pmxss
SiGe alloy layers tnay be grown on Si epitaxially by severai techniques [121-24) that
compte in terms of cost, ease of thickness and dopant control, flexibility, scalability and
contamination by impurities. The most common ones are molecular bearn epiiaxy (MBE),
low pressure chernicd vapor deposition (LPCVD), atmoapheric pressure and dtra-
high vacuum chernical vapor deposition (UHV/CVD). The challenge of p w i n g SiGe
ailoys is currentiy met by ail of the above-mentioned methods, with UHVKVD king the
most widely used and the most amenable to high-volume production. This technique was
fmt demonstrated by Meyerson [21]. More specifically, Meyenon and CO-workers at
12
IBM [Il combined the ultra-high vacuum of MBE and a conventional CVD process by
exploiting the role of hydrogen in teguiaihg the chemistry at the Si and SiGe growth
interface.
The UHV/<ND developed by Meyerson 11,211 offers several advantages over other
g r o h techniques, such as low temperature ( 4 5 0 O C ) deposition, in siîu ptype doping,
highiy precise film thickness, composition and dopant concentration profiles that can be
produced of almost hitrary abruptness. The result has k e n the ability to produce a hi@
performance SiGe hetemjmction bipolar transistor.
2.4 Swf'ace Cleaning
The UHV/CVD technique is dependent on a simpk yet vitally important s d a c e cfeaning
and preparation procedure to avoid the growth of native oxide which would hterfere with
epitaxy. Fuli details on this clearting technique have been given elsewhere [1.22]. The
technique relies on hydrogen passivation of the bare silicon surface. This passivation is
accomplished by irnrnersing the substrates in diiute hydrofluric acid and then removing
them without any subsequent rinse. Photoemission spectroscopy studies [25] shows that
HF etching renders the silicon surface passive, free of oxide, and stabiiized by the
presence of a layer of chernisorbecl atomic hydrogen. The hydmgen adlayer formed by an
HF dip reduces the reactivity of water vapor Mth the silicon surface by ppproximately
thirteen orders of magnitude [1,25]. The hydrogen adlayer acts as a chernical banier to
recontamination. This means that in UHV/CVD there is no "native oxide" to be removeci
13
from a siIicon surface prior to epitaxial growth, provided the temperature/time history of
the load sequence prevents hydrogen desorption until growth is initiated.
2.5 SiGe F i Growth
After the Si wafer surfaces wefe hydrogen passivated, they were placed in a quartz wafer
boat and inserted into the load lock chamber, which is pumped to below lx104 torr [l]. A
hydrogen flow at a corresponâing pressure in excess of 200 mtorr was used during wafer
boat transfer into the main chamber. This prevents the cross-contamination resulting from
residual gas in the load chamber. Hydrogen flows terminated when the main chamber was
isolated from the load chamber. Growth is then initiateci imrnediately. Gaseous sources
employed are silane (SiHJ, gemume (GeHJ and diborane (BZH& using helium as a
diluent of dopants to produce films of desired chernical content. Deposition of SiGe
ailoys is perfomed at a temperature of about 525 O C and a total operathg pressure of 1.0
mtorr. With appropriate control and rapid pumping of the gas mixture mentioned above,
high quality of SiGe with a e . W o chernical uniformity and film thickness b e r than
Il . W o have been demonsErated [1,25].
2.6 Polycrystalline Silicon
Polycrystalline silicon (polysiiicon) is an important material in integrated circuit
technology, because of its high-temperature compatibüity with single-crystal Si and its
semiconducting pmperties. For almost three decades, polysilicon has ben used in metai
oxide serniconductor and bipolar technologies [26,27]. It may be used as the gate in MOS
14
devices, as the emitîer, base contact or collecter contact in bipolar junction transistors,
and also in onchip resistors and capacitors, and interconnect Lines [26-291. In bipolar
transistors using polysilicon emitter contact technology, control of the interface between
polysilicon and a siliwn substrate is one of the key parameters to insure repeatability
performance [30].
Polysilicon is so usefui because it foms an adherent oxide, absorbs and re-emits dopants,
has good step coverage if depsiteci by CVD. matches mechanical propetth of Si single
crystai. is compatible with HF, and many other properties, which are beyond the scope of
the present work. These properties make polysilicon uniquely suited to be a prirnary local
intercomect material, and its ability to fom silicides extends that application to longer
intercomect lines. In the present work the polysilicon wiU be used to form the emitter of
both the self-aligned and non-self aligned HBT. and the external base for the non-self
aligned HBT. Another advantage of the polysilicon in the present work, is to protect the
field isolation from HF attack during the passivation process.
2.7 Traasit T i in Bipolar Transistors
2.7.1 One-Dimensional (Vertical) halysis
The figure of merit cornmonly used to characterize the high-frequency behavior of a
bipolar transistor is the cut-off or transition frequency Fr This is the frequency at which
the transistor incrernental current gain drops to imity. The tocal transit time, t,, from the
emitter contact to the coliector contact of the onedimensionai bipolar transistor is related
15
to the transition frequency by [15,16].
F, = 1/(2.rc r,),
t, is made up of six deiay components conespondhg to different regions of the
transistor. The physical formula of each component is given as foiiows [15,16].
1. Neutml e m i w region chargrirg time T,
where W, and Wb are the emitter depth and neural base width respectively, F, is a
grading coefficient (typically between 1 and 5). and D,, is the elecûm diffusion constant
in the base.
2. EmmLtter-basejunciion chargihg time t,
This is the deiay t h e due to emitter-base junction capacitance, Cm times the 'diffusioli
resistance' r, (=l/&. where is the transconductance, g, = & NT, where I, and V, are
collector current and thermal voltage respectively),
3. me-transit tirne t,
For a Si device having uniforni doping, simple theory [31,32] predicts that for a given
base width, rb is given by
According to eq.2.2, there is a drift field resuiting from the grading of the Ge across the
quasi-neutrai base. This means that the first term of eq.(2.9a) shouid be multiplieci by
such a grading factor G,, in this case eq.(2.9a) should be read as,
canier velocity and the rernaining parameters have their usual meaning.
4. Collecter space charge iayer m i t hine t,
where WS1 is the coiiector depletion width.
5. Rase-collecmr junction capacimnce chcaging titne t,
t c b = fe CJC,
where CJc is the base-coiiector junction capacitance.
6. RC time constant for bare-collecter jwtction r,
t, = r, CJC,
s, is the time constant for charging the base-coliector capacitance C,, through the
coiiector resistance- Here r, is the undepleted collector resistance, i.e the resistance of the
collector region between the base-coLIector space-charge Iayer and the heavily doped
substrate or burie- layer.
There is an additional delay r, due to free carrier charge in emitter-base spacecharge
layer [15]. There is no explicit analytical formula for this delay. According to Roulston
[IS]. this delay is very s d l and ua be obtained from BIWLE3 simulation [33].
Thus, the total delay, r,, is given by adding ai l of the above components:
After manipulating the above equation, the fmal total delay becomes,
The contribution of each delay component to the total delay will be discussed in chapter
four according to the specification irnposed by each design. The simulation resuits
obtained from the BIPOLE3 1331 program WU give us an approximate value for each
component of the delay. It shouid be noted that the delay due to the substrate capacitance,
C,,, which is equal to CJsc thes rc was not included in the total delay given by eq.2.14,
and will be addresseci in the two-dimensional analysis given below.
The second important parameter of the bipolar transistor is the maximm osciüation
frequency, Fm. It is defined as the fiequency at which the maximum available power gain
of the transistor drops to unity. For bipolar transistors a convenient approximation for Fm
is given by eq.2.5.
2.7.2 Two-Dimemionai (Laterai) AnaJysis
In the vertical (one-dimensional) analysis ail the delays given by eqs. 2.7-2.12 were
cornputeci as "charge density/current density" [15]. in addition, the transition frequency F,
in vertical analysis was detemined directly h m the sum of al1 six vertical delay times
given by eq.2.7 to eq.2.12 F, in a real transistor is always less han would be pcedicted
using eqs.2.6 and 2.14 because these equations do not take into account the foiiowing
factors: (1)sidewail injected charge and current, (2)sidewali capacitance for the emitter-
base junction, (3)exainsic base region capacitance. and (4)collector substrate resistance
and capacitance (for IC devices).
It is very diff~cult to incorporate the above four factors in simple %and calcuiations" of
BJT performance. Lateral effects can, however, be taüen into account using the BIPOLE3
19
program. For this purpose the BIPOLE3 manual 1331 defiaes a new set of delay tunes in
lateral analysis, and these are given as foîlows:
(1) r,,: is a small signal delay time due to the integrai of minoriiy carrier charge in the
whole of the active (intrinsic) region. This include the exnitter, base, emitter-base and
base-collector space charge layers. The delay tirne sAvo is related direcîiy to the vertical
simulation delay the . In the BIPOLE manual. the delay time r,,, is defined as the delay
due to the intrinsic region diffusion capacitance Ca- Rouiston 1151 tias derived an
equation relating C&f to the delay times te, s,, t,, T, and the tramconductance as
follows:
(C, /g,J is equivalent to the delay r,,, thus
(2) s,,,: is the delay tirne due to sidewaii injected electron concentration into the base
region outside the active (intrïnsic) base region.
(3) s,: is the delay time due to minority carrier charge in the emitter-base space charge
layer.
(4) s,,: is the delay t h e due to C, and total coiiector series tesistance. This delay is
equivalent to total jmction capscitance divideci by small signal tnuisconductance k.
20
(5) s,: is the delay time due to &T/q) (CE + C,& where q is the electronic charge and
the remaining parameters have their usual meaning.
(6) s,: is the delay tirne due to (Cric L@). where %, is the vertical raistance under
the collecter contact, and p is the current gain.
Adding al1 of the above delay times, the total delay tirne q,,, in a two-dimensional analysis
is thus given by,
T, = zAVO + 'CA-+ f ES^ + fRa + SR^^ + tSUB (2.17)
The transition frequency F, is then given by,
In many practical devices, lateral effects must be taken into account to accurately ptedict
F,. In chapter four, BIPOLE3 program will be used to sirnulate the HBT and BJT devices
using both vertical and lateral analysis.
3.1 Transistor Structures
Two basic HBT structures were developed in the present work Both stnictures follow a
relatively conventional bipolar process flow prior to base formation. Devices are built
over a heavily doped n+ buriecl layer diffusai into a Iightly do@ p-type substrate. A
much more Lighcly doped r epitaxial (epi) coilector layer is gram over the buried layer.
The buried layer is contacteci with a deep coilector sinker diffusion. Transistors are
isolated with a deep borm diffusion penetrating through the thickness of the epi collecter
to the ptype substrate. The active region in which the base and erninef are formeci is
defined by semi-recessed local oxidation of the silicon (LOCOS) isolation. A layer of p+
polysilicon ("field poly") extends from the active region over the field oxide to allow
contact to the base to be made in the field region,
The base region is formed by the WHVKVD technique described in chapter taro. The
deposited base layer grows epitaxialiy in the active region, and adds to the thickness of
the field poly in the field region. A polysiiicon emitter is used Silicidation with platinum
is used to reduce the tesûtance of the emitter stripe and exposed extrinsic base regions
both in the active region and over the field
The two device structures considered differ in the alignment of the siiicided base to the
emitîer. The f i t structure, which will be referred to as the "self-aligned" (SA) structure,
is shown in cross-section Fig.3.1. In this device the silicided base region is self-alignecl to
the emitter polysilicon stripe. The low-resistance silicided extrllisic base is separated from
the intrinsic base by just the width of the oxide spacer formed on the exnitter sidewall,
providing a very low value of extrinsic base resistance. Use of a deposited base ailows
base contact to be made over the fieM oxide, so that the extrinsic portion of the base-
coliector junction on either side of the emitter stripe has a width equal to the minimum
lithographie dimension (1.5 pm). This provides a anisiderable reduction in CJc compared
to a typical single-poly self-aliped BJT (341. The main drawback of the self-oligned
structure is the risk that the extrinsic SiGe base in the active region will be partly or
cornpletely consumed during the emitter poly etch This risk is compounded by the need
to ensure removal of the emitter poly "stringer" from the field poly sidewall, and the fact
that it is difficult to devise a plasma etch chemistry that atîacks polysilicon but not SiGe.
If the emitter poly etch breaks tfuough the SiGe base, contact to the base is lost. Similas
risks are associaied with the formation of the oxide spacer on the emitter sidewd.
The non-self aligned (NSA) structure shown in cross-section in Fig.3.2 avoids the
problem of ernitter poly etch endpointhg by extending the emitter polysilicon over the
edge of the device well. In this structure the active emitter area is defined by opening a
window in a deposited oxide separating the emitter polysilicon h m the base. This
Figure 3.1 Cross-sectional view of the self-aligned HBT structure
Figure 3.2 Cross-scctional view of the non-self aiigned HBT structure
structure is much more tolerant to process variation, but suffers from increased base
resistance since the silicided region does not extend to the edge of the intrinsic base.
3.2 Device Layout
The Layout of each SA and NSA structure, which is presented below, consists of severai
mask levels for the process steps. The L-Edit program [35] was used to design the
required mask layout. In the current HBT technology, the 1X npn has a single poly
emitter with active area 1.5x3.0 pm2. The HBT process is optimized mund the emitter
polysilicon. Figures 3.3 and 3.4 illustrate the mask levels for each structure. Part of the
layers shown in Figs.3.3 and 3.4 wiil be descn'bed in detail in chapter five, whereas layers
cornmon to Gennum's existing bipolar process will not be describeci. The main difference
between the SA and NSA stnicturs is the difference in the base contacting scheme.
Figure.3.3 illustrates the layout of the SA stnicture, where the base of the transistor
consists of two componentts. The füst component is due to the intrinsic base situated
directiy underneath the emitter poly, and the second component is due to the extrinsic
base situated just outside the emitter poly, and bounded by the field poly.
Two base contacts were introduced to a 1X npn self-aligned and non self-aligneci
structures (Fig.3.3 and 3.4). and were placed laterally on each side of the emitter poly
without compromising the device width. The main feature of the two-base contact
devices, is that the areas of these devices are smdler than the one contact device. In this
case the parasitic capacitances were reduced, therefore enhancing the device performance.
25
Figure 3.3 Sewaligned HBT with two base contacts
Figun 3.4 Non-self aligned HBT wiîh two base contacts
CHAPTER 4
DEVICE SIMULATIONS AND ANALYSIS
4.1 Introduction
Simulation of any serniconductor device before fabrication is a very important step,
because preiiminary perfomiance estimates can be obtained from simulations very
quickly, and at much Iower expense than the results obtained €tom the fabrication
processes. The complete process flow is often very lengthy. usualiy taking several weeks
and sometimes several months depending on the number of the masks used and the
complexity of each process step. Two types of simulation software are commonly used
in the development of new semiconductor technologies: process simulators and device
simulators. Process sirnulators predict structural details such as doping profides and the
thickness of oxide layers on the basis of pmcess parameters such as implant doses and
fumace cycle rimes and temperatures. The most widely used simulators in this category
are SUPREM3 and SUPREM4 [36]. Device simulators take structural information as
inputs, and predict device electrical characteristics. Modem simulators can provide quite
accurate predictions of device characteristics. particularty if there has been an opportunity
for calibration. Even without a calibration, the simulator program still provides vaiuable
information compared to the resuits obtained from the anaiytical equations.
In the present work, BIPOLE3 has been selected as a device simulator program to design
structures for the new SiGe HBT technology. BIPOLE3 [33] was developed by Prof. DJ.
Roulaon and CO-workers at the Univenity of Waterloo, Ontario. to provide a convenient
and rapid means of predicting teminal elecb-ical characteristics of bipolar transistors
from input consisting of fabrication data such as impurity profiles, mask dimensions and
recombination data. This would help gain insight into critical device characteristics such
as the transition frequency, oscillation frequency. current gain, Eady voltage and most of
the parasitic resistances and capacitances of the transistor. It shouid be mted that
BIPOLE3 does not have models precisely describing the novel HBT structures
considered hem, particularly in regard to the extrinsic base. However. in terrns of the
simplicity, cost and speed, BIPOLE3 is arguably the best simdator that adequately
describes the present HBT.
The BIPOLE3 bipolar device simulation program is based on obtaining a set of
differential equations describing current flow in the vertical (mitter-base-couector)
direction and a separate differential equation descnibing current flow in ihe lateral
direction [37.38]. In the vertical 'x' direction, the device is divided into five regions: (1)
neutral emitter, (2) emitier-base space charge layer, (3) neutral base, (4) basecollector
space charge layer, and (5) neutral wiiector. In the three quasi neutral regions, Poisson's
equation is not solved. but only the transport and continuity equations. The solution for
majority carrier cunwit is then perfomed in the lateral 'y' direction in the neuaal base
region, using the resuits obtained from vertical analysis. The a h of the whole analysis is
to predict the electrical characteristics in terms of the physical parameters. The éetaüs of
29
the theoretical analysis in the vertical and lateral directions are beyond the scope of this
thesis and are given in the references [37,38]. AU of the foliowing resuits were based on a
up-to-date version of the BIPOLE3 program (v.2.5.0. 23 March 1997 [33]).
4.2 Electricai Performance Specifications
One of the objectives of the present work is to determine doping and Ge concentration
profiles for a SiGe base HBT meeting the foIlowing eleceicai specifications:
1.F,=Fm=20GHzat I.=200pAandV,=l.OV.
2. A brgakdown voltage BV, 25 V.
3. A current gain p of approximately 200.
These electrical specifications were to be met with an equipment set providing a
minimum Lithographic feature size of 1.5 pm. The target emitter window size for a "lx"
device was 1.5 pxn x 3.0 p.
For a 1X device a collecter cment of 200 @ corresponds to coiiector cuctent density J,
of just 4.4~10) N c d . In conaast the high performance devices reported by researchers at
IBM [12] reach peak F, at Je - 105 A/cm2. Further, these devices typically have breakdom
voltages of 2 to 3 V. The design problem faced hem is therefore very different to that
encountered in developing an HBT intended to provide maximum speed without conceni
for power dissipation or break d o m voltage BV,.
4.3 Caicdation of the Extrinsic Base of the NSA Devices
Before modeling the NSA devices, it is worthwbile to shed the light on the BIPOLE3
caiculations of the extemal base resistance for the SA devices. BIPOLE3 does not have
models precisely desmiing the novel HBT stnxctures considered here, particuiarly in
regard to the extrinsic base. Figure 4.1 shows the extrinsic base cross-section of an npn
SA device where the P region is separated from the emitter diffusion by a distance
ESBX. The deficiency in the BIPOLE3 prograrn is that the sheet resistance in the ESBX
region is computed h m the intrinsic region irnpurity profile, and this approximation
does not reflect the true impurity profile in our SA devices. This means that the total
rneaswed base resistance may differ from the predicted base resistance. in the case of
NSA devices, the BIPOLE3 program can not be used unless the extrinsic base resistance
is modeled, because it is only suitable for SA devices. For this reamn two approximate
models were suggested and used throughout the simulations, and their results are
presented in the following sections. Beiow is a brief discussion of each model.
4.3.1 Model 1 (Ovcrcstima&s Base Resistancc)
Model 1 overestirnates the exths ic base resistance of the NSA devices. In this model
there are three parameters. These parameters are used by BIPOLE3 program, and have
the following meaning:
(1) REXTSW.0 Wsq. it represents the silicided region of the extrinsic base sheet
resistance according to Fig.4.2. Figure 4.2 shows part of the layout of the NSA device
illusaated in Fig.3.4. The magnitude of the REXTSQ is given above, based on previous
measurements of siiicided devices.
(2) ESB: is the distance from the emitter window to the base contact metal.
(3) ESBX: is the distance h m the emitîer window to emitter poly edge.
In model 1 shown in Fig.4.2, the value of the REXTSQ was fixed during simulation,
whereas the values of ESB and ESBX were varied depending on the geometry of îhe
device. The drawback of this model cornes from the fact that BIPOLE3 cornputes the
sheet resistance over distance ESBX from the inmnsic base regioa impurity profile
directly under the emitter. These caldations are not accurate, because the impurity level
under the emitter poly is l e s than that outside it, dong the path towards the base contact,
which is situated outside the field oxide. This is the reason that the simulation gives a
higher value for the extemai base resistance than is acnially anticipated.
ESB
ESBX
ESB ESBX
Figure 4.2 Mode1 1 for the NSA device
Figure 4.3 Mode1 2 for the NSA device
4.3.2. Mode12 (Underesthates Base Resistance)
In mode1 2 shown in Fig.4.3, the parameters REXTSQ and ESB have different meaning
as given below.
(1)REXTSQ: describes the sheet resistance of the field poly and SiGe poly stack. From
short loop experiments, the value of the REXTSQ for polysilicon (thicbiess=3000 A) was
found to be 165 wsq. It is expected that this value wiil be reduced if the thickness of the
SiGe layer is added to the thickness of the field poly, because the sheet resistance is
inversely proportional with the thickness.
(2)ESBX: is the distance h m the emitter window to field poly edge.
The ESB has the sarne meaning as given in model 1. In model 2, it is assurneci chat the
silicided region of the HBT, which is just outside the field pdy, has negligible tesistance,
because it is insignificant cornpareci with the remaining components of the total extrinsic
base. In model 2, the magnitudes of the ESB and ESBX also depenàs on the geometry of
the device. In the following anaiysis, both models were employed to calculate the
extrinsic base resistance of the NSA devices.
4.4 Delay Times Contributhg to the Transition Frequency
In order to gain insight into the mechanisms that govem F,, vertical and lateral analyses
have been conducted under various conditions to determine the magnitude of each delay
component that contributes to F, in the HBT.
4.4.1 Preliminary Caldations
The transition frequency given by eq.2.6 contains severai cornponents representing the
delay times in various regions of the transistor. Before perfonning detailed BIPOLE3
simulations, it is desirable to evaluate each component in order to identify which delay
time makes a signifiant contribution to the Fp
Reliminary calcuiations have been carrieci out to select doping leveis to serve as a
starting point for BIPOLE3 simulations. The doping levels in the emitter, base and the
collecter were found to be equal to 3 x I P /cm3, t ~ l O * ~ /cm3 and 2.8x1016 /cm3,
respectively. The foiiowing one-dimensional hand caicuiations teveai why these doping
levels were chosen. The self-aligned SAlX device was chosen for this analysis.
1. Charging time rir the quasi-neutd etnitter region r,
From eq.2.7, r, = W, Wb /(F, D,),
Here the ernitter stripe depth We=500 A, Wb=450 A, Dn=2.3 cm2/s and Fc=5, so the delay
tirne s, = 1.94 ps. To reduce this delay either We or Wb or both should be reduced. The
emitter depth can be reduced using a weU controlled rapid thermal annealing pmess
instead of the conventional fumace anneal. Reducing the base width below 450 A is
limited by base punch through, and is not practid. It should be noted that there is a
composition factor, resulting h m germanium-induced band gap reduction at the base-
emitîer depletion edge Dg]. The structure studied hem bas no Ge content at the base
emitter junction, so this factor was wt included in the calculation of s, According to
35
Patton et al [39], the composition factor gives a significant reduction in te. However.
BIPOLE3 program takes into account such factor durhg the simulation.
2. Emitîer-base jwrction chargrng time t,
From eq.2.8, r, = CJE /g,,,.
where g,=C N,, for &=2=U)O pA and Vt=û.0259 V. thus &=7.7x1(r3 S. The emitter-base
junction capacitance CE is given by [IS],
C E = E S ~ &fL (4-1)
where = 11.9 E, ( E, is the pemittivity of free space) is the silicon perrnittivity, A,
(-4.5 pz) is the emitter-base j d o n area and X, is the width of the junction. By using
eq.Al.1 (Appendix A). &=().O2 pm for Vp0.77 V. Substituting the values of E,, A,
and X, into eq.4.1, CE =23.6 fF, thus the delay tirne t, = 3.0 ps. This is a very
significant delay which would slow down the device. In order to minimize it, the doping
ievel in the base must be reduced to a minimum. This is one of the main reasons which
led to the use of a Iight doping level in the base of the transistor.
3. Base-tmnsit rime tb
From eq.2.9b, rb = (Wb f2 D,) G, + (Wb /vJ,
G, is the grading factor taken from eq.2.9b. For Wb =4M A. Dn=6.78 cm2/s, and the
reduction in the base band gap ~E~4.075 eV per 10- [12], thus rb = 1.13 ps. This
delay is also important and can only be reduced by decreasing the width of the base. In
the present work it is dif f idt to reduce the Wb below 450 A. because of the occurrence
of base punch through, as explained eariier. Also, since muiimizing CJc requires a lightiy
doped base, if Wb is too smaü the base resistance will be excessive and Fm will be
degraded.
4. Collector spuce charge loyer Pansit t h e r,
From eq.2.10, 7, = W , 1 2 V,
Using eq.Al.2 (Appendix A), W , a . 3 pn and v, = 10' d s . thus r, = 1.5 ps. Although
this delay is not dominant, it c m not be neglected. This delay can only be reduced by
increasing the doping level in the coflector, which wouid increase the junction
capacitance CJc.
5 . Bcèse-collecter junction capcitance charging tirne s,
From eq.2.11, r, = r, CJc= CJc /&,
The base-coliector junction capacitance CJc is given by [15],
CK = €si (4-2)
The base-coiiector junction area & of the device SA 1Xa 13.0 pz. W, d . 3 pm,
C,, -4.7 fF, thus T, = 0.6 ps. This delay is relatively insignificani.
6. Collector chorgrng time sc
From eq.2.12, r, = rc C J ~ .
For r, -50 Q, C,= =4.7 €F as given above, thus s, 4.23 ps. This delay is srnail and can be
37
neglected.
%y substituting ail of the above delay times into eq.2.6, the F, was found to be equal to 19
GHz. Furthermore, the above analysis indicated that the dominant delay tirne is due to the
emiaer-base junction charging tirne z*. Having s, as the dominant delay is unusuai, and
reflects the very low current density at which the device is to be operaîed. To control r,
very light base dopiag must be useci.
The unity power gain oscillation frequency Fm is related to F, by eq. 2.5,
Fm = [ F, 1(8 n RB CjdI*,
The above equation shows that Fm depends on the parasitic elements ( RB C d . ?'O
increase Fm, both RB and CJC must be decreased. Decreasing the CJc is possible by
increasing the Wd through decreasing in the coiiector doping. The base resistance RB can
be decreased by increasing the doping level in the base, and th& degrades F, because the
junction capacitance Cm will increase and ultimately introduce an unacceptable delay in
the r,. This case is much worse in the non-self aligned devices, because RB in these
devices is much larger than RB in the self-aiigned devices.
In ail of the above analysis, the laterai effects that have been discussed in section 2.7.2
were not included in the hand caiculations, because they are difficult to include
analytically. It is possible, however, to include these effects using lateral analysis in the
BXPOLE3 program.
4.4.2 Simulation R d t s
The purposes of the present simulations are two-fold The first is to select the best doping
profiles and junction depths in order to meet the required specifications. The second is to
determine the effect of device geometry on performance to determine the benefits which
might be expected with improved tithographic resolution. Several dimensions for the
length and width of both emitter mask and field poly (polysilicon). in addition to the
emitter poly width, have been investigated and are iilustrated in Table 4.1. In Table 4.1.
SA and NSA are Labels used to define the self-aligned and non-self aligned transistors
respectively.
In order to simulate the device characteristics using BIPOLE3. several input parameters
must be provided. The most important parameters are sumrnarized as foiiows: the doping
in each region of the transistor, whether the doping is uniform or graded across each
region (in the present simulation a unifom profde was considered in each region); the
mask dimensions and device geometry; thicbiess of the epitaxial layer; width of the
transistor base and the Ge concentration and its profüe across the base; the depths of the
emitter-base and base-coiiector junctions. In addition, appropriate values for the control
parameters of BIPOLE3 program must be specified. The metaiîurgical junction depth X ,
which is required in the simulation. was dculated using the foiiowing procedure:
Table 4.1. Mask dimensions of the SiGe HBTs
E1.mask width um
1 : E means emitter 2: F means field
The width of the depletion region at the ernitter-base junction X, and at the base-
collector junction & was caldated using a step junction-type model. The metallwgical
junction depth at the base-coiiector region (XJ& is the surn of the parameters XJ,, Wb, &,
and &. In the present work, the X,, (the metallurgical junction depth at emitter-base
region) was considerd to be equaf to 0.05 p and the width of the quasi-neutml base Wb
was 0.045 pm. The junction depths & and X, depend on the dopant concentration in
each region, and can be calculated analyticaiiy using eqs.Al.1 and A1.2 using a depletion
approximation appmach. In this case X, can easily be obtained for a given value of Wb.
The depletion Layer capacitances' CIE and C,, were calculated using eqs. A2.1 and A2.2
res pec tivel y.
4.4.2.1 Enect of Doping Lewis on the Delay Times
4.4.2.1.1 Vertical Anaiysis
By adjusting the vertical profile of a HBT structure, it is possible to extract several
important parameters which dexfibe the performance of the device. S e v d device
geometries have been simulateci, and the results of two typical HBT SA125X and SAlX
devices are presented in Table 4.2. This table shows how the delay times change as the
dopùig Ievels in the active regions of the transistor change. The changes in the delay
tirnes 5, r,, and 5, are insignifiant. This means that the main components of the delay
times are due to the sum of the emitîer-base junction charging tirne, t,, the base transit
time t,, and the collector space charge transit time, t,,. The base transit time seems to be
independent of the variation of the doping levels, whereas the delay times t, and r , are
41
slowly changing with the doping levels. The delay tirne hcan be reduced by decreasing
the emitter-base capacitance CE, and this can be achieved by using a lightly doped base.
This is the only profde-parameter that can be used to rninimize the effect of CE on the
performance of the devices. On the other hand, it is possible to reduce the effect of the Cm
by reducing the size of the device as in the case of the SA125X device in order to
increase the collector current density at &= 200 pA. More detail on this point wiU be
given in section 4.6.
The base transit time cm be decreased by decreasing the thickness of the SiGe layer but
at the expense of the break down voltage BV, (due to the increase in the current gain P).
and also at the risk of base punch thmugh. As rnentioned earlier, the minimum base width
used in the present simulations was 450 A. The collector space charge layer thne t,, can
be reduced by decreashg the collector depletion width Wd. This can be achieved by
increasing the doping level in the collector, The consequemes of this procedure is that the
break down voltage BV, will decrease and the base-collector junction capacitance CK
will increase. These results wiil be demonstrateci in section 4.5. Table 4.2 incikates that as
the size of the transistor changed, the delay time 7, significantly increased. Accordhg to
eq.4.1, the junction area of the device SA125X is smailer than that of the device SAlX,
thus the magnimde of the junction capacitance CJE for the SA125X device is smalIer than
that of the SAlX device. The magnitudes of the CE for these devices wiil be given in
section 4.6.
Table 4.2 Effect of doping levels on the delay times obtained from vertical analysis
Table 4.3 Effect of doping levels on the delay t h e s obtained from laterai andysis
Doping Levels /cm3
ED' =6.0x10aD B D ~ =1.0x10'~ EPI3=2.8x1O"j
ED =3.Ox10" BD =1,0~10'~ EPI=2.8~10'~
ED =3.0x102" BD =1.0x1OX8 EPI=1.0x10'6
1: ED means emitter doping
2: BD means base doping
3: EPI means epitaxial coilector doping
Device Niune
SA125X S A ~ X
SA125X SAlX
SA125X SAlX
Doping Levels /cm3
ED =6.0x10m BD =l.OxlO" EPI=Ux 1 016
ED = 3 . 0 ~ 1 0 ~ ~ BD =1.0x10'8 EpI=28~10'~
ED =3.Ox1O2O BD =1.0~10'~ EPI=~.OX~O~~
te
Ps
0.160 0.160
0.209 0.203
0.198 0.193
Device Name
SA125X SAlX
SA125X SAlX
SA125X SAlX
G b
Ps
3.190 4.110
3.350 4.320
3599 4.070
h v o Ps
4.010 3.980
3.990 4.020
4.480 4.500
5gc Ps
0.020 0.023
0.031 0.034
0.031 0.033
%a Ps
0.295 0.244
0.304 0253
0.342 0.285
Tb
PS
2000 2.W
2098 2.065
2040 2.016
%CE
Ps
0.128 0.140
0.141 0.152
0.032 0.038
LI PS
1.7% 1.700
1 . m 1.600
2.300 2.300
%EE
ps
3.530 4200
3.600 4.360
3.400 4.220
PS
0.081 0.087
0.110 0-103
0.020 0.021
Ft GHz
19.98 18.58
19.80 18.11
19.28 17.60
Ft GHz
21-96 19.70
21.80 19.11
I
19.43 18.43
C a fF
29.05 29.28
28.32 29.62
31.00 31.92
& xlWS
, 0.720 0.735
0.709 0.728
1
0.699 0.709
4.4.2.1.2 Lateral Analysis
The lateral simulations are important because they represent the tme terminal
characteristics of the device. It is also interesthg to compare the results obtained h m
this analysis where the laterd effects were included to that obtained from the vertical
anaiysis where the lateral effects were neglected.
The simulation d t s of the lateral anaiysis of the two devices SA125X and SA1X are
presented in Table 4.3. The delay t h e s rEsc (due to the minority carrier charge in the
emitter-base space charge layer) and r, are 2-3 x10-l5 seconds and 6x10-l7 seconds
respectively, and thus can be ignorecl. The delay tirne s,, due to sidewall injection
diffusion capacitance, and the delay zR, due to C,: and total collecter series resistance
are aiso smail but are much larger than the delay times t~x: and tm. The dominant delay
times are due to the zAv0 and rrrn . These delays have already been discussed in section
2.7.2. It should be noted thaî the size of the device SA125X is slightly smaller than the
device SAlX, and therefore the total delay times of the former device are always shorter
than the latter device, thus its transition frequency F, is larger.
The result. obtained from the verticaI and lateral analysis, which are presented in Tables
4.2 and 4.3 respectively, are correlateci with each other. The delay tirnes tREE and r,,
obtained frorn the lateral analysis can be correlateci with the delays td and r,
respectively. The magnitudes of the delays s, and T, only are slightiy larger than the
delays r, and t, . This means thaî the lateral effects are insignifiant at the low coiiector
44
currents investigated here. The magnitude of the delay time tAvo was found to be higher
by 5-9 % than the magnitude of the sum of the four delay times T, T*, r, and s,. In
other words, the magnitude of the F, obtaùied h m the vertical analysis is higher by 5-Wo
than F, obtained from the lateral anaiysis. This relatively small difference between the
results of vertical and Iateral analysis can be explained in terms of sidewal1 capacitance
which is not taken into account in the vertical analysis. Emitter de-biasing [15,40]. which
could also cause ciifferences between verticai and lateral analysis, is not likely to be
important at the low coiiector currents considered here. For &= 200 pA, Ib= 1 @, so for a
base resistance of 200 9, V, at the center of the emitîer stripe is approximately 200 WV
less than at the edge. This difference in V, is negligible.
4.4.2.2 Effect of Transistor Size on the Delay Times
The influence of the device scaling on the delay times is presented in this section. Two
devices having different geometries, SAl25X25 and S15X15, were selected. The analysis
of the remaining devices was found to be similar, and so will not be repeated here. The
effect of device scaling on other transistor parameters will be discussed in section 4.6.
4.4.2.2.1 Verticai AnaJysis
The results of two devices SA125X25 and S15X15 are presented in Table 4.4. Table 4.4
indicates that the delay times, te T*, and r, are insignificant. The remaining delays are
similar to those results presented in Table 4.2 with the following ciifferences. The
magnitudes of al1 the delay times for aü the &vices of Tables 4.2 and 4.4, which had
45
different geometries, except the delay t due to the emitter-base junction capacitance, are
almosr independent of the transistor size. The s, was found to be strongly dependent on
the size of the transistor.
The preliminary venical analysis indicated that the device SA15X15. which hu the
smallest size among the devices listed in Tables 4.2 and 4.4, has the srnallest value of .r,.
The reduction in the r, can be atîri'buted to the reduction in the exnitter-base capacitance
CE The magnitudes of the junction capacitance CE for each device obtained from the
vertical analysis wiil be presented in section 4.6.
4.4.2.2.2 Lateraï Analysis
The simulation results of the lateral analysis for the devices SA125X25 and SAl5X15 are
presented in Table 4.5. The delay times s,, and t, (not shown in Table 4.5) are in the
order of (2-3)~10-*~ seconds and (5-8)x101' seconds respectively, and thus can be
neglected. The delay times +An and r,, are also insignificant. Thus, the remainuig
delays r,,, and s,are the main components of the total delay. Al1 these observations
are sunilar to those resuits presented in Table 4.3. The delay time t, which is related to
the s, in the vertical analysis is strongly dependent on the size of the transistor. It
decreaseâ as the dimension of the device decreased. This means that there is a
consistency between the results obtained from the vertical and l a ted analysis witb the
lateral resuits king more accurate than that obtained h m the vertical analysis. It should
also be noted that the magnitude of the delay time r,,, obtained from the lated analysis
46
Table 4.4 Effect of a transistor size on the delay times obtained h m vertical analysis
Doping kvels /cm3
Table 4.5 Effect of a transistor size on the delay times obtained from lateral aaalysis
Doping Leveis 1 km3 Ft
GHz
is in agreement with the prediction of eq.2.16 with minor differences e q d to about
5-9%. This difference is expected because there are several factors which are not taken
into account during the vertical analysis. The resdts presented in Table 4.5 also indicated
that the magnitude of the delay t,, is equal to (C,, /gJ, and this resuit is consistent with
eq.2.15 of chapter two.
4.5 E f f e of Doping Levels on tbe Ekctrical Characteristics
In section 4.4.1 the delay t h e in each region of the transistor was identified using hand
caicuiations. Several solutions were suggested to rninimize the delay tirnes. In this section
the BIPOLE3 program will be used to examine the results discussed in section 4.4.1. For
this reason, extensive investigations have k e n carried out in order to identify the best
doping levels which meet the required specifications that have k e n mentioned earlier in
section 4.2.
In order to fmd out the e f k t of doping levels on the transistor performance in a certain
region, it is required to change only the doping bels in that region. In the present
investigation, the doping level in the base was kept constant, and equal to l.O~lO'~/cm~.
The selection of the doping level in the base was not arbitrary, it was based on both the
hand calcuiations (section 4.4.1) and the preliminary simulation results. It was found that
increasing the doping level in the base reduces the base resistance and increases the Fm
significantly, but it degrades the F, because CE inmeases. This point has already been
discussed in the earLier sections.
The simulation results of the best doping levels, which meet the specifications, in the
emitter, base and coliecîor regions of the HBT are illustrated in Tables 4.6 to 4.9. The
analysis given in these tables is for 1X SAlX and NSAlX devices. These devices can be
fabricated using a simple process flow and the iithographic equipment available at
Gemum. For those devices having geometrîes different from the devices SAlX and
NSAlX, which are presented in Tables B.1-8.4 (Appendix B), it is also possible to
fabricate some of them using very fine adjusment during the alignment and lithographie
processes. The Tables B.l to B.4 contain information about the transistor parameters for
the self-aligneci and non-self aligned structures of various geometries. These Tables
indicate that there are several transistors which meet and exceed the required
specifications. Among the best performance transistors which significantly exceeds the
specifications was the SAOSX. This device, however, can not be made with the current
available equipment. The 0.5 pm poly-emitter stripe width of the device SAOSX can only
be defined using 0.5 pm Iithography equipment or an electron beam direct write
technique, which is currently available at Carleton University.
4.5.1 Emitter Doping Level
The results of simulations for SAlX and NSAlX devices are presented in Tables 4.6 and
4.7. The remaining devices are given in Table B.l of Appendix B. In Tables 4.6,4.7 a .
B. 1, al1 the parameters have their usual meaning except the following: %, is the extrinsic
base resistance, and (FJ;), and (Fm), are the peak values of the transition and osciliation
frequencies respectively. and (U, is the value of colledor current giving highest F,
49
The simulation results indicated that when the emiaer doping levels were changed €rom
6 x 1 ~ / c m 3 to 3x10rn/an3, the F, and Fm decrease accordingly. The main reason for these
changes is that the parasitic capacitances at the emitter-base junction CE was slightly
increased. The increases in the CE can be attniuted to the decrease in the width of the
depletion region &, since the latter depends on the doping levels according to eq.Al.l
(AppendUc A). However, the changes in F, and Fm were insignificant (- 1-295) and can be
neglected, Furthemore. there is a noticeable increase in the current gain P as a result of
the reduction in the emitter doping level. This result is in agreement with the Roulston
predictions [15], in that in simple theory is proportional to the exnitter doping level in a
vertical npn transistor.
4.5.2 Epitaxid CoUcdor Doping Level
The Tables 4.7-4.8 and B.2-B.3 (Appeadix B) indicated that when the doping level in the
collecter (epiwial layer, usually referred to as EPI) decreased h m 2.8x10L6/cm3 to
l.O~lO~~/crn~, the magnitudes of the following parameters are changed accordingly as
describeci below.
(1) Table 4.2 indicated rhat re and T, decreased by about 5% and 6% respectively.
whereas r,, increased by about 30%. h spite of these changes, the decrease of F, was
insignifiant.
Table 4.6 Heavy emitter doping
r, = 200 pA XJ, = 0.05 pm BV- = 6.0 V V, = 1.0 V XJ, = 0.1384 pn BV, = 18.7 V ED =6.0 xlOa cm-3 Wb = 0.045 prn Reach through = 4.19 V BD = 1.0 x1018 cme3 TEP1 = 0.59 pm Ge =IWO EPI = 2.8 x1016 cm-3
Parameters I SAlX SiGe
NSAlX SiGe
. . -. . -. -- - - - - - - --
Fm (GHz) 18.6 12.0, 14.0* 17.4
Rb (8) 190 190 620
R b (0 260 910,61W 150
CE 19.59 19.59 17.93
C J ~ (E) 4.52 4.52 2.9
* Underestirnates base resistance
+ Si-base doping profiles: ED = 3.0 x102' Wt = 0.05 pm SV, = 9.6 V BD = 4.0 x10 l8 cm" Xlz = 0.1398 ~III SV,, = 21.0 V EPI =1.0 x 10 l6 cm3 Wb = 0.07 pm Rach through = 4.19 V
TEPI = 0.59 pm
Table 4.7 Light emitter doping
I, = 200 pA XJ, = 0.05 pn SV- = 5.7 V Vk = 1.0 V XJ,=0.1381 pm SV, = 19.0 V ED =3.0 xlOm cm4 Wb = 0.045 pm Reacb through = 4.79 V BD = 1.0 ~ 1 0 ' ~ cm3 TEP1 = 0.59 pm Ge =IWO EPI = 2.8 x10 l6 cm-3
Parameters I SAlX SiGe
l NSAlX
I SiGe
* Underestimates base resistance
+ Si-base doping profiles: ED = 3.0 xlOm cme3 XJ, = 0.05 pm BD = 4.0 x 10 cm-3 XJ, ~0.1398 pm EPI =1.0 x10 l6 cm3 Wb = 0.07 pm
TEPI = 0.59 pxn
BV,, = 9.6 V SV,, = 21.0 v Reach through = 4.19 V
Table 4.8 Light erniüer doping, iight EPI doping
I, =200@ XJ, = 0.05 pm SV, = 7.5 V Vk = 1.0 V XJ2=0.1359 un SVh = 19.2 V ED = 3.0 x1O2' Wb = 0.045 p Reach through = 1.92 V BD = 1.0 x10 l8 cm-3 TEP1 = 0.59 pm Ge =IO% EPI = 1.0~10 l6 cm'3
* Underestimates base resistance
Parameters
F, (GHz)
Fm (GHz)
Rb (a) Rbex <a> CE (fF)
CJC (fF)
C,, (fF)
(m, (GB)
(F,), (GHz)
O p (PA)
P
+ Si-base doping profdes: ED = 3.0 xlOm cm" XIl = 0.05 pm SV,, = 9.6 V BD = 4.0 x10 l8 cm3 XJ2 =0.1398 pm SV,, = 21.0 V EPI =1.0 x1016 cme3 Wb = 0.07 pm Reach through = 4.19 V
TEPI=O.59 pm
SAlX SiGe
18
23
190
250
20
2.99
12.3
21.9
25.9
331
841
NSAlX SiGe
18
14.5, 17.1*
190
1300,dOW
20
2.99
12.3
21.9
16.1, 19.W
331
841
SA1X' Si
14.1 1
17.4
620
150
17.93
2. 9
10.8
17
20-3
597
127
(2) There is an appmiable increase in the Fm of the NSA devices due to the change in iîs
main components, CJc and the total base resistance (%+L). The decrease in the base-
collecter capacitance CJc can be amibuted to the increase in the depletion Mdih at the
coilector junction X, The increase in the total base resistance (%+L) of the NSA
devices is expected. It starts from the edge of the emitter poly and extends above the field
oxide up to the base contact.
(3) The breakdown voltage BV, is sispificantly increased from 5.7 V to 7.5 V, whereas*
the reach through voltage is decreased from 4.79 V to 1.92 V as a result of the decreasing
in the doping level of the EPI layer. Wolf [41] indiateci that when the epitaxiai layer
thickness is too small, under increasing reverse-bias voltage the depletion region of the
C-B junction wiil entirely penetrate the epitaxial layer before the predicted BV, voltage
has been reached. If the voltage is increased beyond this point, the depletion region must
enter the heavily doped buried layer, resulting in BV,, values smaller than those
predicted merely by the doping in the EPI layer.
(4) The percentage of the increase and decrease in the F,. Fm, P and other transistor
parameters fluctuating from one transistor to another depends mainly on the size of the
transistor. The most sensitive areas which affect the performance of the device are the
length and width of the field poly and the length and width of the emitter stripe mask.
Table B.2 (Appendix B) indicates that when there dimensions becorne smaller, the
performance of the device improves. because the parasitic capacitances and r e s i s m
54
are reduced. Furthermore, the mail geometq devices may nm at higher nirrent density
for a given collecter m e n t .
Table 4.9 shows another doping profile, where the doping levels in the coilector and the
base are similar to that presented in Table 4.8 except the doping level in the emitter was
increased from 3.0x1@'/crn3 to 6.0x1@%m3. The simulation results indicated that the
performance of the devices shown in Table 4.9 is siightiy improved, but is insignifiant.
It should be noted that the values of the current gain P depicted in al l tables are high.
According to Roulston [42], the author of the BIPOLE3 program, the values of should
be srnalier after fabrication than the numericaliy caiculated by BIPOLE3, partly because
the control parameters of the SiGe in the BIPOLE3 program were not fully established.
Also to be noted that, the cunent gain is strongly dependent on the minority carrier
lifetime in the emitter and surface recombination velocity [15], which is ciifficuit to
predict. because it is processing dependent.
There are rwo extra parameters left, which are not included in dl tables, the Early voltage
(VA) and the pinch sheet base resistance. Early voltages calculatecl h m BIPOLE3
simulations were fomd to be between 87-14 V. The fluctuations in the values of the VA
are due to the actual variation in the doping levels used during the simulations. For
example, the Early voltage of al1 the devices shown in Tables 4.7 and B.2 was found to be
87 V, whereas for the devices in Tables 4.8 and B.3, VA =140 V. Early voltage for
Si-base devices was found to be equal to 28 V. The pinch sheet resistance for al1 the
55
Table 4.9 Heavy ernitîer âoping, light EPI doping
I, =ZOO@ XJr = 0.05 pn BV,, = 7.7 V V, = 1.0 V XJ2=0.1362 pm BV, = 19.2 V ED = 6.0x10m cm-' Wb = 0.045 pn Reach through = 1.92 V BD = 1.0 x10 l8 cme3 TEPI = 0.59 pn Ge =lWo EPI = 1.0 x10 l6 cm-3
* Underes tirnates base resistance
+ Si-base doping profiles: ED = 3.0 xlOM cm" XJ, = 0.05 pm BD = 4.0 x10 l8 cm-3 XJ2 =0.1398 p EPI = 1.0 x10 l6 Wb = 0.07 pm
TEPI = 0.59 p
BV- = 9.6 V SV, = 21.0 v Reach through = 4.19 V
NSAlX SiGe
18.7
14.8, 17.7*
190
890,6ûW
19.57
2.79
12.3
24
16.8, 19.8*
466
619
Parameters
F, (GHz)
Fm (eh)
Rb (QI
R h (QI
CjE (fF)
C,, (fF)
CJ, (fF)
(FJP (GHz)
(FJP (GHz)
(up (PA)
P
SAIX' Si
14.1
17.4
620
150 I
17.93
2.9
10.8
17
20.3
597
127
SAlX SiGe
18.7
23.4
190
250
19.57
2.79
12.3
23.6
26.9
466
619
4
present SiGe-base devices were found to be between 1 1.8 Wsq to 14.1 Wsq, whereas
for the Si-base device, the pinch sheet resistance was found to be 19.9 Wkq.
The general conclusions for this section are given below:
1. The performance of most of the devices îhat are presenteà in Table 4.6 is slightiy better
than al1 of the devices presented in Tables 4.7 to 4.9, with the resuits of the devices
shown in Table 4.8 as a second best performance. This can be explained in ternis of the
appropriate selection of the doping levels across the transistor regions. Evidence for chat
can be seen from the performance of the devices shown in Table 4.6 as compareci to the
same devices shown in Tables 4.6 and 4.7. The emitter implantation time for the devices
shown in Table 4.6 is twice than that shown in Table 4.7, and may slow down the
production Modern implantation equipment using high m n t density may resolve this
type of delay.
2. Generally, al1 the simulation results presented in Tables 4.649 and part1 of Table 8.1
of Appendix B indicate that without exception. the performances of the SA devices are
betîer than the corresponding NSA devices simulated under same conditions. The
transition kequency F, of m a t of the SA devices is slightly lower than that of the NSA
devices, because CJc in the SA devices is slightly larger than that of the NSA devices.
This is due to the fact that the geometries of the SA devices are slightly different from the
correspondmg geometries of the NSA devices. Furthemore. the oscillation frequencies
Fm of the NSA devices are srnailer than that of al1 the SA devices, because the total base
resistance in the NSA devices is much larger than that of the SA devices, though the C,
57
in the NSA devices is srnaMer than that of the conesponding SA devices. Generally, the
magnitude of the total base resistance (% + R,) times C,= for SA devices is smailer than
for the correspondhg NSA devices.
3. The ciifference between the vertid and lateral analysis was found 5-!?%O, which is
insignificant. This means that the crowding effect [15.40] is negligible. This point was
discussed earlier.
4.6 Influence of Device Scaüng on the Electrical Characteristics
Earlier it was noted that the main challenge faced in the design of the HBTs reporteci here
was the need to deliver high performance at relatively low current density. In order to
investigate the effect of mask dimensions and consequently the size of a transistor on its
performance. severai SA and NSA HBT devices with different dimensions have been
designed and subjected to simulation. These devices are Listed in Tables B.1 to B.4 of
Appendix B. Additional detail on the dimensions of these devices is given in Table 4.1.
In these devices the emitter mask length (EML) was reduced from the normal length (3
pm) to 2.5 pm, 1.5 psn, and 1.25 p. The emitter width poiy (EWP) was also reduced
h m 1.5 pm to 1.25 p. As a result of these changes the remaining device geometry for
each device was reduced accordingiy.
The devices listed in Tables B. 1 to B.4 were simulateci under various doping levels.
Among the Listed devices is the self-aligned device SAOSX , which has the best
performance compareci with the remaining devices. This device has F,= 26.2 GHz and
58
F e 37.2 GHz as shown in part1 of Table B.1. The superiority of this device can be
aitributeci to the significant decrease in the htrinsic base-resistance & and the parasitic
capacitances, especiaily at the emitter-base junction CE.
The feature of the devices presented in the Tables B.1 to 8.4, is that the capacitance of aU
the SA and NSA devices at the emitter-base junction CE is much smailer than the CE of
all the devices presented in Tables 4.64.9 simulateci under similar doping levels. The
reduction in the size of these devices reduces the parasitic resistances and capacitances,
and lads to irnprovement in their performance. It should be noted that Table B.3
indicates that Ft and Fm for 2=2W @ for sorne devices are below 10 GHz. However, the
peak values of the F, and Fm , which are located at 4= 97 to 139 pA for such devices
were found to be above 20 G H z This would suggest that this type of devices are only
usehi for very tow power applications, specifically for I, < 200 pA.
The simulation results presented in Tables B.1 and B.4 indicate that as the emiaer doping
ievel increases the performance of the device is enhancd These results are consistent
with the results pfe~ented in section 3.7 and ülustrated in Tables 4.6-4.9. Generaily, the
influence of doping levels on the performance of ail the devices presented in Tables B.1
to B.4 are similar to those devices presented in Tables 4.6 to 4.9.
The general conclusion to this section is given as foliows: The length rad width of the
field poly, length and width of the emitter stt5pe were found to play important role on the
59
performance of the device. As these parameters becorne smaiier, performance of the
device is significantly improved. This is due to the reduction in îhe &, CE and CJc
combined with the requirernent for operaiion at I, = 200 pl.
4.7 Simulation R d t s of an Si-Base Dence
It was found usehi to compare the simulation resulrs of the SiGe-base devices with the
corresponding Si-base, to justify the contention that the SiGe-base devices have superior
performance relative to the Si-base devices. One of the npn 1X self-aligned devices was
chosen for this task. The result of the simulations are presented in the thbd colunin of the
Tables 4.6-4.9 and last row of the Tables B.1-B.4. Without exception, the performance of
al1 the SA and NSA SiGe-base devices are much better than the Si-base devices.
Evidence for that can be seen, for example, in the total base-resistance of the SiGe-base
devices being much srna.Net than the comesponding resistance in the Si-base devices. The
current gain of the SiGe-base devices is much higher than for the Si-base devices, and
this result is consistent with eq.2.1. The Early voltage was found to be equal to 28 V for
the Si-base, cornpared to 87 to 140 V for SiGe-base devices.
Ln order to explain the difference between the performance of the Si-base and the SiGe-
base devices, the contribution of each delay in the F, of the Si-base devices should be
deterrnined Vertical and lateral simulations were carried out, and the results are
iiiustrated in Tables 4.10 and 4.1 1. For the pirpose of the cornparison, the simulation
results of the SiGe-base of the SAlX device are repeated in Tables 4.10 and 4.1 1. During
60
the simulation, it was found that in order to avoid the base punch through, the width of
the quasi-neunal base should be made equal to 700 A, and the doping level in the base
shouid be equai to 4x1Ol8 /cm3. This doping is four Urnes higher than for SiGe-base
devices. It should be noted that the Si devices have a diffuseci base and thus the doping is
non-uniform across the base and bas a Gaussian profile, whereas in the SiGe devices tbe
doping is graded unifomily across the base. W u s e of these ciifferences. cornparison
between the simulation results of the Si-base and SiGe-base devices wiil be qualitative.
The simulation r d t s presented in Tables 4.10 and 4.11 can be summarized as follows:
(1) There is full agreement for F, obtained from vertical and lateral analysis. This means
that the lateral effects are insignificani-
(2) The delay t h e t, in the neutral emitter is much larger in the Si-base than that of
SiGe-base. According to eq.2.7, the 5 is proportional with the base width Wb and the
width of the Si-base is rnuch larger than the width of the SiGebase devices as m e n t i o d
earlier.
(3) The emitter-base junction charging tirne r, is the dominant delay. It is about 8%
Iarger in Si-base than that of SiGe-base.
(4) The delay due to a free carrier charge in emitter-base space charge s,, is much larger
in Si-base than in Siûe-base devices. According to Roulston [15], the delay t,, is
proportional with 1&. Since is proportional to I, and P in Si-base devices is much
smaiier than f3 in SiGe-base devices (Tables BI.-B.4). thus the delay r,, should be higher
in Si-base compared to SiGe-base devices.
61
(5) The delay time in îhe base r, of Si-base devices is les than half of the delay in SiGe-
base devices. This wodd suggest that the r, is not an important delay for Si-base devices.
This result is inconsistent with the essence of eq.2.2, where the ratio of s,,, /s, is l e s
than unity. The inconsistency can be explained in tenns of the doping profile in the base
of both the Si and SiGe devices- As mentioned above, the doping profile in the SiGe
devices is unifonn across the exnitter, base and collecter, and does not obey a typicai
Gaussian profile. The base in the Si device has a non-unifomi pmfüe and follows the
Gaussian profile. This wodd suggest that when a reverse bias is applied across the
coliector, the depletion region at the base-coiiector junction WU enter the quasi-neutral
base region. In consequence, the thicbias of the base wül reduce and thus allow the
carriers to reach the coiiector much faster and the t, will becorne shorter. The drawback
of this feature is that the Si devices will suffer from low punch through, and this
significantly reduces the Early voltage. This conclusion is consistent with the present
results, where the Early voltage was found to be much larger in SiGe-base devices than
that in the Si-base devices.
(6) The transit time due to coilector space charge layer r,, is aiso signifiant, and is about
8% larger in Si-base than in SiGe-base devices.
(7) The coilector charging t h e rd is insignificant (=0.01 ps), thus it can be neglected.
(8) Table 4.1 1 shows that the deiay tAVo is about 29% higher in Si-base than in SiGe-base
devices, because the delays se and 7, which are part of the delay sAvo are much larger in
Si-base than in SiGe-base devices (Table 4.10).
Table 4.10 Delay times for Si-base devices obtauied from vertical analysis
Table 4.1 1 Delay times for Si-base devices obtained from lateral analysis
Doping Levels /cm3
ED =3.Ox1O1O BD 4 . 0 ~ 1 0 ' ~ EPI=1.0~10'~
ED =3.OxlO 1 SAlX: SiGe 1 0.193 1 4.07 ( 0.03 1 2.02 1 2.3 1 0.02 1 18.43
Device Nvne
SAlX: Si
Doping kvels /cm3
ED =3.0x10a BD =4.0~10'~ EPI=1.0x10'6
PS
1.821
ED =3.ûxlO " BD =l.Oxl0la 1 SAlX: SiGe 1 4.5 1 0.29 1 0.04 ( 4 2 2 1 17.6 1 31.92 1 0.709 EPI=l.o~lo'~
Device Name
SAlX: Si
'AVO
Ps
6.35
2,
Ps
4.46
S~~
PS
0.24
Te PS
1-54
=*EE
ps
4.61
T~~
PS
0.03
4 Ps
0.91
Ft GHz
14.16
%A
Ps
2.5
C m fF
44.89
& xlWS
0.693
*a
Ps
0.01
FC GHz
14.16
4.8 General li.ansistor CharadtFistics
Figure 4.4 shows a typical shuiation of the uniforni vertical profile for the SAlX and
NSAlX of the SiGe-HBTs. This structure bas an ernitîer doping level of 3 x l P /cm3 at
the poly/mono interface, a base doping level of 1 x 1 0 ~ ~ /cm3 and an epi-layer that has a
doping Level of 2.8~10'~ /cm.). The Ge content hot shown in Fig.4.4) is rarnped fiom O to
10% across the base. The spacers at the emitter-base and base-collecter regions are also
not shown in Fig.4.4, becawe BIPOLE3 program cadt provide simulations for the
spacers.
A typical Gummel simulation plot for the SAlX and NSAlX of the SiGe-HBTs at
V, = 1 .O V is shown in Fig.4.5. The emitîer area of the device shown in Fig.4.5 is
l.5x3.0 pl2.
Figure 4.6 shows a typical plot of the 1, versus the collector-emitter bias (V,) for SAlX
and NSAlX SiGe HBTs. The simulations were conducted at different values of I, h m
0.2 pl to 0.5 pA. The simulation resuits indicated that the emitter-to-collecter
breakdown voltage BV- at V, = 1.0 V is 5.7 V. The base-to-collecter breakdown
voltage is 19.0 V. The Early voltage for the device shown in Fig.4.6 is 87 V.
High frequency performance variatioas with device geometry and doping for SiGe-HBTs
have been discussed in sections 4.4 to 4.6. Typical transition frequency F, and maximum
frequency of oscillation Fm versus coiiector -nt I. at V, ~ 1 . 0 V. are shown in Fig.4.7.
64
Figure 4.7(a) demonstrates the high performance of the SA device, where F, and Fm have
peak values equd to 26.5 GHz and 23.7 GHz respectively at I, = 948 pA. In the NSA
device shown in Fig.4.7 (b), the F, and Fm have peak values equal ta 25.3 GHz and 14.5
GHz respectively at I, = 941 pA. The significant decreases in Fm is due to the increase in
the extrinsic-base resistance of the devices.
Net Doping vs Depth 1E21,
0.1 0 2 0.3 Depth (microns)
Figure 4.4 Typical sirnulated irnpurity profile for SAlX and NSlX of SiGe HBT
Gummcl Plot
Figure 4.5 Typical sirnulated GurnmeI plots of base and collecter currents for SAlX and
NSlX of SiGe HBT
Figure 4.6 Typical simulateci L-V, characteristics for SAlX and NSlX of SiGe HBT
1E-M lm
(a) SAlX
lEOd 1- 0.0001 0.001 0.01
(b) NSAl X Ic (A)
Figure 4.7 Simulaied F, and Fm as a function of I. for SiGe HBT
CHAPTER 5
DEWCE FABRICATION AND CHARACTERIZATION
5.1 Introduction
This chapter describes the pfocessing experiments camied out to realke the SiGe HBTs
designed in chapter 4. The strategy followed in developing the new SiGe HBT
technology was to keep the process architecture as close to existhg Gennum BJT
technologies as possible, making modifications on1 y when necessary . The main
modifications required were the development of three new process modules: field poly
formation, SiGe base deposition and local interconnect fornation In addition, some
rninor modifications to layer thickness and annealing conditions in the baseline BJT
technology were found desiraMe to optimize device performance. The majonty of the
processing experiments were carrieci out in Gemum's fabrication luie in Burlington,
Ontario. Some additional experiments were completed in Carleton University's
Microelectronics fabrication facility. In order to protect information proprietary to
Gemurn, no details on the baseline BJ'T process flow on which the SiGe base was grafted
will be given here.
5.2 Test Wafer Layout
Before processing could begin, it was necessary to genemte a complete test wafer layout,
including passive devices, transistors designed for DC measurements and transistors in
special pad frames intended for high frequency AC s-parameter measurements. For the
passive components, it is required to design a test structure in order to be able to measure
the sheet resistance, the capacitance, and the linewidth for most of the device layers. The
main objective is to ensure that the values of the device parameters are within the
required specifcations. Four point van der Pauw structures [43] were used to measure the
sheet resistance, whereas four point Kelvin structures were used to measure the linewidîh
of each layer.
The layout was accomplished using the L-Edit program. It was f i necessary to prepare
a new L-Edit technology fle describing the SiGe HBT process. including design des .
M i l e laying out acnial transistors, dimensions were minimized in accordance with these
design d e s to minirnize parasitic capacitance.
5.3 Short Loop Expeiiments
The purpose of the short loop (preliminary) experiments is to opumize the conditions of
the depositions, etchïng, diffusions, oxidations and Lithography. For example, in the
process integration, the thickness and the concentration of the epitaxial coliector are
important parameters which determine the breakdown voltages of the bipolar transistor.
These parameters should be selected in such a way to meet as closely as possible the
device specifications.
In order to integrate a new process module in an existing tecbnology, it is necessary to
perform short loop and mechanid experiments in order to be able to identify and
70
optimise the process under investigation mtil it meets the specificatioh The short loop
and the mechanical experiments can be regarded as preliminary experhents. The
meaning of the short loop experiments can be elucidated by the foilowing example. If a
specific thickness of an oxide layer is required to be grown on a certain layer, then the
annealing temperature and deposition time should be optimised until it mets the
specification. A mechanical expriment is one intended to establish device structures
(such as layer thickness, etch parameters, etc.) without providing eleceical test rrsults.
Thus, from the short lmp and mechanical experiments, we can obtain optimiseci
conditions before we start full-wafer processing.
In the present work, we have performed several short loops and mechanical experiments
for the SiGe HBT technology. Three new modules have been developed, and the feature
of each process for each new layer are discussed below. The remauillig process modules
of the new HBT technology are cornrnon to other Gemurn technologies. The new
modules are as foliows:
1. Field poly module
2. SiGe deposition module
3. Local intercomect module
Each module consists of two or more process steps. Rocess details for each module are
given below.
5.4 Field Poly Module
The UHV/CVD method for SiGe deposition requires an unusual precleaning procedure in
which the substrate is dipped in a u t e hydrofluoric acid and then removed without any
rime step. This procedure passivates dangling bonds on the Si surface with hydrogen.
Since bare siiicon is strongiy hydrophobie, a wafer slowly pulied h m hydrofluoric acid
solution will emerge in a compietely dry condition. This cleaning procedure can also be
applied to wafers with pattemeci oùdes on their surlaces (as would typicaîiy be the case
in a full process) providecl l e s than 15% of the surface area is oxide. To achieve l e s than
15% oxide surface coverage in a commercial bipolar process, it is necessary to coat most
of the wafer surface with a sacrificial polysilicon layer that wiil be referred to as 'field
poly".
Apart from being essential to the UHVKVD precleaning process, the field poly offers
advantages to the HBT process flow. For example, the structure of the deposited SiGe on
the field poly is different h m the structure of the SiGe deposited onto an oxide layer,
because the former substrate has a polycrystalline stmcture whereas the latter substrate
has an morphous stnicture. Since the nature of the substrate has an influence on the
growth of the deposited layer, it is expected that the sheet resistance of the SiGe
deposited on the field poly, to a certain extent, is slightly l a s than that of the SiGe
deposited ont0 the field oxide. Furthemore, the thexmal expansion coeff~cient of the field
poly should be closer to the thermal expansion coefficient of the SiGe than the thermal
expansion of the field oxide. This means the thermal stress arising h m the ciifference in
72
the thermal expansion of the film (field poly) and that of the substrate (field oxide) will
be much less in the case of the field poly surface than in the field oxide surface. Themal
stress results from the difference in the thermal expansion coefficients of the film and the
substrate when the fihdsubstrate is cooled from a high temperature to room temperature.
Consequently, the sheet resistance of the SiGe layer on the field poly will be less than
that on the field oxide. This feature is especially important for the non-self aligned HBT,
because in this architecture the resistance of the field poly is part of the total extrinsic-
base resistance of the transistor base. This point was discussed in chapter 4. Most
important, in the present technology, the width of the field poly defines the single crystal
SiGe region of the self-aligneci transistors.
The process module for field poly formation consists of the following eight steps:
1. Pre-field poly ciean and field poly deposition
2. Field poly cap oxide
3. Field poly implant
4. Field poly anneal
5. Cap oxide etch
6. Field poly mask
7. Dry poly field etch
8. Field poly mask resist strip
Cross sectional views aaoss a poly f i ge r after each of the above steps are given in
Fig.S.1 ( a d . A brief description of the above process flow follows. Wafers are f i t RCA
73
cleaned and then loaded hm a low pressure chemicai vapour deposition (LPCVD) tube.
Fig.5. la shows the field poly layer deposited ont0 the field oxide. The deposition
conditions of the pdysilicon were obtained from the short loop experiments. After
deposition, the wafers were inspectai in a high intensity light to ensure that they appear
unifoxmly free from any defects such as streaks or haze. Following this step, the cap
oxide (500 A) was thermdiy grown on the field poly by means of wet oxidation using
predeteded conditions (Fig.S.lb). Next, ion implantation was used to implant boron
(B') into the field poly through the cap oxide, using an energy of 30 keV and a dose of
3x 1 015 ions/cm2 (Fig.5. lc) . After ion implantation, the wafers were pre-diffusion cleaned
and fumace annealed at 950 OC for 40 minutes (Fig.5.ld). Followïng the drive-in, the cap
oxide was removed using a plasma etch. The field poly inside the active region was
etched using a plasma dry etch, based on the results obtained ftom the short Ioop
experiments (Fig.5-le). Finaily, a poly mask resist strip (using an oxygen plasma ashing
process) was perfomed to conctude the field poly process.
The cap oxide serves two functions. First, it blocks the implanteci B-impurity from
evaporation from the field poly layer during the field poly anneal process, and thus
reduces its sheet resistance. Secondly, it reduces the defects on the surface of the field
poly resulting h m the boron implantation darnage, and aiiows a higher implant energy
to be useci. With increasing implant energy, the dopant penetrates deeper and becornes
less sensitive to severai sources of process variation It should be noted that the gmwth of
the cappïng oxide onto the field poly consumes part of it. According to Wolf [Ml, the
74
i Field Poiy ' < . . . Field.Polv. 1
(a)After field poly deposition
@)AAer field poly cap oxide
(c)After field poly implant
Figure 5.l(a-c) Schematic cross-section of the field poly process sequence of the SiGe
HBT
(d)AAer field poly anneal & cap oxide etchback
LThin Oxide . - .
n-epi . .
(e) Mer field poly maswetch
Figure 5.1 (de ) Schematic cross-section of the field poly process sequence of the SiGe
HBT
oxide consumes silicon to a depth of about 0.44 bX , where t, is the grown oxide
thickness. For t, -500 A. the siiïcon consumption was found to be equal to about 220 A.
The consumption of silicon resulting h m growth of the capping oxide was taken into
account during the field poly deposition.
A Iarge set of samples of field poly layers has been prepared under various conditions. A
summary of the resuîts for these sarnples together Mth theu conditions is given in Table
5.1. This table shows effects of various parameters on the sheet resistance of the field
poly. Including are thickness of the field poly, implantation types and theù doses and
energies, annealing tirne and temperature and fmaily capping of the field poly. To assess
quantitatively the effect of these panmeters on the characteristics of the field poly, a
comprehensive microstmctural analysis is required, which is beyond the scope of thk
thesis. The main feature of the results presented in Table 5.1 can be explaineci as foliows.
Table 5.1 indicates that the sheet resistance R, of the field poly is inversely proportional
to the film thickness. Also to be noted is that, the opticai microscope examinations
indicated chat when the annealhg temperature is raised to 1000 OC, most of the wafers
become hazy. This problern û more pronounced for uncapped sarnples annealed at 1000
OC . However, this type of pmblem completely disappeared when the annealing
temperature was r e d u d to 950 "C. It is expected that the high temperature annealing
process causes vertical grain growth of the field poly. which enhances the roughness of
the interface, giving haze [45].
Table 5.1 Summary of the field poly resuits
Implant Energy No. keV
Annealing Oxide R, T i Temp cap min OC
*: Means the wafer was hazy
Table 5.1 also indicates that when a BF, implant is used, the sheet resistance of the field
poly becornes less than when B+ is implanteci. Unfortunately, the presence of the fiuorine
(frorn the BF, implant) may enhance boron peneaation through the oxide layer into the
underlying substrate. The spreading resistance analysis indicated that when BF, was used
the boron penetrates to the underlaying substrate through the oxide layer. Elementai
boron is therefore considerd to be superior to BF2 as an implant species to dope the field
P ~ Y -
According to the above analysis, the optimized conditions for preparing the field poly are
to cap it by an oxide, then implant it with B+ with a dose of 3x1015 ionslcd using an
energy of 30 keV, and finaliy fumace anneal it at 950 OC for 40 minutes. It should be
noted that, during the emitter processing, it was found that thickness of the field poly
should be less than 2000 A in order to reduce the emitter stringers.
5.5 SiGe Base Deposition Module
The SiGe base module consists of two processes given bdow.
1. SiGe Deposition
2. Sacrificial low temperature oxide deposition (S AC-LTO)
The SiGe Iayer was prepared using a UHVKVD technique in a 'Sirius" hot wall reactor
from Leybold AG. This system is very s M a r to that developed by Meyerson [ t O ] .
Before SiGe deposition, the thin oxide, which covered the opening of the field poly in the
nepi region, was etched away (Fig.5.h) mtil the surface became hydrophobie. Next, the
79
wafers were loaded immediately in the UHVKVD chamber for deposition of the SiGe
layer (Fig.5.2b).
On the basis of simulations with a version of SUPREM3 calibrateci for use with SiGe
base regions, the group responsible for growth of the SiGe epitaxial base recomended
the insertion of additional buffer and spacer layers on the emitter and collector sides of
the base. The SiGe s c h e stans by depiting a 200 A siiicon b&er layer onto the
epitaxial coiiector layer at the base-coliector region. This layer, which is an extension of
the existing field poly layer for the non self-aligned stnicture, is useful because it
decreases the sheet raistance of the field poly, and it covers any surface roughness chat
may axise from the previous process steps. Following the buffer layer, a 100 A spacer
layer of undoped SiGe ( l a G e ) is deposited onto the previous silicon layer. The main
purpose of this layer is to accommodate the outdiffusion of boron from reaching the
collector during annealing of the field poly or emitîer poiy. The surface of this layer is
very clean, free from any owde or con tamination, and can be regatded as an excellent
nuc!eation suxface for the next doped and graded SiGe layer. Then, the main layer of 700
A of graded SiGe (W6-1096) dopeci with boron of concentration of 1x1018 atoms/cm3 is
deposited. Finally, a 400 A deposition of undoped silicon spacer above the previous layer
at the base-ernitter jmction was performed to finish the structure. The feature of the
spacer is to prevent arsenic out-diffusion from the ernitter h m reaching the base.
Additional benefit is to ensure that the SiGe is not oxidized during the emitter poly
annealing. It has been found that the presence of a smaii amount of Ge during sificon
80
oxidation process enhanced the oxidation rates 1461. In addition the Ge was found to be
segregated to the growîh interface during oxidation. Pile-up of Ge at the interface is likely
to lead to a leakage under electrical stress. In order to control these effects. the presence
of the undopeci spacers whether Si or SiGe at the baseemitter or base-coUector junctions
serves as a sacrificial layer for preventing oxide growth The spacer also helps d u c e the
emitter-base junction capacitance. because the emitter pol y, which has the highest doping
concentration, is not deposited directiy on the doped and graded SiGe layer. Furthemore,
the spacers also dlow for dopant diffusion during the ernitter anneal. It shodd be noted
that the Ge profile was rarnped h m W o at the emitter-base junction to 10% at the base-
collecter junction. The Ge and boron profiles were chosen to o p h i s e the required F, and
other transistor parameters.
The final step in the SiGe process is to deposit a sacrificial low temperature oxide
(SAC-LTO) layer on the wafers to pmtect the SiGe base from photoresist d h g the
local intercornet patternhg (Fig.5.2~). The thickness of the SAC-LTO was between
1300 A to 1700 A. The SAC-LTO wiii be etched away in the later stages.
In the self-aligned architecture, the SiGe layer under the emitter poly has a single crystal
structure and detennines the intrinsic base-raistance, whereas the SiGe in the silicided
region determines the extrinsic base-resistance. In the non self-aligned architecture, the
extrinsic resistance has three components. The first i s the resistance of the SiGe h m the
edge of the emitîer poly to the edge of the field poly inside the base active region (the
81
(a) After cap oxide etch
I
(b) After SiGe deposition
- - - - -- -
(c) Mer SAC-LTO deposition
Figure 5.2(a-c) Schematic cross-section of the SiGe process sequence of the SiGe HBT
SiGe in this region has a single crystal structure). The second is the resistance of the
SiGe/field poly stack from the edge of the field poly inside the active region to the
silicided region outside the field poly region (the SiGe in this region has a polycrystaliine
structure). The third component is due to the resistance of the silicided region comeaing
to the contact, and the SiGe layer in uiis region has a polycrystalline structure.
5.6 Local Intciconncct Module
As mentioned above, SiGe gram over field poly has a polycrystalline structure, whereas
the growth of SiGe in the epitaxial Si-base has a single crystal structure. We refer to the
field region where the SiGe has a polycrystalline structure as a local intercomect. Both
structures are comected with each other as if there is one wntinuous conducting layer.
The local Uitemmect is made up of SiGe overlying field poly. The local interco~ect is
silicided later in the process flow for both self-aligned and non-self aligned architectures.
For both self-aligned and non-self aligned architectures, the base contacts were placed on
local intercomect regions outside the base active region. The local intercomect process
module consists of five steps:
1. Local intemnnect mask
2. Sacrificial LTO etch
3. SiGe and field poly etch
4. Local interco~ect resist strïp
5. Sacrificial LTO etchback
(a) After ld-interconnect rnasWetch & S i M e l d poly âry etch
(b) AAer photoresist strip & SAC-LTO etchback
Figure 5.3(a-b) Schematic cross-section of the LOC-INT process sequence of the SiGe
HBT
The process flow starts by masking the wafer using the local intercomecî mask
(Fig.5.3a). Next, part of the sacrificial LTO on the field poly is removed using a BOE
(buffer oxide etch) wet etch, followed by removal of the underlying SiGdfield poly stack
using a plasma dry etch (Fig.5.3a). Fig5.3a shows a lateral etch taking place resulting
from the isotropie nature of the wet et& The adverse effects of the lateral etch at this
stage is not important because physically it does not affect other layers on the wafer. The
next step is to saip the photoresist using the oxygen plasma etch. Finally, the sacrificial
LTO is rernoved using a wet etch method (Fig.5.3b) and this fùiishes the local
intercomect pmcess flow module.
5.7 Rapid Thermal Emittcr Anntaling
The technique of rapid thermal anneaiing (RTA) is becoming widely applied in the
serniconduc?or industry and serves, among other tbings, to minimize the diffusion
between a film and the substrate or between the layers of a device. This technique can
activate the dopant in a few seconds with minimal redistriiution, compared to minutes in
a conventional fumace annealing, which substantially broadens the profde. RTA is
therefore desirable as a means of activating the emitter implant in SiGe B T S .
To calibrate the existing rapid thermal annealing AG Associates Heatpulse 210 System
[47], the following procedure was adopted. Boron was implanted into n-type <100>
wafers using an energy of 35 keV and dose of 5x1015 ions/cm2. These implant conditions
were chosen to produce a layer in which sheet resistance is a strong function of anneal
85
temperature for temperatures close to 1025 O C . Immediately prior to introduction into the
Heatpdse chamber, wafers were given an RCA type clean ending with a dip in 10:l
H,O:HF to remove any interfacial oxide. Several tests were conducted on a test wafer to
establish the annealing conditions. Argon gas was used during the annealing cycles.
Finally, the real wafers were introduced into the RTA chamber and annealed individually
between 945 O C and 1070 O C for 10 seconds.
The sheet resistance of each wafer was measured ushg the four-point van der Pauw
method. The measured sheet resistances were found to be between 2û and 81 Wsq, and
these values correspond to a temperature range between 1070 OC and 945 OC at the wafer
centre. The results of the calibration are given in Table 5.2.
In the present work, the emitier poly anneal was the only signifiant thermal step
following SiGe base deposition. It was c h e d out using furnace annealing at 850 O C for
20 minutes, followed by RTA in argon atmosphere 970 OC-1000 OC for 20 seconds. The
wafers were RCA cleaned and dipped in HF acid solution before RTA as describeci
above. For some additional wafers the emitter was exchsively fumace annealeci at 900 O C
for 20 minutes.
Table 5.2 Variation of sheet resistance with temperature
T,: Heatpulse preset temperature
T,: Wafer temperature
p: Wafer sheet mistance
5.8 Device Chamderistics and Discussion
This section describes the DC and AC measurement results provided by Gennum for 1X
self-aligmd and non-self aligneci SiGe HBTs. The doping Ievels in the ernitter. base and
epi-layer are 3xlP /cm3, 1x10" /cm3 and 1 ~ 1 0 ' ~ /cm3 respectively. The Ge concentration
is rampeci from O to lWo across the base. More details on the SiGe deposition conditions
were given in section 5.5.
5.8.1 DC Characteristics
Gummel plots of collector and base currenu are shown in Fig.5.4 for self-aligned
(Fig.5.4(a)) and for non-self aligned (Fig.5.4(b)) SiGe HBTs. Figure 5.4 indicaîes good
constancy of current gain down to a very low current with the non-self aligned HBT
being the bat. The 1-V behaviour demonstrates the quality of the epitaxial material used
and highlighting the low current capabilities of the SiGe HBTs process. This means that
the metastable strained SiGe layers can withstand some high-temperature processing
wi thout deleterious electrical effects.
Variation of collector current with collecter-emitter voltage for different base currents for
SiGe HBT (SA and NSA) is shown in Fig.5.5. This figure shows the emitter-coUector
breakdown occurs near BV, = 7 V, which considerably exceeds design targets.
From the experiment, it was observed that the current gain P for the NSAlX device is
equal to 385 at a coilector current 4~200 pA. The high experimental value of P was about
half of the predicted value by the BIPOLE3 program. The e m e n t a l value of P as
88
0.0 1 Gumrnel Plot
05 0.6
(a) SAlX
Figure 5.4 Experimental coliector and base cunents versus base-ernitter bias for the SiGe
HBT
O 1 2 3 1 5 6 7
(a) SAlX vce O
Figure 5.5 Experïmentai collecter current versus coiiector-emitter bias for different base
currents for the SiGe HBT
compared to BIPOLE3 strengthens cod~dence in the accuracy of the sirnulator. However,
the difference in the numerical value of P may be atîributed to the foilowing factors: (1) $
is strongly process dependent and (2) the BIPOLE3 program was not calibrated. Taken
into account that p is known to be strongly process dependent, and the BIPOLE3 program
was not calibrated. the experimental value of P as compared to BIPOLE3 is encouraging.
5.8.2 AC Characteristics
The frequency response of the SiGe HBT was evaluated by meamring s-parameters using
a high frequency network analyzer in conjunction with a Cascade RF wafer probe. After
correctkg for the effect of the pad capacitance, the transition frequency F, for the SAlX
and NSAlX SiGe HBTs measured at a coiiector current I, = 200 were 12.2 GHz and
13. l GHz respectively. The doping leveb for the fabricated devices were as foiiows:
Emitter doping=3x 1 020/cm3, base doping=l xl OIS/ cm3, and epitaxial coiiector doping
=1xl0l6/cm3. The transition frequency dependence on the coiiector current is shown in
Fig.5.6 for both SAlX and NSA lx devices. The difference between the simulated and
experirnentai values in the F, is given below.
The simulation resuits of the SAlX and NSlX devices, which had the same stmcture as
the fabricated devices except for the base width Wb (Table 4.8). indicated that the F, is
e q d to 18 GHz at I, = 200 pA and V, = 1 V. The disagreement between the simulated
and experimental results may be due to ciifferences in the base widîh. Specificaliy, the
simulation results were baseâ on the neuesl base width k ing equal to 450 A. There is as
91
Figure 5.6 Measured transition frequency versus collecter current for the SiGe HBT
yet no experimental measmement (either secondary ion mass spectroscopy (SIMS) or
spreading resistance profde (SRP)) providing information on the base width of the
experirnentai devices. In the presence of boron out-diffusion from the base into the
surrounding spacer layers, the thickness of the neuuai base might be expected to be as
much as 700 A. When the simulations are repeated for a base width equal to 700 AT the
transition frequency F, was found to be equal to 15.2 GHz at I, = 200 pA and V, = 1 V
for both SAlX and NSlX devices.
The analysis of the total delays reveaied that the delay across both the neutrai emitter r,
and neutrai base rb is about twice in the case of Wb =700 A than Wb =450 A. Taken into
account that BIPOLE3 was not calibrated, and was not an ideal sirnulaior (as was
discussed in chapter 4 for our devices, especiaily for non-self aligned devices), the
simulation and experimental results are in good agreement. On the other hand. if we
assumai that outdiffusion of boron occurrecl, which will be trapped by the spacers, the
thickness of the base will increase. This means that if the sùnulations are repeatd again
for a base width larger than 700 A, the simulation results wiil become very close to the
experimental resdts.
In the case of the self-aiigned devices, in addition to the problem of the base width
discussed above, there are additional factors which have signifiant impacts on the F, and
other transistor panmeters. niese include the consequences of overetching during
patterning of the emitier poly and emitter poly oxide sidewd spacer, and the presence of
93
an emitter polysilicon Stringef on the field poly sidewall. The goal of the plasma etch
step which defmes the emitter stripe is complete removal of the ernitîer polysilicon h m
regions not protected by photoresist without damage to the underlying SiGe base layer. It
is difficult to device a plasma etch chemistry which attacks polysilicon yet does not etch
SiGe aiioy with Ge content of a few percent. (Recall that the Ge content is graded across
the base, rising from 0% at the emitter-base junction to 1Wo a the base-collecter
junction). The problem is compounded by inevitable cross-wafer and wafer-to-wafer
variations of IWO or more in etch rate in commercial plasma etchers. A similar problem
arises during formation of the oxide spacer on the emitter sidewd that is required for the
dicidation proces. The latter problem is improved somewhat by the relatively
selec tivity achievable between oxide and d icon in plasma etching.
Reducing the thickness of the SiGe base in the region between the emitter and the field
poly may lead to a situation in which the base is completely consumed during
dicidation This will create a Schottky diode in the extrinsic basecollector junction
Although this is not entirely undesirable (the diode acts as a Schottky clamp, preventing
saturation of the base), it may lead to considerable variation in base-coiiector junction
characteristics from device to device.
The emitter stringer results from the anisotropic nature of the etch used to pattern the
emitter. Etches of this kind kave deposits on the sides of vertical structures. Since the
ernitter polysilion is patterned before the emitîer anneal, the smnger is likely to be
94
undoped. Further. the stringer is W<ely to be completely converted to M i during
silicida tion, slightly reducing base resiotance. Unfortunately . at the place where the
emitter stnpe intersects the field poly sidewall, the presence of the emiaer poly siringer
may interfere Mth the formation of the emitter oxide sidewal1 spacer. A short-circuit
between the silicided exnitter and the silicided e x h i c base may fonn at this location,
Since the cross-sectional area of the short is ükely to be very srnail. it may appear in the
base-ernitter diode characteristics as an încrease in leakage current at low bias. It is
possible that the non-ideal current apparent at low V, in Fig.5.4a arises in this way.
The best approach to rernoving the emitîer stringer is to reduce the height of the field
poly, and to slope the edge of the field poly sidewall by using an isotropie etch to define
this feature. In the self-aligned device the field poly need only be thick enough to aliow
for silicidation.
CHAPTER 6
CONCLUSIONS AND RECOMMENDATIONS
6.1 Conclusions
This thesis has described the design, fabrication and electrid characterization of a novel
self-alignecl SiGe aUoy base heterojunction bipolar transistor. The device stnrcture uses
an emitter polysiïicon stripe to define the width of the intrinsic device, provides self-
alignment of the silicided e x h i c base to the emitter, and allows contact to the base to
be made over the field oxide, minirnizing parasitic capacitance. Although self-aligned
single-pclysilicon homojunction BJTs have been reported previously, this is the fmt
demonstration of a comparable HBT. The new structure can be fabricated with a
considerabiy sirnpler proce!ss flow than previously reporteci SiGe base HBTs. A more
conservative non-self alignai structure which simuiaîion predicts should offer somewhat
inferior elecmd performance was also fabricated.
The work is also novel in the extension of SiGe HBT design to far lower cunent densities
and device power dissipation levels than considered in previous work Previous
researchers typicaiiy concentrated on optimizing the speed of the SiGe HBT irrespective
of power dissipation. typically optimizing operation for cumnt densities approaching 106
A/cm2. The present study required optimization of speed for operation at 200 pA
collecter current in a device Mth a 1.5 pm by 3.0 pm inûinsic area. corresponding to a
collecter cunent density of just 4.4 x 1W A/cmL.
The development of the SiGe base HBT described here was a large project involving
contributions from several researchers. The main coritributions made by the author are:
1. Design of a composition and doping profile capable of providing high-speed
performance at low current density. This part of the work was carrieci out using the
BIPOLE3 device simulator.
2. Development of the key process modules quired io hplement the SiGe base HBT by
modiQing an existing homojunction BJT process architecture at Gennum Corporation.
3. Layout of a suite of hîgh-frequency and low-frequency test transistors for use in
process development. AU experimental resuits reported here were obtained from this set
of devices.
4. Analysis of electrical test data on prototype devices provided by Gemm to assess the
success of the profile design, to test the accwacy of the BIPOLE3 simulator in describing
the new SiGe HBT structure, and to rnake recommendations for structural modifications
to improve performance in future process nins.
The most important points emerging from the present investigation can be summarized as
follows:
1. The prelirninary caldations and simulation r d t s identified the dominant
components of the defay times that ùifluenced the performance of the device. These
include, the emitter-base junction charging time t,, basetransit time r, and c o k t o r
space charge layer transit time &.,. Boih one-dimeensional (vertical) and two-dimensional
(lateral) analysis were conducted using the device simulator BIPOLE3 program. The
resuits of the transition frequency obtained from the vertical analysis are 59% higher
than the transition frequency obtained h m the lateral analysis. This would suggest that
the lateral effects, which were ignored in the vertical analysis are not important in the
curent devices.
2. The simplified regional analysis of transit times in SiGe HBTs presented in this thesis
identified the main stnicturai parameters that significantly influence transistor electrical
performance. This approach greatly facilitates the physical interpretation of numerical
simulation on the F, and Fm and provide insight into how F, can be modelied. The andysis
indicated that in order to achieve high performance at low coilector current (&=2OO pA),
the SiGe-base must be Lightly doped, whereas the emitter shouid be heavily dopeci. The
optirnized doping levels in the emiaer. base and coilector are 3 x l ~ / c m 3 . l~lO'~/cm.' and
2.8~10~~/crn~. respectively. It was found that by simulation the above doping levels
combineci with a base-width Wb equal to 450 A give F, z 18.5 GHz. Decreasing Wb below
98
450 A gives unacceptably low bmakdown voltage BV,. hcreasing Wb was found CO
significmly degrade the speed of the devices.
3. The simulation resuits revealed very significant performance advantages can be
obtained by reducing device geometries. For example, at I, =200 pA, FI and Fm for the
device SAO5X (shown in Table B. 1 Part 1 of Appendix B) are 26.2 GHz and 37.2 GHz
respectively. The analysis indicated that the parasitic capacitances CE and C,c and the
total base mistance are rnuch smaller for srnail-geometxy devices than the typical 1X
devices.
4. The simulation results conclusively indicate that the SiGe-base devices have much
better performance than the corresponding Si-base devices. Specificaiiy, at a given
collecter curent, the transition frequency F,, maximum oscillation frequency Fm, m e n t
gain p. Early voltage VA, and the breakdown voltages BV, and BV,, are much higher
for SiGe-base devices than the comsponding Si-base devices. This indicates that SiGe
HBTs c m offer significant performance advantages even for low power operation.
5. Three process modules have been developed and integrated with the G e ~ w n ' s
existing BTT techno10gies to aliow fabrication of the new SiGe base HBT. These modules
include field poly formation, SiGe-base deposition and local interconnect formation.
6. The fmt examples of both the self-aligned and non-self aligned devices have been
successNly fabricated at Gennum Corporation. Elecaical test results for this set of
devices are very encouraging. The self-aligned devices show non-idealities in the
Gumrnei plot at low current density, probably as a result of peripheral leakage resulting
from the emitter poly stringer on the field poly sidewall. DC characteristics for the non-
self aiigned devices were near ideal. At &= 200 @ typical self-aligned devices gave
F,= 12.2 GHz while a non-self aiigned device gave FL=l 3.2 GHz.
7. Difference in performance of simulated and experimental devices are believed to result
from differences in the width of the SiGe-base. The simulation results were baseci on the
base-width equal to 450 A in order to achieve the target specifications. However, in order
to ensure that the present devices should work at this stage of the cwent phase, the base-
width was arbitrarily increased to 700 A. The penalty for this action is that both FL and Fm
of the SA and NSA devices were seriously degraded. The F, for SAlX and NSlX devices
was found to be equal to 12.2 GHz and 13.2 GHz respectively, at &=200 pA. In addition
to the base width Wb, there are several main rasons which lead F, for SAlX to be smailer
than Ft of the NSA device.
6.3 Re~~mtnendations For Future Work
When this work was initiateci. no experimental data was available on boron and
germaniun diffusion in an SiGe HBT structure of the kind considered here. Now that a
fmt set of test devices has been produced, doping profies should be obtained using
100
SIMS and/ or SRP techniques before and after emitter annealing, This would provide
empirical data on the effect of the ernitîer anneal on device structure for use in future
designs. Zn addition, availability of actual doping profiles would permit precise
cornparison of the predictions of the BIPOLE3 sirnulator with the performance of an
experimentai device. This calibration of BIPOLE3 would be very usefid for subsequent
redesign of doping and composition profiles.
The available information on the doping and composition profies actuaily produced in
the f i t set of test devices suggests thor the base width wu closer to 700 A than the
design value of 450 A. An attempt should be made to produce a second set of test devices
with neutral base widîh as close as possible to 450 A.
To make the self-aligned HBT stnicnue manufacturable in an industriai environment, the
issue of polysilicon emitter stringers on the field poly sidewail must be addresseci. This
problern can probably be solved by reducing the field poly height, rounding the shape of
the field poly sidewall, and perhaps modifying the emitter polysilicon plasma etch.
Al. The pn One-Sided Step Jundon
The space charge (depletion) w i d h in the emitter-base X, and the basezoliector &
regions at thennodynamic eqdibrim can approximately be calculated using a depletion
Iayer approximation. Only the final forrndae are given below, and the details are given
elsewhere [16].
where the Na and Nd are ionized acceptor and donor dopant concentrations, respectively;
q is the elecîronic charge; E, (=&,,cl) is the permittivity of silicon; E, and el are the
perrnittivity of the fk space and the relative permittivity of the silicon (4 1.9) [15]
respectively; V,, and V\)K are the built-in-voltage at the emitter-base and base-coiiector
regions respectively, and in general is given by [IS] ,
where k is the Boltzmann's constant and T is the absolute temperature; for kT= 0.0259
eV at 300 KT q (intrinsic d e r concentration) for siiiwn was taken to be equal to
1.6~1 01° /cm3 [15]. As mention4 above eqs. Al. 1 and A1.2 were derived under the
assurnption of themiodynamic equilibrium, so when an extemal bias voltage is applied
across the pn junction. eqs. A l -1 and A l -2 should be modifieci in such away thar this bias
should be subtracted from the built-in voltage V,.
A2 Depletion Layer Capacitance
For a p n junction, the depletion or the space-charge layer capacitances are given by [15],
where Cid and CM are the depletion layer capacitances of the two junctions at zen, bis;
y. and y, are coefficient constants which are îaken to be equal tol/2 and l/3 respectively
[15]. These values based on the assumption that the emitter has a uniform doping profde
whereas the emitter-base jrnction was more closely approximated by a linearly p d e d
junction profile. The present simulation results are in agreement with Roulston r d t s
[15]. The remaining parameters in eqs. A2.1 and A22 have their usuai meaning. The
values of the parameters of the right side of both eqs. A2.1 and A2.2 were obtained h m
the simulation analysis.
APPENDIX B
B. 1 Tables
Table B. 1 Part1 . Heavy emitter doping, various geornetries
r, =zoo pA v, = 1.0 v ED =6.O xlOm cm'3 BD = 1.0 x10 l8 cm" EPI = 2.8 xI0 l6 cm"
F, % Rbcr G H z P Q
372 100 290
23.1 170 250
16.7 180 n o 2&7* 440*
20.6 190 260
14.7 190 760 1 72* 46(P
SA-IX' EPW=15 FPW=3.0 pm
* UnderestSrnates base resistance
+ Si-base doping profiles: ED = 3.0 x10 cm-' BD = 4.0 x10 cm3 EPI = 1.0 x10 l6 cm"
Table B. 1 Part2 Heavy ernitter doping, various geometries
The BVh and the reach through of the foiiowing devices are slightly different h m the devices listed in Table B.l partl, and their magnitudes are given below: SV, = 19.0 V Reach through = 5.17 V
NSAlL5X25 EMW=125 pnY
EMG-1.5 p l FPW =275 pn
Table B.2 Part 1. Light exnitter doping, various geomeaies
XJ, = 0.05 pm SV, = 5.7 V XJ,= 0.1381 pm BV, = 19.0 V Wb=0.045 prn Reach through = 4.79 V
EPI = 2.8 x10 l6 cm'= Ge= 10%
NSA125X EMw=125 pJn FPW =u (un
* Underestimates base resisiance
+ Si-base doping profiles: ED = 3.0 xl0 cm-3 BD = 4.0 xlO l8 cm" EPI = 1 .O x 1 0 l6 cm"
XJ, = 0.05 pm BV, = 9.6 V XJ, = 0.1398 pm BV, = 21.0 V Wb = 0.07 pm Reach through = 4.19 V TEP1 = 0.59 pm
Table B.2 Part2 Light emitter doping, various g-etries
NSAlZXlU
EMG-123 pl FPW =275 p m
SA1 EX25
NSAlsXI5 W = 1 5 pm -- 1.S pm FPW =3.0 pm
SA-1X' EPW=lLi )rm
FPW=3.0 t
Table B.3 Partl. Light emiüer doping, Light EPl doping, various geometries
BD = 1.0 x10 '"cm" EPI = 1.0 x10 I6 cm-3
XJI = 0.05 pm BV,= 7 5 V ]U2=0.1359 p SV, = 19.2 V Wb=0.045 pm Reach through = 1.92 V
- - ~- --
* Underestimates base resistance
+ Si-base doping profiles: ED = 3.0 xlOm cm" BD = 4.0 x10 I8
EPI= 1 . 0 ~ 1 0 ' ~ cm"
XJ, = 0.05 BV, = 9.6 V XJ,=0.1398 ym BVb=21.0V Wb =0.07 prn Reacù through = 4.19 V
TEPI = 0.59 pm
Table 8.3 Part.2. Light emitter doping. light EPI doping, various geometries
I, =200pA v, = 1.0 v ED = 3.0 xlOa cmJ BD = 1.0 x10 l8 cm-3 EPI = 1.0 x10 l6 cm-3
FR GHz
NSAI25Xl25 EMW=125 pm E M S 1 2 5 pl FPW = t 7 5 pm
NSAlSXlS EMW=15 pm EMG- 1 5 pm FPW =3.0 pro
SA- 1 X' EPW=lS pl FPW=3.0 pm
Table B.4 Heavy emitter dopiog, light EPI doping. various geometries
I, =2ooM v, = 1.0 v ED = 6.0 xlOa cm" BD = 1.0 x10 l8 cm-' EPI = 1.0 x10 l6 cmm3
* Underestimaies base resistance
+ Si-base doping profiles: ED = 3.0 x10 XJ1 = 0.05 pn BV, = 9.6 V BD = 4.0 x10 cm'J XJ,=0.1398 p BVcbo=21-0V EPI = 1.0 x1Ol6 cm-' Wb = 0.07 pm Reacb through =4.19 V
TEP1 = 0.59 pm
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