Design of two stage OP AMP
-
Upload
azmathmoosa -
Category
Engineering
-
view
351 -
download
19
description
Transcript of Design of two stage OP AMP
DESIGN OF TWO-STAGEOP AMPS
AZMATH MOOSA
M.TECH 1ST YR
EEC7209 DESIGN OF ANALOG AND MIXED MODE VLSI CIRCUITS
DEPARTMENT OF ELECTRONICS
PONDICHERRY UNIVERSITY
INTRODUCTION
• OP AMP IS A FUNDAMENTAL BUILDING BLOCK IN MIXED MODE DESIGN
• THEY ARE IMPLEMENTED USING MOS TRANSISTORS
• TWO STAGE OP-AMPS ARE A POPULAR TECHNIQUE
THE OP-AMP
• MOSTLY FAMILIAR AS IC 741
• DIFFERENTIAL AMPLIFIER
• IDEAL CHARACTERISTICS
• INFINITE GAIN
• INFINITE BW
• INFINITE INPUT Z
• 0 OUTPUT Z
THE ARCHITECTURE
A1 A2 1
V1
V2 VOUT
Cc
DifferentialInput Stage
Second Gain Stage
OutputBuffer
+
-
DESIGN PARAMETERS
• GAIN
• GAIN BANDWIDTH
A1
+
-
signal signal
DESIGN PARAMETERS
• SETTLING TIME
• SLEW RATE
A1
+
-
Sle
w R
ate
Settling Time
DESIGN PARAMETERS
• OUTPUT VOLTAGE SWING
• OUTPUT RESISTANCE
A1
+
-
Vdrop
Vout
Vdrop
DESIGN PARAMETERS
• OFFSET
• NOISE
A1
+
-
DESIGN PARAMETERS
• COMMON MODE INPUT RANGE (ICMR)
• VICM IS THE AVERAGE OF V1 AND V2 (THE INPUT PINS) THAT THE OP AMP CAN HANDLE
• COMMON MODE REJECTION RATIO (CMRR)
• RATIO OF DIFFERENTIAL MODE GAIN OVER COMMON MODE GAIN
• POWER SUPPLY REJECTION RATIO (PSRR)
• RATIO OF THE CHANGE IN SUPPLY VOLTAGE IN THE OP-AMP TO THE EQUIVALENT (DIFFERENTIAL) OUTPUT VOLTAGE IT PRODUCES
• LAYOUT AREAA1
V1
V2
DESIGN RESULTS
• THE TOPOLOGY
• THE DC CURRENTS
• W/L RATIO
• COMPONENT VALUES
DESIGN PROCEDURE - STEP 1
• PICK A TOPOLOGY
• USUALLY COMES FROM PRACTISE AND EXPERIENCE
DESIGN SPECIFICATIONS
• GAIN AT DC (AV(0))
• GAIN-BANDWIDTH, GB
• PHASE MARGIN (OR SETTLING TIME)
• ICMR
• LOAD CAPACITANCE, CL
• SLEW RATE, SR
• OUTPUT VOLTAGE SWING
• POWER DISSIPATION
DC BALANCE CONDITIONS
• KEEP ALL TRANSISTORS IN SATURATION
• M4 HAS TO BE FORCED INTO SAT
• ASSUME VSG4 = VSG6
• M4’S G&D@SAME POT. => SAT.
𝑆𝑖=𝑊 𝑖𝐿𝑖
𝑓𝑜𝑟 h𝑡 𝑒 h𝑖𝑡 𝑡𝑟𝑎𝑛𝑠𝑖𝑠𝑡𝑜𝑟
STEP 1 - 3
• FROM PHASE MARGIN (SETTLING TIME) CHOOSE CC
• IDEALLY FOR 60 PHASE MARGIN CC > 0.22 X CL
• DETERMINE MINIMUM VALUE FOR TAIL CURRENT
• I5 = SR X CC
• DESIGN FOR S3 FROM THE MAXIMUM INPUT VOLTAGE SPECIFICATION
STEP 4 - 6
• VERIFY THE POLE OF M3 DUE TO CGS3 AND CGS4 WILL NOT BE DOMINANT BY ASSUMING IT TO BE GREATER THAN 10 X GB
• DESIGN FOR S1/S2 FOR DESIRED GB
• DESIGN FOR S5 FROM MIN INPUT VOLTAGE
STEP 7 - 10
• FIND S6 BY LETTING P2 EQUAL TO 2.2 TIMES GB AND ASSUMING VSG4 = VSG6
• CALCULATE I6 AND ADJUST AS NECESSARY (S6 MUST SATISFY VOUT(MAX))
• DESIGN S7 TO ACHIEVE THE DESIRED I5 AND I6 RATIO
• CHECK GAIN AND POWER DISSIPATION
STEP 11 - 12
• IF THE GAIN SPECIFICATION IS NOT MET, THEN THE CURRENTS, I 5 AND I 6 , CAN BE DECREASED OR THE W/L RATIOS OF M2 AND/OR M6 INCREASED.
• THE PREVIOUS CALCULATIONS MUST BE RECHECKED TO INSURE THAT THEY ARE SATISFIED.
• IF THE POWER DISSIPATION IS TOO HIGH, THEN ONE CAN ONLY REDUCE THE CURRENTS I 5 AND I 6 .
• REDUCTION OF CURRENTS WILL PROBABLY NECESSITATE INCREASE OF SOME OF THE W/L RATIOS IN ORDER TO SATISFY INPUT AND OUTPUT SWINGS.
• SIMULATE THE CIRCUIT TO CONFIRM THE DESIGN
EXAMPLE
• PROCESS SPECIFICATION
• DESIGN SPECIFICATION
STEP 1- 3
• CALCULATE MIN VALUE OF CC
• ROUND UP CC AND CALCULATE I5 FROM SR
• CALCULATE S3 USING ICMR
STEP 4 - 5
• CHECK VALUE OF MIRROR POLE P3
• CALCULATE GM1 (GB IN RADIANS)
• CALCULATE S1 AND S2
STEP 6 - 7
• NEXT CALCULATE VDS5
• CALCULATE S5 FROM SAT RELATIONSHIP
• CALCULATE S6
STEP 8 - 9
FINAL DESIGN
SUMMARY OF RELATIONSHIPS
c
sC
I
)(
2
42
1
42
11
s
m
dsds
mv I
g
gg
gA
)( 766
6
76
62
I
g
gg
gA m
dsds
mv
c
m
C
gGB 1
L
m
C
gp 62
c
m
C
gz 61
(min)1(max)033
(max) TTS
DDin VVI
VV )((max)11
(min) satDSTS
SSin VVI
VV
DSSATDS
IV
2)(
THANK YOU