Design of Low-Voltage Analog Ampliﬁers Using Floating-Gate...

UNIVERSITY OF OSLODepartment of Informatics

Design of Low-VoltageAnalog AmplifiersUsing Floating-GateTransistors

Henning Gundersen

Cand Scient Thesis

May 2000

Acknowledgments

This thesis is a part of my work for the Cand� Scient� degree at the Department ofInformatics� University of Oslo�

I want to thank everybody who have helped me� and have believed in me� withoutyou this thesis would never have been a reality�

A very special thanks to my supervisor Yngvar Berg� with his enthusiastic way of guid�ing me in the right direction� In addition invaluable help from Ph�D student Dag T�Wisland who helped me with his knowledge in chip design� for managing the laboratoryequipment� and simulations problems with the Cadence application program� I alsowant to thank M�Sc student �ivind N�ss� he made things much easier since he alreadyhad done all the digging in the dirt ahead of me�

And last but not least� I want to thank all of my friends� without them life outsidethese four walls� would have been dull and boring� and not given me new strength tocarry on�

Department of Informatics� University of Oslo� ��th May ��

Henning Gundersen

I

Contents

� Introduction �� The Floating Gate UV MOS Transistors � � � � � � � � � � � � � � � � � � �� Low�voltagelow�power Ampli�er Design Using

FGUVMOS transistors � � � � � � � � � � � � � � � � � � � � � � � � � � � � �� Presentation of the results � � � � � � � � � � � � � � � � � � � � � � � � � � �� Overview of the Thesis � � � � � � � � � � � � � � � � � � � � � � � � � � � � �

� The Floating�Gate UVMOS Technology �� Introduction � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �� FGUVMOS Transistor Model � � � � � � � � � � � � � � � � � � � � � � � � �� Tuning of The FGUVMOS Transistor � � � � � � � � � � � � � � � � � � � �� Programming of the FGUVMOS Circuits � � � � � � � � � � � � � � � � � �

�� Inverter � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �� Analog Inverters � � � � � � � � � � � � � � � � � � � � � � � � � � � �� Analog inverter with bias control � � � � � � � � � � � � � � � � � � ��

�� Di�erence in Programming of the Circuits � � � � � � � � � � � � � � � � � ��

� Analog and Digital Floating�Gate Circuits �� Introduction � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �� Building Blocks in the FGUVMOS Ampli�er Design � � � � � � � � � � � �

�� Inverters � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �� Analog Inverters � � � � � � � � � � � � � � � � � � � � � � � � � � � �� The Floating�Gate Analog Inverter �� The Floating�Gate Additive Analog Inverter with Tunable Gain � �� Floating Gate Current Sum Circuit � � � � � � � � � � � � � � � � � ��

� The Ultra Low Voltage FGUVMOS Ampli�er �� Introduction � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ��

�� DC � Characteristics � � � � � � � � � � � � � � � � � � � � � � � � � �� AC � Characteristics � � � � � � � � � � � � � � � � � � � � � � � � � ��

�� OTA with Floating�Gate Circuits � � � � � � � � � � � � � � � � � � � � � � � �� The Simple Di�erential Ampli�er � � � � � � � � � � � � � � � � � � �

III

IV CONTENTS

�� The Sinh Ampli�er di�erential in and outputs � � � � � � � � � � � �� Transconductance ampli�er with dynamic load � � � � � � � � � � �� Transconductance ampli�er Vdd = 0.8V � � � � � � � � � � � � � � �� Transconductance ampli�er Vdd = 0.5V � � � � � � � � � � � � � � �� Transconductance ampli�er Vdd = 0.3V � � � � � � � � � � � � � � ��

�� Tanh Ampli�ers � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ��

� Conclusion and Further Improvements �� Summary � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ��

�� FGUVMOS Design � � � � � � � � � � � � � � � � � � � � � � � � � � �� Further Improvements � � � � � � � � � � � � � � � � � � � � � � � � � � � � �

Chapter �

Introduction

The main subject of this thesis� is characterization of low�voltagelow�power ampli�erdesign using Floating�Gate UV MOS Transistors �FGUVMOS�� The objective of low�voltagelow�power electronic research� is to develop methods and circuits for systemsoperating at low�voltage power�supply ��

Why do we need low�voltage Ampli�ers� One reason is because of the continuingdown�scaling of processes� the channel length is scaled down to sub�microns� and thethickness of the gate oxide is just nanometers� Then we need to reduce the powersupply to ensure device reability� Another reason is the use of portable equipment�sensors and portable medical monitoring instruments� in order to have an acceptableoperating time from the batteries� and we have to lower the supply voltage� to reducethe power consumption�

Reducing the Supply Voltage

The minimum supply voltage in traditional low�voltage circuits may be de�ned as�

Vsup,min = 2(Vgs + Vsat)

The low�voltage circuits are able to operate on a supply voltage� Vdd of two stackedgate�source voltages and two saturation voltages �� Low�voltage circuit are circuitswhich operate with power supply Vdd less than 3V � There are ampli�ers available today�using � Volt single supply voltage �� If we look at the power consumption in a digitalCMOS circuit� the good news is that it follows a square law� hence great power savingsare realized just for a small reduction in the power supply� However� when looking at adigital design with a power supply of 3.0V � and then reduce the supply voltage to 1.0V �the reduction in the dynamic power consumption P1P2 =

12

32= 11% of the original� which

is a power saving of �� And then when reducing the power supply from 3.0V to0.5V the reduction is ��

The demand for low�voltage low�power will reduce the dynamic range of an ampli�er�in order to maximize the dynamic range� A low�voltage ampli�er have to deal with a

�

� CHAPTER �� INTRODUCTION

voltage swing that extend from rail�to�rail � both on the output and the input stage�When going down with the supply voltage to less than 0.5V � it is important that theoutput signal has an amplitude swing close to Vdd� This means that we are getting aproper dynamic range� and a satisfying Noise Margin� Other factors which are appearingwhen we do reduce the power supply� is decreased signal�to�noise ratio �SN�� andreduced bandwidth�

�� The Floating Gate UV MOS Transistors

This thesis will deal with the design of ampli�ers which uses Floating�Gate UV MOSTransistors �FGUVMOS�� Floating�Gate MOS transistors have been used for severalyears as long term non�volatile memories �� By using FGUVMOS transistors thee�ective threshold voltage of the transistors may be tuned with UV�light �� which is described in section �� The Floating�Gate transistor may be used todesign both analog and digital low�voltagelow�power circuits �Vdd < 1V )� ��

The idea of using a Floating�Gate MOS transistor is to separate the gate of atransistor from the rest of the circuit� and then inject charge on the �oating gate node�In order to separate the node or the �oating gate from the input� we have to usea coupling capacitor� There may be multiple inputs to each device� with a separatecoupling capacitor� since the input signal is not directly coupled to the gate of thetransistor�

�� Low�voltage�low�power Ampli�er Design UsingFGUVMOS transistors

The main objective of this thesis is to characterize the Floating�Gate UVMOS OTA�

circuits� A short description of the di�erent building blocks which are used in theampli�er circuits� will be analyzed with measured and simulated results� The mainfocus will be DC�characteristics of the di�erent circuits�

Floating Gate UV�MOS �FGUVMOS� transistor design� uses supply voltages lessthan � V� This is why we call them ultra low�voltage circuits� The FGUVMOS�ampli�eris a rail�to�rail ampli�er� the response of the FGUVMOS circuit has a signal amplitudeclose to Vdd both on the output� and on the input stage�

�� Presentation of the results

The measured results of the circuits will be presented� but due to limited time� notall of the circuits which are implemented have the measured results available� In that

�Ampli�ers capable of reaching both supply �rails� are called rail�to�rail ampli�ers�Operational Transconductance Ampli�er

�� OVERVIEW OF THE THESIS �

case the simulated results will be presented� The layout of the fabricated chip andthe simulation are done with the application program Cadence ver� � �� which usesSpectreS as a simulation tool� The measurement equipments and methods used� isexplained i appendix �

�� Overview of the Thesis

Chapter � gives a short introduction to the thesis� and background information�

In Chapter � we present the fundamental theory in the FGUVMOS transistor tech�nology� and problems according to the UV programming process�

In Chapter � the common building blocks used in OTA design using FGUVMOStransistors are presented�

In Chapter � we do present some simple OTA�s� and analyses and characterize theresults of the di�erent ampli�er circuits�

In Chapter � a summary and the conclusion of the thesis is provided�

CHAPTER �� INTRODUCTION

Chapter �

The Floating�Gate UVMOS

Technology

�� Introduction

Floating�Gate MOS transistors have been used for several years to store digital informa�tion in EPROMS� EEPROMS and �ash memories �� However� in �� a method forusung multiple inputs to a �oating gate �� was discovered� The �oating gate voltagewas established as a weighted capacitive voltage summation� This new way of usingthe �oating gate introduced some interesting analog and digital information�processingcircuits� such as DA converters �� and multiple�input �oating gate ampli�ers ��Shibata and Ohmi named these devices neuMOS transistors� Yang� Andreou andBoahen named it Multiple�Input Floating�Gate Transistors �FGMOS �� Theabove mentioned methods have used Fowler�Nordheim tunneling to inject charge on the�oating gate �� We are using UV�light to get the same result� We named our devicesFloating�Gate UV MOS Transistors� FGUVMOS �� These transistors canbe implemented in any commercial double�poly CMOS process�

The circuits presented in this thesis have been made by using the �� μm CMOSprocess from AMS �� In such a process we let the gate �poly�� be a �oating node�and we use poly� to make the capacitor�CPOLY�� When using the AMS��μm process�poly� have to be larger than poly�� and by changing the area of overlap between poly�and poly�� we are able to make several di�erent capacitors� An example of a Cpolycapacitor is shown in �gure �� b�� The UV�window is made in the junction betweengate and source� To make the UV�hole� we are using metall � and metall �� and to makesure there is a hole in the paci�cation layer� we need a PAD opening over the transisor�The UV�window is seen as a box and as a circle in the source end of the transistor in�gure ��

�

� CHAPTER �� THE FLOATING�GATE UVMOS TECHNOLOGY

�� FGUVMOS Transistor Model

CmVm

C1

NVfgn

Id

C2V2

V1

�a� A multi input N�transistor

Diffusion

V1 Drain

Source

V2

Poly2Poly2

Poly1

Cpoly2UV-Window

Cpoly1

�b� Layout of a � input N�transistor

Figure �� Floating Gate UVMOS Transistors

To understand the operation of the FGUVMOS transistor� we have to discuss thecapacitive division with the �oating gate as the dividing node�

Capacitive voltage divider

When looking at �gure �� we can see a simple capacitive voltage division� If we aregoing to solve the capacitor network� we have to de�ne Q = CV � Assuming there is nocharge on the middle node V � we get�

−Q1 −Q2 = −C1(V1 − V )− C2(V2 − V ) = 0 ��

This gives us�

V =C1

C1 − C2V1 +

C2C1 + C2

V2 ��

FGUVMOS Transistor Model in Weak Inversion

When focusing at the multiple input n�channel FGUVMOS transistor in �gure ��each input has an e�ective coupling capacitance Ci� to the �oating gate �� The input

�� FGUVMOS TRANSISTOR MODEL �

Q1+

Q2

V2

+

VC2

C1

V1

Figure �� Capacitive Voltage Divider

signal is attenuated with a factor Ki =CiCT

� where CT is the total load capacitance seenfrom the gate� Ki is called the capacitive division factor for input i�

We will express the behavior of a FGUVMOS circuit in equilibrium condition� Thismeans that we are in the equilibrium point� and all control inputs are equal to Vdd/2 andthe transistor current is equal to Ibec� Assuming we are using the transistors in weakinversion�� the accumulated drain current modulation of m�inputs is expressed as theproduct

∏mi=1 exp{

1nUt(Vi − Vdd/2)ki}� The e�ective drain current of a n�FGUVMOS

transistor is then given by ��

Ids,n−MOS = Ibec

m∏

i=1

exp{1

nUt(Vi − Vdd/2)ki} ��

Similar� we get the drain current of a p�FGUVMOS transistor�

Ids,p−MOS = Ibec

m∏

i=1

exp{1

nUt(Vdd/2− Vi)ki} ��

We express the min and max currents in terms of the balanced equilibrium current�

Imaxds = Ibecexp{1

2nUTVddki} = Ibec�Σ

mi=1ki ��

Iminds = Ibec�Σmi=1(−ki) =

(Ibec)2

Imaxds

≡ (Imaxds )∗ ��

Where � = exp{ 12nUT

Vdd}�

The Dynamic Range �DR� is expressed by�

DR =Imaxds

Iminds��

Assuming Σmi=1ki = 1� it will then give us the the Dynamic Range equal to �2 ��Similar analyses may be done for strong inversion as well


FGUVMOS Design

In a FGUVMOS design there is always one p�MOS stacked on top of one n�MOS tran�sistor� The height is always two� but it is possible to connect transistors in parallel�and each �oating gate may have several inputs connected through �oating capacitorsshown in �gure �� a�� In this way we are able to compensate for the limited stacking�Even when having these limitations� it is possible to design several di�erent FGUVMOScircuits� as showed later in the thesis�

�� Tuning of The FGUVMOS Transistor

In order to use the circuits in low voltage operation� we have to inject charge to the�oating gate� hence we are changing the e�ective threshold voltage �Vth� of the transistorseen from an input� The traditional way to access or charge the �oating gate is byusing electron tunneling� also called FowlerNordheim tunneling or electron injectionalternatively known as avalanche injection ��

In order to initiate the FGUVMOS circuits� we need to access the �oating gatethrough a resistive coupling �� In our case we have used UV�light �250nm� in or�der to charge the �oating gate� When exposing the gatesource region� to UV�light aUV�activated conductance is temporarily connecting the sourcedrain to the �oatinggate� The entire chip is exposed to UV�light� and the UV�activated conductance willdisappear once the UV�light is removed� The FGUVMOS programming technique isdescribed in a number of steps�

��Decide the operative supply voltage Vdd �normal biasing �The ideal supply voltage may be di�erent for di�erent applications�

�� Apply Vdd2 to all external inputs�

When the programming is �nished� all internal nodes and the output are set to Vdd2

��Apply the programming voltages at the supply rails V− at Vdd� and V+at Vss�The supply rails are used to provide the programming voltages� The e�ective thresholdvoltage seen from the control gate� is determined by the programming voltages�

� Terminate the programming by turning the UV�light source o� whenthe output converges to Vdd2

�� Set the biasing voltages to normal values�Use the transistor in operative mode�

�The source and drain are switched during programming of the chip

�� TUNING OF THE FGUVMOS TRANSISTOR �

Vfgp

Vfgn

Cn

Cp

Vin Vout

��

�a� Operative mode �normalbiasing

C l

Vfgp

Vfgn

Vwell

Gnf

Cn

Cp Gpgs

Gpf

GngsGngb

Gpgb

Gpgd

Gngd

Vpsub

Vout

V-

V+

Vdd/2

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

�b� Programming mode �reversed biasing�

Figure �� Single input FGUVMOS circuit

When we are using the transistor in operative mode there is no resistive connectionsto the �oating gate� �gure �� a�� In the programming mode� the desired UV�activatedconductance Gngd and Gpgd appear� �gure �� b�� The parasitic UV�activated conduc�tances Gngs� Gnf �Gngb� Gpgs� Gpf and Gpgb� are determined by the layout and have tobe considered when designing the circuit �� When using traditional transistors as seenin �gure �� the programming conductance compared to the parasitic conductanceis approximately �� The parasitic can be reduced by narrowing the UV�window orusing U�shaped transistors or ring transistors as shown in �gure ��

Charge Loss

Storing charge on a �oating gate have been utilized for several years in digital design� but�nding a way to control this stored charge with su�cient precision is what happens whenusing UV�light to program the circuit� And recently this kind of device has attracted aconsiderable interest as a non�volatile analog storage device and as a precision analogtrimming element �� Experiential results show that voltage on the �oating gate canbe adjusted in increments of sub millivolts� and the charge loss over a period of � yearsis approximately � � at room temperature� ��

We have done some measurements over several months in AMS 0.8μ process� without


Drain

Source

UV-Window

Gate

Poly1

Diffusion

�a� U shaped transistor

Source

UV-Window

Drain

Gate

Poly1

Diffusion

�b� Ring transistor

Figure �� Layout of transistors

any noticeable problems with charge loss� We have not done any of these tests in theAMS 0.6μ process� However� during the test period over three months there have notbeen any signs of charge loss on the �oating gates�

�� Programming of the FGUVMOS Circuits

In order to use a circuit with a power supply less than � Volt� we have to program the ef�fective threshold voltage Vth� and to decide the current levels also called the equilibriumcurrent of the circuits� This section will cover some simple structures like inverters andanalog inverters� and characterization of di�erence in programming voltages and equi�librium currents� The functionality of these circuits will be explained later in chapter ��

�� Inverter

One of the most common building block in FGUVMOS circuits is the digital inverter�seen in �gure �� This section will mainly focus on the programming of the circuit�As seeing in �gure �� this is a symmetrical design� hence it is the same amount ofn�MOS and p�MOS transistors� and the same load on the �oating gate on the n�MOS

�� PROGRAMMING OF THE FGUVMOS CIRCUITS ��

C i

In

C i

Ip

VoutVin

��

��

Figure �� Inverter

and p�MOS transistor CiN = CiP = Ci� The inverter is implemented with Ci = 18.4fF �and with U�shaped transistors l = 0.6μ,w = 10μ� The measured n�MOS currents Inof an inverter with Vdd = 0.5V are shown if �gure �� Typical reprogramming�time ofthis kind of circuit� that is the time required to change the equilibrium currents� is lessthan � minutes�

A useful operation mode is to use the circuit in weak through moderate inversion�which means we can use the circuit with an equilibrium current Ibec ranging from 1nA to1μA�� This shows that the drain current Ids is exponential� as explained in the previoussection� If we use a supply voltage of �� V� we have to set the programming voltageV+ in a range from ��V to ��V� and the corresponding programming voltage appliedat Vdd are shown in �gure �� The same current level with supply voltage equal to ��V� is achieved using programming voltages V+ ranging from �� to �� V� Finally if weare using a power supply with of �� V� the programming voltage V+ is �� to �� V�

An example� assuming we want Ibec = 10nA and we want to use a supply voltage ofVdd = 0.5V � If looking at �gure �� and �� this gives us V+ = 2.1V and V− = −0.2V �By using these �gures it is easy to �nd the corresponding programming voltage for thedi�erent equilibrium currents Ibec�

�These circuits can also be used with a larger equilibrium currents but this is just an example toillustrate the di�erent in the programming of the circuit

�� CHAPTER �� THE FLOATING�GATE UVMOS TECHNOLOGY

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.510

−10

10−9

10−8

10−7

10−6

10−5

10−4

Measured N−Fet currents of a inverter

Vin [V]

Vou

t [V

]

Figure �� Measured n�MOS current In of an inverter with Vdd = 0.5V

1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.510

−10

10−9

10−8

10−7

10−6

10−5

Programming voltage V+

[ V ]

Equ

ilibr

ium

cur

rent

I bec [A

]

Measured equilibrium current (Ibec

) of the inverter

Vdd=0.5 VVdd=0.8 VVdd=0.3 V

Figure �� Measured equilibrium current of the inverter


1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5−1.2

−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4Measured programming voltage of the inverter

Programming voltage V+

[ V ]

Pro

gram

min

g vo

ltage

V−

[V]

Vdd=0.3 VVdd=0.5 VVdd=0.8 V

Figure �� Measured programming voltage of the inverter

A twelve row inverter structure is implemented with the same transistors and thesame input capacitors Ci� As we can see from the measured result from inverter �� in �gure �� there is no problem to program the chip� Inverter �� is used as areference programming point� If focusing at �gure �� the switching point is exposedmore detailed� The o�set between inverter � � and inverter �� is approximately ��mV� and between the switching point of �� and �� is less than 10mV �This is better than a standard inverter chain in an ordinary CMOS process�

Figure �� expresses the operation range of an inverter� as we do see� if the equilib�rium current Ibec is more than 70μA� the gain is less than �� and this is not useful to usein a chain of inverters� This is due to the transistors operating in strong inversion� hencethe drain current Ids is linear� An inverter structure will function in strong inversion�as long as the gain is more than �� If not� there will not be any ampli�cation�


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Measured output from 12 row inverter structure

V in

V o

ut

Inverter # 3 Inverter # 12Inverter # 9

Figure �� Measured output from the inverter structure

0.3855 0.386 0.3865 0.387 0.3875 0.388 0.3885 0.389 0.3895

0.394

0.396

0.398

0.4

0.402

0.404

0.406

0.408

0.41

0.412

0.414

Measured output from 12 row inverter structure

V in [V]

V o

ut [V

]

Inverter # 3 Inverter # 12Inverter # 9

Figure �� Measured output from the inverter structure in detail


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Measured output of the inverter with increasing equilibrium current (Ibec

)

Vin [V]

Vou

t [V

]

Ibec

=70uA

Ibec

=3nA

Figure �� Measured output from the inverter with increasing Ibec

�� Analog Inverters

In �gure �� an analog inverter is shown� An analog inverter �� is a circuit which dohave the following characteristics Vout = Vdd − Vin ≡ V

∗in� hence the output voltage is

analog! inverted � of the input signal� The measured output voltage Vout is shown in�gure ��

The analog inverter is almost similar to the digital inverter� but it has a diodecoupled output stage� The functionality of this circuit is explained in chapter ��The analog inverter is also a symmetrical circuit� but it has more load on the input�and a feedback from the output to the input� The circuit is implemented with inputcapacitor Ci = 18.4fF and feedback capacitor Cr = 14.2fF � The transistors are U�shaped with l = 0.6μm and w = 10μm� The measured n�MOS currents �In� are shownin �gure �� and typical programming time of this circuit is also approximately �minutes�

An acceptable operation mode is an equilibrium current Ibec from 1nA to 1μA� henceweak to moderate inversion� When the supply voltage is ��V� a programming voltageV+ from ��V to ��V is used� The respectively programming voltage of the supply railV− is shown in �gure ��

When using Vdd = 0.5V the programming voltage of V+ is between ��V and �� V�and with supply of �� V� the supply rail V+ is in the range of ��V to �� V�

�In other words the gain of the circuit is ��


Cr

Cr

Ci

In

Ip

Vin Vout

Ci

��

��

��

Figure �� The analog inverter

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

V in (V)

V o

ut (

V)

The Output voltage of the analog inverter #1

Vdd = 0.3 VVdd = 0.5 VVdd = 0.8 V

Figure �� Measured output voltage of the analog inverter


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.510

−10

10−9

10−8

10−7

10−6

Measured nFET transistor current of the analog inverter

Vin (V)

I nF

ET

(A

)

Figure �� Measured n�MOS current In of the analog inverter

As the �gures shows� we can use the same programming voltage V+� when using thecircuit with supply voltage either ��V or ��V� however� there is not any signi�cant dif�ference of Vdd = 0.8V � This means� if the circuit is programmed for a supply voltage of"�� V� we do not need to reprogramme if we switch the supply voltages to Vdd = 0.8V �The corresponding programming voltage of rail V− is shown in �gure ��

If we look more closely at �gure �� we notice the breakpoint of the curves� this iswhen the output of the circuits converges to Vdd/2 during UV�programming� At thispoint the n�MOS is stronger than the p�MOS and to compensate we do have to makethe p�MOS stronger� Figure �� shows that the programming of the circuit is linear�

The di�erence in the characteristic between supply voltage Vdd = 0.8V � Vdd = 0.5Vand Vdd = 0.3V in �gure �� is expected� because the �oating�gate on the p�MOSis relative to Vdd not to Vss� The di�erence between Vdd = 0.3V and Vdd = 0.5V isapproximately �� V� and between Vdd = 0.5V and Vdd = 0.8V it is � V�


2 2.2 2.4 2.6 2.8 3 3.2 3.410

−10

10−9

10−8

10−7

10−6

10−5

Programming voltage V+ [ V ]

Equ

ilibr

ium

cur

rent

Ibec

[A]

Measured equilibrium current (Ibec) of the analog inverter

Vdd = 0.8 VVdd = 0.5 VVdd = 0.3 V

Figure �� Measured equilibrium current of the analog inverter

2 2.2 2.4 2.6 2.8 3 3.2 3.4−1.6

−1.4

−1.2

−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4


Pro

gram

min

g vo

ltage

Vdd

[V]

Programming voltage of the analog inverter

Vdd = 0.3 VVdd = 0.5 VVdd = 0.8 V

Figure �� Measured programming voltage of the analog inverter


�� Analog inverter with bias control

Let us then focus at another circuit� the analog inverter with bias control� which isexplained in chapter �� The n�MOS current Ini and Inr� with increasing programmingvoltage Vss� are shown in �gure �� As the �gure �� shows� this is also a symmetricalcircuit� with input capacitors Cpi� and Cni� and feedback capacitors Cpr� and Cnr� Thecircuit is implemented with the same U�shaped transistors that has been used in thedigital inverter and the analog inverter� l = 0.6μm and w = 10μm� but with the inputcapacitors Cpi = Cni = 18.4fF � and feedback capacitors Cpr = Cnr = 6fF and thebias capacitors Cb = 14.2fF �

VbVb

Vb*Vb*

Cb

Cb Cb

Cb

Inr

Ipr

Ini

Ipi

Vin

Cpi

Cni Cnr

Cpr

Vout

��

��

��

��

��

��

Figure �� The analog inverter ��

When looking at �gure �� with a supply voltage of ��V� the equilibrium currenton the input stage Ini is equal to equilibrium current Inr� when the programmed supplyrail V+ " �� V� This gives us a equilibrium current of approximately 0.5nA� The inputstage is similar to a digital inverter and the output stage is an analog diode coupled stagesimilar to the analog inverter� From the measurement on the equilibrium current in thedigital inverter versus the analog inverter� we have seen that the digital inverter willhave a higher equilibrium current� however� the di�erence between equilibrium currenton the input and output stage is not as signi�cant� as we should suppose� This is whatwe have experienced with the measurement on the fabricated chip� and what we haveto look more closely to� in a further investigation of this UV�programming process�

If we are looking at the characteristics for Vdd = 0.5V � we do notice that Ini isequal to Inr when V+ = 2.5V � This gives a equilibrium current Ibec = 0.05nA� As weshould expect the current Ini is larger than Inr� and the same is the case with a supplyvoltage of ��V� The respective programming voltage of the supply rail V− is shown in�gure ��

If we focus at the di�erence of the two n�MOS currents Ini and Inr� there is no


2.5 3 3.5 410

−11

10−10

10−9

10−8

10−7

10−6


Equ

ilibr

ium

cur

rent

Ibec

[A]

Measured eqilibrium current (Ibec) of the analog inverter #2

Vdd = 0.3 V − IniVdd = 0.3 V − InrVdd = 0.5 V − InrVdd = 0.5 V − IniVdd = 0.8 V − IniVdd = 0.8 V − Inr

Figure �� Measured equilibrium current of the analog inverter ��

signi�cant di�erence� this means that this circuit is easy to control in respect of theequilibrium current�

The relationship between the equilibrium current Ibec and the programming voltageVss is linear� If we wanted an equilibrium current Ibec at approximately 1μA� thecorresponding programming voltage V− would be approximately �V�

�� DIFFERENCE IN PROGRAMMING OF THE CIRCUITS ��

2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4−2.5

−2.3

−2.1

−1.9

−1.7

−1.5

−1.3

−1.1

−0.9

−0.7

−0.5

−0.3

−0.1

0.1

0.3

0.5Programming voltage of the analog inverter #2


Pro

gram

min

g vo

ltage

V−

[ V

]

Vdd = 0.8 VVdd = 0.5 VVdd = 0.3 V

Figure �� Measured programming voltage of the analog inverter ��

�� Dierence in Programming of the Circuits

A circuit in FGUVMOS design will consist of di�erent building blocks� and as we haveseen from the measured result on the analog and the digital inverter� they need di�erentprogramming voltage� �gure �� We have to focus this problem more closely� Perhapswe should make transistors with a di�erent geometry in the di�erent blocks� or we couldmake the UV�hole di�erently in an analog and a digital inverter� The UV�programmingtime is approximately the same in the building blocks�


1.5 2 2.5 3 3.5 410

−11

10−10

10−9

10−8

10−7

10−6

10−5

10−4

Programming voltage Vss [V]

Equ

ilibr

ium

cur

rent

Ibec

[A]

Measured eqilibrium current Ibec

, Vdd

= 0.5 V

Digital Inverter

Analog inverter #1

Analog inverter #2

Figure �� Measured equilibrium current Ibec

Figure �� shows the di�erent equilibrium current Ibec� with a supply voltage of��V� Assuming we are using this circuit in weak to moderate inversion� hence equilib�rium current is 1nA to 1μA� This gives the digital inverter a programming voltage V+�� to �� V� and of the analog inverter gives V+ between �� to �� V� and with theanalog inverter �� the programming voltage V+ is �� to �� V� This means� if we arebuilding an ampli�er with a digital inverter and a analog inverter� we are able to use aprogramming voltage V+ from �� V to �� V�

Between a digital inverter and an analog inverter �� there is no intersection� thebest solution is separate supply� And �nally between an analog inverter and the analoginverter �� the programming voltage V+ should be �� V to �� V�

Chapter �

Analog and Digital Floating�Gate

Circuits

�� Introduction

This chapter will cover the di�erent circuits used in the FGUVMOS ampli�er design �Other fundamental circuits used in a FGUVMOS design� is not covered in this thesis�� In order to make it easier to understand� there will be used some symbols�The symbols are shown in �gure ��

n~

p~In

Out Out

OutOut

(a) Inverter

In1 In1

In2 In2

In

In1

In2

Vb*Vb

(b) Analog inverter

In1

In2

Out

Out

(c) Current sum, P-type

(f) Current sum, N-type(d) 2 input inverter (e) Analog addaptive inverter

Figure �� Symbols used in FGUVMOS design

��

� CHAPTER �� ANALOG AND DIGITAL FLOATING�GATE CIRCUITS

�� Building Blocks in the FGUVMOS Ampli�er Design

�� Inverters

C i

In

C i

Ip

VoutVin

��

�a� One input

C i

C i

C i

C i

Ipa

VoutVin2

Ina

Vin1

��

��

��

��

��

�b� Two input

In1

In2

In

Out

Out

�c� Symbols

Figure �� Inverters

The inverter is a digital circuit and one of the most fundamental blocks in theFGUVMOS design� This is a useful building block� both in the analog and in thedigital circuit� Figure �� shows two kinds of inverters� an one input �a�� and a doubleinput inverter �b�� The symbols which will be used later in the thesis are shown in�gure �� c��

Inverter � Voltage Characteristics

Figure �� shows the output voltage of the inverter with Vdd " �� V� �� V� and ��V� This is a rail�to�rail signal even with a supply voltage of �� V� We also notice areduced gain with Vdd " �� V� and when the transistors are in strong inversion� henceequilibrium current more than 1μA�

Figure �� shows the output voltage of a tree row digital inverter structure� withsupply voltage �� V� All digital inverters are implemented with capacitors Ci = 18.4fF �and U�shaped transistors with l = 0.6μm and w = 10μm� The measured results in�gure �� shows a rail�to�rail output swing for each of the three outputs� The o�setbetween the outputs� is due to mismatch� The UV�programming balance is done on the�rst inverter in this chain�

The gain of the di�erent nodes is shown in �gure �� As we can see� the gain atnode �� is approximately �� in node �� it is approximately �� and on the output itis approximately �� The gain increases approximately with a factor � through eachinverter� however this is not an accurate measurement due to the limited resolution�

�� BUILDING BLOCKS IN THE FGUVMOS AMPLIFIER DESIGN ��

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.80

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8Measured output voltage of the inverter

Vin

Vou

t

Ibec

= 90 nA

Ibec

= 1.7 uA

Ibec

= 1.6 uA

Ibec

= 1.6 uA

Ibec

= 45 nA

Ibec

= 37 nA

Figure �� Measured output voltage of the inverter

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5Measured output of a 3 row inverter

V in (V)

V o

ut (

V)

Inverter # 2Inverter # 3Inverter # 1

Figure �� Measured output from a row of � inverters

�� CHAPTER �� ANALOG AND DIGITAL FLOATING�GATE CIRCUITS

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−10−9.5

−9−8.5

−8−7.5

−7−6.5

−6−5.5

−5−4.5

−4−3.5

−3−2.5

−2−1.5

−1−0.5

00.5

11.5

22.5

33.5

44.5

5

Vin [V]

Gai

n

Measured gain of the 3 row inverter

Inverter # 2Inverter # 1Inverter # 3

Figure �� Measured gain of the � rows inverters

Figure �� shows the gain of the �� row inverter chain� with the same transistorused in the three row structure� and with supply voltage �� V� The output voltagecharacteristics are shown in �gure �� and �� The inverter has a large gain� and itis useful as an output stage in an analog ampli�er design�

Inverter � Current Characteristics

The current in the p�MOS transistors of the inverter in �gure �� a� is given by�

Ip = Ibecexp{kinUT(Vdd/2− Vin)} ��

and similar the current in the n�MOS transistor is�

In = Ibecexp{kinUT(Vin − V dd/2)} ��

If looking at the � input inverter in �gure �� b�� we can express the p�MOS currentby�

Ipa = Ibecexp{kinUT(Vdd − Vin1 − Vin2)} ��

And the n�MOS current is given by�

Ina = Ibecexp{kinUT(Vin1 + Vin2 − Vdd)} ��


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

−20

−15

−10

−5

0

5

10

15

20

Vin [V]

Gai

n

Measured gain of the 12 row inverter structure

Inverter # 3 Inverter # 9 Inverter # 12

Figure �� Measured gain of the �� rows inverters

We name the duoble input inverter� an additive inverter ��

The output current of an inverter is sinh shaped as focused in �gure �� and theoutput current is given by�

Iout = In − Ip = 2Ibecsinh{ki

nUT(Vin −

Vdd2} ��

And similar we will get the output current of the double input inverter�

Iout = Ina − Ipa = 2Ibecsinh{ki

nUT(Vin1 + Vin2 − Vdd} ��

To use an inverter�chain to increase the gain on the output� is not very useful� Wecould have used larger input capacitors and longer transistors� or we could use a biascontrol� on the output stage� as shown in �gure ��

The output current on the inverter with bias control is given by�

Iout = Ina − Ipa = 2Ibsinh{(Vin1 + Vin2 − Vdd)K} ��

where Ib = Ibecexp(Kb(VbVdd2 ))� Kb =

kbnUT

and K = kinUT


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−6

−4

−2

0

2

4

6x 10

−6 Measured output current Iout

of a inverter with Ibec

=300nA

Vin

[V]

Vou

t [V]

Figure �� Measured output current of an inverter with Vdd = 0.8V

Iout

Cb

Vb*

Vb

CbC i

C i

C i

Ina

Ipa

VoutVin2Vin1

C i

��

��

��

��

��

��

Figure �� Output stage with bias


�� Analog Inverters

Two di�erent types of analog inverters �� are shown in �gure �� The analoginverter in �b� is a four transistor symmetric circuit� as we do see the input stage issimilar to an inverter� and the output stage is a diode coupled stage� Figure �a� showsa more compact design with only two transistors� The output gain of the circuit in�gure �a�� is controlled by the capacitive division factor ki and kr� and if we make kra little smaller than ki� we are able to compensate for the early e�ect� The outputcharacteristics� both simulated� and measured� is shown in �gure �� With kr smallerthan ki� the gain of the circuit is ��

Cr

Cr

Ci

In

Ip

Vin Vout

Ci

��

��

��

��

��

�a� Ver �

VbVb

Vb*Vb*

Cb

Cb Cb

Cb

Inr

Ipr

Ini

Ipi

Vin

Cpi

Cni Cnr

Cpr

Vout

��

��

��

��

��

��

�b� Ver �

Out

Vb*Vb

In Out

In

�c� symbols

Figure �� Analog Inverters

If looking at the analog inverter in �gure �� a� the current In is given by�

In = Ibecexp{1

nUT(Vin − Vdd/2)ki} × exp{

1

nUT(Vout − Vdd/2)kr} ��

Similar we get the current Ip�

Ip = Ibecexp{1

nUT(Vdd/2− Vin)ki} × exp{

1

nUT(Vdd/2− Vout)kr} ��

We let In = Ip and assuming that ki = kr = k this gives�

exp{ knUT (Vin − Vdd/2) +knUT(Vout − Vdd/2)} = exp{

knUT(Vdd/2− Vin) +

knUT(Vdd/2− Vout)}

exp{ knUT (Vin + Vout − Vdd)} = exp{knUT(Vdd − Vin − Vout)}

If we solving this for Vout it gives� Vout = Vdd − Vin ≡ V∗in� which is an analog inverted

input signal� with gain ��Simulation is done with SpectreS which is included in the Cadence applications program


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Vin

[ V ]

Vou

t [ V

]

Simulated and measured output voltage of a anlog inverter

SimulatedMeasured

Figure �� Simulated and measured data of the analog inverter

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Vin [V]

Vou

t [V

]

Measured analog inverter characteristics

Increasing Ibec

Ibec 0.1nA − 0.4nA

Ibec 0.14nA − Ibec 300nA

Ibec 0.44nA − Ibec 2uA

Figure �� Measured output voltage of the analog inverter ��


The analog inverter �� is implemented in the AMS ��μ process �� using transistorswith w = 10μ� l = 0.6μ and Ci = 18.4fF � Cr = 14.2fF � The analog inverter may beprogrammed to di�erent supply voltages� Vdd� The measured results of supply voltagesVdd = 0.3V � Vdd = 0.5V � and Vdd = 0.8V is shown in �gure �� The linear rangeof operation� for extreme low supply voltages is limited by the linear region of thetransistor� approximately 4UT in weak inversion�

Analog Inverter � Output Characteristics with Vdd = 0.8V

The analog inverter can operate in weak inversion� through moderate to strong inversion�Hence equilibrium current �Ibec from 0.4nA to 2.0μA� as we can see of the output voltagein �gure �� The output signal is almost rail�to�rail� it is 13.5mV from Vss and 40mVfrom the Vdd� This gives an output voltage amplitude of � �� mV�

As long as the equilibrium current� Ibec is less than 1μA� the output voltage isalmost analog inverting the input� hence the gain is �� With Ibec more than 1μA�the transistors are in strong inversion� and the output voltage is not perfectly analoginverted� the gain is less than ��

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−1.4

−1.2

−1

−0.8

−0.6

−0.4

−0.2

0Measured analog inverter gain

Vin (V)

Gai

n

Increasing Ibec

Figure �� Measured output gain versus Ibec of the analog inverter ��

If we are increasing the equilibrium current� we get less gain as shown in �gure�� This can be explained when the transistors are going from weak inversion tostrong inversion� The gain is decreased when the output is getting closely to the supplyrails� due to the linear region of the transistors�


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−1

−0.9

−0.8

−0.7

−0.6

−0.5

−0.4

−0.3

Vin [V]

Gai

n

Measured analog inverter gain

Vdd= 0.5 V Vdd = 0.3 VVdd = 0.8 V

Vdd = 0.5 V

Figure �� Measured gain of the analog inverter ��

Figure �� shows the gain of the analog inverter� As we can see the linear regionof the gain is 0.1V to 0.65V �


Figure �� shows the output voltage of the analog inverter with Vdd = 0.5V � andequilibrium current from 0.14nA to 300nA� The output swing is 42mV from Vdd and6mV from the Vss� which is almost rail�to�rail� and output voltage amplitude is ��mV�

The linear region of the gain as shown in �gure �� is 0.15V to 0.37V with supplyvoltage of ��V�


The output voltage of the analog inverter with the supply voltage of �� V� is just shownwith equilibrium current from 0.1nA to 0.4nA� The output swing is 45mV from Vddand 7mV from the Vss� which gives the output voltage of � �mV�

The linear region of the gain is 0.15V to 0.2V as shown in �gure ��

The Quality of a Analog Inverter

If focusing on �gure �� we do notice that the analog inverter are able to operatefrom weak inversion through moderate to strong inversion� hence equilibrium current


Ibec from 0.4nA to 2μA� with Vdd = 0.8V � then the gain is from �� to �� With apower supply of �� V and equilibrium current ranging from 0.1nA to 1μA� the gain isfrom �� to ��

10−10

10−9

10−8

10−7

10−6

10−5

−1.02

−1

−0.98

−0.96

−0.94

−0.92

−0.9

−0.88

Ibec [A]

Gai

nMeasured analog inverter gain

Vdd = 0.8 VVdd = 0.5 V

Figure �� Measured gain versus Ibec of the analog inverter ��

The Output Current of an Analog Inverter

If we combine equation �� and �� and assuming ki = kr = k� we get the outputcurrent�

Iout = In − Ip = 2Ibecsinh{K(Vin + Vout −Vdd2)} ��

where K = knUT

� The output current is sinh shaped� which gives the same shape asthe output current of an inverter� as the measured output current shows in �gure ��This means that the circuit can be used either as an input stage or as an output stage�If we are using it as an output stage� we can add a bias control� The output current isthen given by�

Iout = In − Ip = 2Ibsinh{K(Vin + Vout −Vdd2)} ��

where K = knUT

and Ib = Ibecexp{kbnUT(Vdd2 − Vb)}�


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−3

−2

−1

0

1

2

3x 10

−6 Output current of the analog inverter #2

V in (V)

I out

(A

)

Figure �� Measured output current of an analog inverter

�� The Floating�Gate Analog Inverter ��

The �oating�gate analog inverter �� in �gure �� is made of four transistors and havea bias control voltage input� The analog inverter �� is implemented with Ci = 18.4fF �Cr = 6fF � The transistors are U�shaped with l = 0.6μm and w = 10μm�

The input stage is a digital inverter� and therefore the currents on the input stagein �gure �� are given by�

Ipi = Ibecexp{kinUT(Vdd − Vin1)} ��

Ini = Ibecexp{kinUT(Vin1 − Vdd)} ��

And the output stage is a linear output stage also called a diode coupled stage� and thecurrent can be expressed as�

Ipr = Ibecexp{krnUT(Vdd2− Vout)} ��

Inr = Ibecexp{krnUT(Vout −

Vdd2)} ��


#

6.00fF

Ci

Ci

Vin1

Ipr

InrIni

Ipi

Cr

Vout

Cr18.4fF

18.4fF

6.00fF

10/0.6

10/0.6 10/0.6

10/0.6

��

��

��

��

Figure �� The �oating�gate analog inverter ��

Analog Inverter �� The Output Characteristics with Vdd = 0.8V

Figure �� shows the output voltage of the analog inverter with equilibrium currentsfrom 4.8nA to 98nA�

When the equilibrium current is small� the n�MOS does not work properly� and itis not pulling all the way to the rail� When the equilibrium current is more than 30nAthe output swing is almost rail�to�rail� it is approximately �mV from the Vdd and Vsssupply rails� This gives an output voltage swing of 780mV �

The output gain and linearity is controlled by the capacitive division factor ki andkr� by using a slightly smaller kr we can compensate for the Early e�ect� If we dochange the capacitive division factor ki and kr we will be able to change the gain� Wehave Ip1+Ipr = Ini+Inr� assumimg kr " 3ki� It gives the output voltage Vout = {

Vin3 }∗�

Figure �� shows the output current with increasing equilibrium current from4.8nA to 98nA� The maximum output current Imaxout � with equilibrium current Ibec =98nA� is 2.8μA� and with equilibrium current Ibec = 4.8nA the Imaxout is 0.25μA�


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8Output voltage Ibec 4.8nA − 98nA Vdd = 0.8 V

Vin [V]

Vou

t [V

]

Increased Ibec

Increased Ibec

Figure �� Measured output voltage of the analog inverter �� Vdd = 0.8V

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−3

−2

−1

0

1

2

3x 10

−6 Output current Ibec 4.8nA − 98nA

Vin [V]

Iout

[A]

Increasing Ibec

Increasing Ibec

Figure �� Measured output current of the analog inverter �� Vdd = 0.8V


Figure �� shows the transconductance Gm� We can see transconductance is in�creasing when approaching the supply rails� This is an interesting feature of a sinhampli�er� because traditional ampli�er has a tanh shaped current� where the transcon�ductance decreases due to transistors operating in the linear region�

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

1

2

3

4

5

6x 10

−7 Transconductance Gm

of the additive analog inverter (Vdd

=0.8 V)

Vin1 [V]

Gm

[mho

]

0.14nA < Ibec

< 120nA

Figure �� Measured transconductance �Vdd = 0.8V

When looking at the relative transconductance shown in �gure �� the equilibriumcurrent is in a range from 0.14nA to 120nA� we do notice with increasing equilibriumcurrent Ibec� the output current is getting more linear� since the transistors are in stronginversion�


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

10

20

30

40

50

60

70

80

90

100

Nomalized Gm

with increasing Ibec

Vin1 [V]

Nor

mal

ized

Gm

[%]

Increasing Ibec

Figure �� Measured relative transconductance� Vdd = 0.8V


Figure �� shows the output voltage with equilibrium current from 1.4nA to 130nA�With a to small equilibrium current the voltage output swing is not rail�to�rail� it is notpulling all the way to the rails� For an optimal equilibrium current� the output reacheswithin 10mV from each rails� this gives an output voltage swing of 480mV �

The �gure �� shows the output current Iout with equilibrium current from 1.4nAto 130nA� The maximum output current Imaxout is 1.6μA with equilibrium current Ibec =130nA� and the Imaxout is 40nA with an equilibrium current Ibec = 1.4nA�


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5Output voltage Ibec 1.4 nA − 130 nA Vdd = 0.5 V

Vin [V]

Vou

t [V

]

Increased Ibec

Increased Ibec


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−2

−1.5

−1

−0.5

0

0.5

1

1.5x 10

−6 Output current Ibec 1.4nA − 130 nA Vdd = 0.5 V

Vin [V]

Iout

[A]

Increasing Ibec

Increasing Ibec


CHAPTER �� ANALOG AND DIGITAL FLOATING�GATE CIRCUITS

Figure �� shows the transconductance of the analog inverter with equilibriumcurrent from 0.06nA to 74nA� We do notice the transconductance is decreased comparedto supply voltage of Vdd = 0.8V �

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8x 10



=0.5 V)

Vin1 [V]

Gm

[mho

]

0.06nA < Ibec

< 74nA

Figure �� Measured transconductance� Vdd = 0.5V

Since the output current is less sinh shaped� the relative transconductance is moreideal as seen in �gure �� hence the output current is more linear�

�� BUILDING BLOCKS IN THE FGUVMOS AMPLIFIER DESIGN �

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.510

20

30

40

50

60

70

80

90

100

Vin1 [V]

Nor

mal

ized

Gm

[%]

Nomalized Gm


Increasing Ibec

Figure �� Measured relative Transconductance� Vdd = 0.5V


Figure �� shows the output voltage with equilibrium current from 0.6nA to 68nA�

When the equilibrium current is to small� the voltage output is not rail�to�rail� weneed a certain equilibrium current to achieve an optimal voltage output swing� Theoutput reaches within 17mV from Vdd and 15mV from Vss for a optimal equilibriumcurrent� this gives an output voltage swing of 268mV � The reason why we do not getan optimal output swing� is because the transistors are reaching the linear region ofoperation�

Figure �� shows the output current Iout� with equilibrium current from 0.6nA to68nA� The maximum output current Imaxout is 0.5μA with equilibrium current Ibec =68nA� and Imaxout is 9nA with equilibrium current Ibec = 0.6nA� We do notice the Imaxout

is reduced when we are reducing the supply voltage� not surprisingly� since it follows alinear law�


0 0.05 0.1 0.15 0.2 0.25 0.30

0.05

0.1

0.15

0.2

0.25

0.3Output voltage Ibec 0.6nA − 68nA Vdd = 0.3 V

Vin [V]

Vou

t [V

]

Increased Ibec

Increased Ibec


0 0.05 0.1 0.15 0.2 0.25 0.3−6

−4

−2

0

2

4

6x 10

−7 Output current Ibec 0.6nA − 68nA Vdd = 0.3 V

Vin [V]

Iout

[A]

Increasing Ibec

Increasing Ibec



Figure �� shows the transconductance of the analog inverter with equilibrium currentfrom 0.05nA to 50nA� The output characteristic is still sinh shaped� and dercreasedcompared to supply voltage of �� V� The circuit is now operating in the linear region�

0 0.05 0.1 0.15 0.2 0.25 0.30

1

2

3

4

5

6

7x 10



=0.3V )

Vin1 [V]

Gm

[mho

]

0.05nA < Ibec

< 50nA

Figure �� Measured transconductance� Vdd = 0.3V

If looking at the relative transconductance in �gure �� we notice that the outputcurrent is more linear over the hole range of the equilibrium currents� compared to theother supply voltages�

CHAPTER �� ANALOG AND DIGITAL FLOATING�GATE CIRCUITS

0 0.05 0.1 0.15 0.2 0.25 0.320

30

40

50

60

70

80

90

100

Nomalized Gm


Vin1 [V]

Nom

aliz

ed G

m [%

]

Increasing Ibec

Figure �� Measured relative transconductance� Vdd = 0.3V

�� The Floating�Gate Additive Analog Inverter with Tunable Gain

The Floating�Gate analog additive inverter �� is an analog inverter with doubleinputs� �gure �� And it does also have a tunable gain or bias control� The inputstage is a two input digital inverter� and then the currents on the input stage in �gure�� is given by�

Ipi = Ibexp{kinUT(Vdd − Vin1 − Vin2)} ��

Ini = Ibexp{kinUT(Vin1 + Vin2 − Vdd)} ��

where the bias current Ib is�

Ib = Ibecexp{kbnUT(Vb − Vdd/2)}

The output stage is diode coupled� and the current may be expressed as�

Ipr = I∗b exp{krnUT(Vdd2− Vout)} ��

Inr = I∗b exp{krnUT(Vout −

Vdd2)} ��


InrIni

Ipi

Cb

Cb

Cr

Cr

Ci

Ipr

Ci

Ci

Cb

Cb

VoutVin2

14.2fF

14.2fF

14.2fFCi

14.2fF

Vin1

18.4fF

Vb*

Vb

Vb

Vb*

18.4fF

18.4fF

6.00fF

10/0.6

10/0.6 10/0.6

10/0.6

6.00fF

18.4fF

��

��

��

��

��

��

��

��

��

��

Figure �� The �oating�gate analog adaptive inverter

where the bias current I∗b is�

I∗b = Ibecexp{kbnUT(Vdd/2− Vb)}

The additive analog inverter is implemented with Ci = 18.4fF � Cr = 6fF andCb = 14.2fF � The transistors U�shaped with l = 0.6μm and w = 10μm� Figure �� shows the output voltage of the additive analog inverter both simulated and measured�As we can see� we have a gain less than �� obviously since Ci is larger than Cr� the biasvoltage is set to Vdd/2

Figure �� shows the e�ect of the bias control voltage� Vb from to 0.8V withtwo equilibrium currents Ibec1 = 17nA �dotted� and Ibec2 = 100nA �solid�� The supplyvoltage is 0.8V � and the voltage input Vin2 = Vdd/2� We do notice that the dynamicrange of the output voltage or the gain of the circuit� controlled by the bias voltage� isdecreased with increasing Ibec�

The output characteristics of the output current with two equilibrium currentsIbec1 = 17nA �dotted� and Ibec2 = 100nA �solid� and with supply voltage of 0.8V �is shown in �gure �� If we do increase the equilibrium current Ibec� the maximumoutput current� Imaxout � is increased� hence with increasing equilibrium current Ibec� thegain is decreased and output current Iout is increased�


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Vin

[ V ]

Vou

t [ V

]

Simulated and measured output voltage of the analog additive inverter

SimulatedMeasured

Figure �� Simulated and measured data of the analog additive inverter

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Vin1

[V]

Vou

t [V]

Measured output voltage with bias, Ibec

= 17nA (dotted) and 100nA (solid)

Vb >> V

b*

Vb >> V

b*

Vb* >> V

b

Vb* >> V

b

Figure �� Measured output voltage of the additive analog inverter with two Ibec

currents and bias control� Vdd = 0.8V


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−8

−6

−4

−2

0

2

4

6

8x 10

−6 Measured output current with bias, Ibec

= 17nA (dotted) and 100nA (solid)

Vin1

[V]

I out [A

]

Vb* >> V

b

Vb >> V

b*

Vb >> V

b*

Vb* >> V

b

Figure �� Measured output current of the additive analog inverter with two Ibec

currents and bias control� Vdd = 0.8V

The Analog additive inverter with Vdd = 0.8V

The output characteristics of the additive analog inverter with bias is� shown in �g�ure �� If we focus at the voltage swing on the output Vout� we will see that this is aproper rail�to�rail ampli�er� the output is 2mv from Vdd and 1mv from Vss� This givesa voltage amplitude of 797mV � or �� output signal�

The �gure �� shows the relationship between the output gain and the bias voltage�With the bias control it is possible to adjust the gain and linearity� The dynamic rangeof the gain is dependent of the equilibrium current� as showed in �gure �� With aequilibrium current of 5nA the gain is adjustable from to �� with the equilibriumcurrent at 100nA the range is from �� to �� We notice� we do have a larger dynamicrange when the equilibrium current is small� this due to the increasing equilibriumcurrent� hence the transistors are approaching strong inversion�

The normalized transconductance of the additive analog inverter� is shown in �g�ure �� As mentioned earlier it is possible to adjust the linearity of the circuit withthe help of bias control� The normalized transconductance Gm shows the relationshipbetween bias and linearity� with the increasing bias voltage the output current is morelinear�


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Output voltage with different Ibec

and Bias Vdd = 0.8 V

Vin1

[V]

Vou

t [V]

Vb* >> V

b

Vb* >> V

b

Vb >> V

b*

Vb >> V

b*

Figure �� Measured output voltage of the additive analog inverter with bias control�

Vdd = 0.8V

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−4

−3.5

−3

−2.5

−2

−1.5

−1

−0.5

0

Vbias [V]

Gai

n

Measured gain of the analog inverter as a function of bias voltage

Ibec = 5nA Ibec = 17nA Ibec = 100 nA

Figure �� Measured gain of the additive analog inverter with bias control� Vdd� V


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

10

20

30

40

50

60

70

80

90

100

Normalized Gm

with Ibec

=90nA and increasing Vbias

Vin1

[V]

Nor

mal

ized

gm

[%]

Vb* >> V

b V

b* >> V

b V

b >> V

b*

Figure �� Measured normalized transconductance of the additive analog inverter


The output characteristics of the additive analog inverter with bias� is shown in �g�ure �� If looking at the voltage swing on the output Vout we will see� this is a realrail�to�rail ampli�er� it is 5mv from Vdd and 2mv from Vss� this gives a voltage amplitudeswing of 493mV � or �� output signal�

Figure �� shows the gain with increasing bias voltage� With equilibrium currentIbec = 0.5nA the gain is in the variability between �� to �� and when the equilibriumcurrent Ibec is 130nA� the gain is �� to �� If we compare these results with thesupply voltage of �� V� we will observe a reduction in the dynamic range� We donotice when the equilibrium current is increasing� the transistors going towards stronginversion� hence the bias voltage adjustment will not a�ect the output voltage in thesame amount�

The normalized transconductance of the additive analog inverter is shown in �g�ure �� The output current is more linear compared to supply voltage �� V�


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5



Vin1

[V]

Vou

t [V]

Vb >> V

b*

Vb >> V

b*

Vb* >> V

b V

b* >> V

b


Vdd = 0.5V

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−2.5

−2

−1.5

−1

−0.5

0

Vbias [V]

Gai

n

Measured gain of the analog inverter as a function of teh bias voltage

Ibec = 0.5 nAIbec = 5 nA Ibec = 130 nA

Figure �� Measured gain of the additive analog inverter with bias control� Vdd = 0.5V


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.520

30

40

50

60

70

80

90

100

Vin1

[V]

Nor

mal

ized

Gm

[%]

Normalized Gm

with Ibec

= 30nA and increasing Vbias

Vb* >> V

b V

b >> V

b*



The output characteristics of the additive analog inverter with bias� is shown in �g�ure �� The voltage swing on the output Vout is almost rail�to�rail� it is 10mv fromVdd and 8mv from Vss� which gives a voltage amplitude of 282mV � this is � � voltageoutput swing�

Let us then focus how the equilibrium current a�ectes the gain� When Ibec = 0.3nAthe gain is �� to �� and for Ibec = 70nA the gain is �� to ��gure �� Wedo also notice that the dynamic range is decreased with reduced power supply Vdd� andincreased equilibrium current�

The normalized transconductance of the additive analog inverter is shown in �g�ure �� The circuit is more linear with reduced supply voltage�


0 0.05 0.1 0.15 0.2 0.25 0.30

0.05

0.1

0.15

0.2

0.25

0.3



Vin1

[V]

Vou

t [V]

Vb >> V

b*

Vb >> V

b*

Vb* >> V

b

Vb* >> V

b


Vdd = 0.3V

0 0.05 0.1 0.15 0.2 0.25 0.3−1

−0.9

−0.8

−0.7

−0.6

−0.5

−0.4

−0.3

−0.2

−0.1

0Measured gain of the analog inverter as a function of the bias voltage

Vbias [V]

Gai

n

Ibec = 0.3 nAIbec = 2.0 nAIbec = 70 nA

Figure �� Measured gain of the additive analog inverter with bias control� Vdd = 0.3V


0 0.05 0.1 0.15 0.2 0.25 0.340

50

60

70

80

90

100

Vin1

[V]

Nom

aliz

ed G

m [%

]

Normalized Gm

with Ibec

=70nA and increasing Vbias

Vb >> V

b*

Vb* >> V

b


Output Characteristics

From equations �� we have the currents Ipi+ Ipr = Ini+ Inr� andVb = Vdd/2� assuming kr = 2ki this gives�

Vout = {(Vin1 + Vin2)/2}∗ ≡ (Vdd − (Vin1 + Vin2))/2

We know that the output gain is related to the capacitive division factor ki and kr� Thismeans that there is a relationship between input capacitor Ci and feedback capacitorCr� As mentioned in section �� the capacitive division factor can be utilized toincrease the linearity and reduced the gain� If kr = 4ki then the output voltage�Vout = {(Vin1 + Vin2)/4}∗

The bias inputs Vb and V ∗b provide a dynamic transconductance Gm and lineariycontrol� as shown earlier in �gures �� and �� In addition �gure �� shows�when Vb >> V

∗b � the total output current Iout is reduced�

The measured output characteristics of the additive analog inverter with tunablegain are shown in �gure �� If V ∗b >> Vb the output can be approximated by the sinhfunction �

Vout ≈ Vdd/2× (1− sinh{K(Vin1 − Vin2/2)}

As also shown in �gure �� and �� whereK is inversely proportional to V ∗b −Vb�and when Vb >> V

∗b the output can be approximated by a tanh function�


Vout ≈ Vdd/2× (1− tanh{K‘(Vin1 − Vin2)/2)}

where K ‘ is inversely proportional to Vb − V∗b �

Generally we can then express the output voltage as a function�

Vout = F{ Vdd − (Vin1 − Vin2)/2} ��

where F can be a sinh� tanh or a linear function depending on the bias control voltage�

00.1

0.20.3

0.40.5

00.1

0.20.3

0.40.5−3

−2.5

−2

−1.5

−1

−0.5

0

0.5

1

1.5

2

x 10−7

Vb

The output current of the additive analog inverter

Vin1

Iout

Figure �� Measured output current of the additive analog inverter

Summary of the additive Analog Inverter

With the bias voltage Vb and V ∗b we are able to make a dynamic transconducance Gmcontrol� or we can change the output voltage characteristic� The gain can be adjustwith bias control or by changing the input capacitore Ci and the feedback capacitorCr� Even if we are using a supply voltage as low as �� V� we do still have a ampli�er�OTA�� which have almost rail�to�rail performance�

The additive analog inverter is a building block with several opportunities� becauseof the tuning ability� It is possible to use it as a stand alone ampli�er� or as a linearizingelement in an OTA design�


0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

00.05

0.10.15

0.20.25

0.30.35

0.40.45

0.5

0

0.1

0.2

0.3

0.4

0.5

Vb*

The output voltage of the additive analog inverter

Vin1

Vou

t

Figure �� Measured output voltage of the additive analog inverter

�� Floating Gate Current Sum Circuit

The Floating�Gate current sum is a building block used in the OTA design of making aTanh�ampli�er �� which will have a tanh shaped output current� All of the previousblocks have a sinh shaped output current� hence we call them Sinh�ampli�ers� This isnot a stand alone circuit� The Tanh�ampli�er will be discussed in section ��

We have two kinds of current sum circuits �� it is a n�MOS and a p�MOS inputcircuit as shown in �gure ��

The output current Ip of the p�MOS circuit is given by�

Ip = In1 + In2

exp{krnUt(Vdd2− Vout)} = exp{

krnUt(V1 −

Vdd2)}+ exp{

krnUt(V2 −

Vdd2)}

And similarly the output current of the n�MOS circuit In is�

In = Ip1 + Ip2

exp{krnUt(Vout −

Vdd2)} = exp{

krnUt(Vdd2− V1)}+ exp{

krnUt(Vdd2− V2)}


V1 V2

Cr

Vb*

VbVb

Ci

Vout

Ip

In2

Ci

In1��

��

��

��

�a� N�Type

Cb

CbCb

In

Ip2Ip1V1 V2CiCi

Vb*

Vout

Cr

Vb*

Vb

��

��

��

�b� P�Type

~

n~

p

In1

In1

In2

In2Out

Out

�c� Symbols

Figure �� The Floating Gate Current Sum Circuits

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

V1 [V]

Vou

t [V

]

Simulated results of the FG current sum circuit (P−type)

V2=0.5 V

V2=0.4 V

V2= 0.3 V

V2= 0.2 V

V2= 0.1 V

V2= 0.0 V

Figure �� Simulated results of the P�Type Floating Gate Current Sum Circuits

Chapter �

The Ultra Low Voltage FGUVMOS

Ampli�er

�� Introduction

This chapter provides some examples of di�erent ampli�ers circuits implemented withFGUVMOS transistors� All circuits consist of U�shape transistors with l = 0.6μm andw = 10μm� The typical gate capacitance Cg of this kind of transistor is approximately� fF � hence the total input capacitance Ct should not be less than Cg�

The designed FGUVMOS circuits will be a Operational Transconductance Ampli��ers �OTA�� also called a transconductance element� it converts a voltage input to acurrent output� This gives�

Iout = GmVin

If we look at the di�erence between an Op�amp and an OTA� an Op amp has a veryhigh open�loop gain� and uses feedback to guarantee a linear operation over a wide rangeof operation �� A OTA uses no external feedback and their transfer and impedancefunctions are directively depended of the Gm in the OTA�

�� DC � Characteristics

The previous chapters have presented the DC�characteristics of the di�erent buildingblocks� and by connecting these di�erent building blocks together� we expect the circuitsto be working properly� We have seen that FGUVMOS circuits are rail�to�rail ampli�erswith a low supply voltage� hence they will have a suitable dynamic range even for supplyvoltages below � Volt�

��

�� CHAPTER �� THE ULTRA LOW VOLTAGE FGUVMOS AMPLIFIER

�� AC � Characteristics

Bandwidth� Gain� and Phase response

A transconductance �gm� stage converts the small�signal�di�erential input voltage� intoa current�� The formula for the small signal gm is given by �

gm =q

kT(Ib)

where qkT =

126mV q is the electron charge and k is Boltzmann�s constant� Ib is the bias

current and T is absolute temperature� At +25◦C� VT =kTq = 26mV and VT is the

thermal voltage�

The low frequency breakpoint of the ampli�er fo is given by�

fo =1

2πRoCp� ��

where Ro is the output impedance and Cp is the dominant pole capacitance�

The high frequency response is determined by gm and Cp

Vout = VdiffgmjωCp

The unity gain�bandwidth� frequency� fu is given when |Vout| = |Vdiff | and gives�

fu =gm2πCp

� ��

As we can see in equation �� if we compare the transconductance gm of a sinh and atanh ampli�er we know that a sinh ampli�er has increasing gm when it is reaching thesupply rails� hence the the sinh OTA has better frequency response when it is reachingthe rails than a tanh OTA�

The ampli�cation of a circuit� or also called the gain� is given by �

Gain = 20logUoutUin

This is also known as the voltage gain of the circuit� The cuto� frequency fc� is givenwhen the voltage gain is �� dB� The FGUVMOS ampli�ers �OTA� in this thesis isspeci�ed with open loop gain�

The phase response of a circuit describes the stability of the circuit� An oscillatorhas a phase shift of 180◦� between input and output� We have to make sure that ifwe are going to make an ampli�er� the phase margin has to be less than �180◦ at thefrequency fu� if not we will have an oscillation�

�The unity gain�bandwidth is at the point where the open loop gain is unity

�� INTRODUCTION ��

Harmonic Distortion

Harmonic distortion is distortion caused by the presence of frequencies that are notpresent in the input signal� � Total harmonic distortion �THD� of a signal� is the ratioof �a�� the sum of the powers of all harmonic frequencies above the fundamental fre�quency to �b�� the power of the fundamental frequency� �

The constructed Sinh OTA�s are more linear than tanh OTA�s� typical values of thedi�erent OTA�s is shown in the table� A way of making the FGUVMOS circuits morelinear is by using the bias voltage� If we look at the relative transconductance we canincrease the linear region� with adjusting the bias current Ib� If we could be able tomake combinations of a sinh OTA and a tanh we could make an even better linearampli�er� hence reducing the harmonic distortion�

Type � Description Linear range

� Tanh 30 − 50mV� Sinh 50 − 80mV� Tanh#Sinh 150 − 250mV Sinh�Tanh� 200 − 300mV

�Harmonic distortion is caused by nonlinearities within the device�The THD is usually expressed in dB Measurements for calculating the THD are made at the

output of a device under speci�ed conditions

� CHAPTER �� THE ULTRA LOW VOLTAGE FGUVMOS AMPLIFIER

�� OTA with Floating�Gate Circuits

�� The Simple Dierential Ampli�er

Vin1

VoutVin2

Figure �� A block diagram of the simple di�erential ampli�er

Cb

Cb

Vin1*

Cn

Vb

Vb*

In

Cn

Ip

Iout

VoutCp

Cp

Vin1

Cr

Cr

Ci

Ci

Vin2

��

��

��

��

��

��

��

��

��

��

��

��

Figure �� A simple di�erential ampli�er

By using an analog inverter and a double input inverter� it is possible to obtain asimple di�erential ampli�er �� The input stage consists of an analog inverter whichhas the characteristics covered in the previous chapter� and the output stage is a dou�ble input inverter with or without bias control� The ampli�er is shown in �gure ��Figure �� gives more detail look of the ampli�er�

The circuit is simulated with Ci = Cp = Cn = 18.5fF and Cr = 15fF � The tran�sistors are U�shaped with AMS 0.6 process parameters and l = 0.6μm and w = 10μm�

�� OTA WITH FLOATING�GATE CIRCUITS ��

If looking at the ampli�er without bias control� the output current is�

Iout = Ip − In

= Ibec[exp{kinUt(Vdd − Vin1∗ − Vin2)} − exp{

kinUt(Vin1∗ + Vin2 − Vdd)}]

= 2Ibecsinh{kinUt(Vdd − Vin1∗ − Vin2)}

if substituting Vin1∗ = Vdd − Vin1 � we get the output current �

Iout = 2Ibecsinh{kinUt(Vin1 − Vin2)}

If we are using the output stage with bias control� the output current is�

Iout = 2Ibsinh{kinUt(Vin1 − Vin2)}

where Ib = Ibecexp{kbnUT(Vb −

Vdd2 )}

The simple di�erential ampli�er is a OTA with a sinh shaped output current� hence itgives a transconductance which is increasing when it is reaching the supply rails�

Figure �� shows the simulated frequency response with equilibrium current Ibecapproximately 60nA� The voltage gain of the circuit is approximately � dB� Thefrequency respons is � MHz �#��dB�� with the phase shift of 55◦� and the roll�o�respons is �dBdecade which gives one dominant pole� The Unity Gain Bandwidth �GBW� is �� MHz and phase shift is �110◦� which makes this ampli�er design stabile�The phase response is shown in �gure � �

As we can see� it is possible to make a very simple fully functional di�erentialampli�er with the use of only four transistors�


100

101

102

103

104

105

106

107

108

109

−20

−15

−10

−5

0

5

10

15

20

25

Freqquency [Hz]

Mag

nitu

de [d

B]

Freqeuency response of a simple diff. amp

Figure �� Simulated frequency response of a simple di�erential ampli�er

100

101

102

103

104

105

106

107

108

109

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

Frequency [Hz]

Pha

se [d

eg]

Phase response of a simple diff. amp

Figure � � Simulated phase response of a simple di�erential ampli�er


�� The Sinh Ampli�er dierential in and outputs

Di�erential ampli�er with bias

A transconductance ampli�er with di�erential in and output is a very useful circuitin analog design� for instance if we are going to build a �lter section� or if we need abalanced input or output stage� The sinh ampli�er in �gure �� has di�erential outputsand inputs� The implemented ampli�er is shown in �gure �� It consists of an analoginverter� the additive analog inverter� and the output stage is an inverter� As we cansee the additive inverter is with a bias control� and this will be the gain control of thecircuit�

V-

V+

VbVb*

Vout+

Vout-

Figure �� Block diagram of the Sinh ampli�er with di�erential inputs

14.16fF

10.07fF

14.16fF

Vb

Vb*

Vb

Vb*

22.97fF

10.07fF

10.07fF

18.53fF

18.53fF

27.21fF

27.21fF

22.8fF

22.8fF

18.4fF

18.4fF

10/0.6

10/0.6

10/0.6

10/0.6

10/0.6

10/0.6

10/0.6

10/0.6

10.07fF

22.97fF

Vout-

��

��

��

��

��

��

��

��

��

��

��

��

V+

V_

��

Vout+

Figure �� Sinh ampli�er with di�erential inputs

The ampli�er is implemented with the capacitors values seen in �gure �� As been


explained in section �� we need di�erent programming voltages for the analog inverter�the additive analog inverter� and the inverter� To make the additive analog inverter towork properly we need a programming voltage larger than �� V applied to Vss� Thenthe inverter on the output is in strong inversion� This means that the drain� sourcecurrent Ids is larger than 1μA� This is the reason why the bias control circuit does nothave an e�ect on the output voltage� and is not shown�

The output current of the analog additive inverter is given by�

Iout− = Ibsinh{k

nUT(Vout− − Vdd)}

where Ib is� Ib = Ibecexp{kbnUT(Vb − Vdd/2)} and kb are the capacitive division factor�

Figure �� shows the output current of the analog additive inverter with increasingequilibrium current� and shows that this stage is working as expected�

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−8

−6

−4

−2

0

2

4

6

8x 10

−6 Output current with different bias voltage

V in

I out

Figure �� Measured output current Iout−� of the sinh ampli�er with di�erent Ibec

The measured output voltage Vout− and Vout+ are shown in �gure �� and �gure ��The input V− � Vb� and V ∗b are set to Vdd/2� If looking at the output current Iout+ onthe output stage� it is given by�

Iout+ = 2Ibecsinh{kinUT(Vdd2− Vout−)} � ��


We know from the measurement on the additve inverter that the output voltage� seenin equation �� is Vout− = F (Vdd − V+ − V−)/2� where F can be a sinh� tanh or alinear function� If we apply this in equation �� for the output current this gives�

Iout+ = 2Ibecsinh{kinUT(Vdd2− F (V− − V+)/2)} � � �

Even if not having optimal working conditions� we are able to make a di�erential am�pli�er� the o�set in the output is due to mismatch� The gain on the output stage ofthe ampli�er is approximately �� as shown in �gure �� The reason why the gain isnot higher is because the equilibrium current on the output stage is more than � μA�hence the inverter is in strong inversion� and the gain on the output is decreased� asshown in section ��

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−0.05

0.05

0.15

0.25

0.35

0.45

0.55

0.65

0.75

0.85Output voltage of the sinh amplifier

V + [V]

V o

ut [V

]

Vout−Vout+

Figure �� Measured output voltage of the sinh ampli�er

AC measurement on the ampli�er is a little di�cult to achieve� because the loadon the PAD of the designed chip� makes an dominant pole �� order low pass��lter��The simulated frequency response is shown in �gure �� The frequency response is� MHz �#��dB�� with �80◦ phase shift� The roll o� response is � dBdecade andindicates one dominant pole� The Gain Bandwidth is � MHz� with �110◦ phase shift�which indicates a stabil circuit� The total voltage gain is approximately � dB� Thephase response is shown in �gure ��

If looking at the measured output characteristics of the circuit in �gure �� we noticethe di�erence in gain of the Vout− and Vout+� which also was discovered in the simulationof the circuit� hence this is not a good balanced di�erential output� A way of solving


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−6

−4

−2

0

2

4

6

8

10

12

14

16

18

V + [V]

Gai

n

Measured gain of the sinh amplifier

Vout+Vout−

Figure �� Measured gain of the sinh ampli�er

100

101

102

103

104

105

106

107

108

109

−25

−23

−21

−19

−17

−15

−13

−11

−9

−7

−5

−3

−1

1

3

5

7

9

Frequency [Hz]

Mag

nitu

de [d

B]

Simulated frequency respons of the sinh amplifier

Figure �� Simulated frequency response of the sinh ampli�er Vdd� � V


100

101

102

103

104

105

106

107

108

109

−350

−300

−250

−200

−150

−100

−50

0

Frequency [Hz]

Pha

se [D

eg]

Simulated phase respons of the sinh amplifier

Figure �� Simulated phase response of the sinh ampli�er� Vdd� � V

this problem is by using an analog inverter on the output� as shown in �gure ��Figure �� shows the simulated output voltage Vout− and Vout+� and as we do noticethis is a proper balanced di�erential output stage�

If we should increase the total gain of the circuit we could change the gain of theadditive analog inverter� hence change relationship between the capacitors Ci and Crexplained in section �� As we can see in �gure �� input capacitor Ci is 27.1fFand feedback capacitor Cr is 6fF � Another way of increasing the gain on the outputstage� is by making the input capacitors on the output stage larger� hence the capacitorCinv is 100fF � or we could made the transistors longer�

Vb

Vin-

Vin+

Vout-

Vout+

Vb*

Figure �� Block diagram Sinh Ampli�er with di�erential in� and outputs


Cir

Cir

Cb

Cb

Cb

Cb

Cor

Cor

Co

Co

Cr

Cr

27.1fCi

CiCi

Ci

Ci

Ci

C inv

C inv

27.1f

27.1f

Vb

Vb

Vb*

Vb*

100f

6f

6f

9.99f

9.99f

9.99f

9.99f

27.1f

18.5f

18.5f

27.1f

10/0.6

10/0.6

11.2f

11.2f

18.5f

18.5f

10/0.6

10/0.6

10/0.6

10/0.6

10/0.6

10/0.6

10/0.6

10/0.6

100f27.1f

VOut +

VOut -

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��Vin -

Vin +

Figure �� Sinh Ampli�er with di�erential in � and outputs

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Vin [V]

Vou

t [V

]

Simulated output of the sinh. amp. with diff in and out

Vout +Vout −

Figure �� Simulated output voltage of the sinh Ampli�er with di�erential in � and

outputs


The Sinh Follower

Figure �� shows a voltage follower� using the sinh ampli�er in �gure ��

Vout

Vin+

VbVb*

Vin-

ki+

Ki_

Figure �� Sinh follower

If looking at �gure �� we can express output voltage�

Vout = A(ki+Vin+ − ki−Vout) � ��

Which gives the following transfer function�

VoutVin+

=ki+

1A + ki−

� ��

Where A is the ampli�cation or Gain of the circuit� and ki+ and ki− is the capacitivedivision factor on the input V+ and V− respectively� The gain of this circuit is measuredto �� like what is shown in �gure �� When focusing at the transfer function �� wedo see if we make the Ki+ a little larger than ki− we are able to make a proper voltagefollower�

The simulated result in �gure �� shows the expected output characteristic withsupply voltage �� V� hence we can make a suitable voltage follower with low supplyvoltage using FGUVMOS technology� Figure �� shows the o�set voltage betweenin and output of the circuit� The error is approximatly 1mV � in the interval from0.1mv − 499mV or �� which is acceptable�


0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0.00

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Vin

[V]

Vou

t [V]

Simulated output voltage of the sinh follower

Vin Vout

Figure �� Simulated output of the Sinh follower

0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0.00

1

2

3

4

5

6

7

8x 10

−3 Simulated difference Vin − Vout of the sinh follower

Vin [V]

Vin

−V

out [

V]

Figure �� Simulated �Vin � Vout� of the sinh follower


�� Transconductance ampli�er with dynamic load

Another way of designing a fully di�erential FGUVMOS transconductance ampli�er isshown in �gure �� This is structure based on the Bram Nauta�s transducer element�� but this is not exactly similar� since Nauta uses six CMOS inverters� Nautaalso used the supply nodes to control the transconductance� and an additional circuitfor the bias control�

Vin2

Vout2

Vout1

Vin1

Figure �� Transconductance ampli�er with dynamic load

Inv1

Inv2

A_inv4A_inv3

Cr

Cr

Ca Cb

Cr

Ca

Cr

Ca

Ca

Cb

Cb

Ci

Ci

Ci

Ci

in2

in1V

V

VV

V bV

b* b*

b out2

out2

Cb

V

out1

V

I

out1

I��

��

��

��

��

��

��

��

��

��

��

��

��

Figure �� Transconductance ampli�er with dynamic load

Since the circuit has no internal nodes� there are no parasitic poles� The analoginverters A$inv� and A$inv � are shunted resistance� connected between the outputnodes and the common mode voltage Vdd/2� The value of these resistance is 1/gm3� and


1/gm4 which is the transconductance of the analog inverters� These elements is makingthe output resistance dynamic� The transconductance are at the maximum for commonmode output signals� and minimum for di�erential output signals�

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−5

−4

−3

−2

−1

0

1

2

3

4

5x 10

−6 Measured output current of the transconductance amplifier

V in1

I out

1

Figure �� Measured output current with di�erent bias control voltage

Focusing at the output current in �gure �� for a supply voltage �� V� we do noticethe bias control does not a�ect the output current� This is because the inverter on theinput is in strong inversion� however� as seeing in �gure �� it is possible to changethe gain of the circuit�

This ampli�er is implemented with the same building blocks as presented earlier�the inverter and the analog inverter� with Ci = 18.4fF � Cr = 14.2fF � Ca = 18.4fFand Cb = 10fF


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−3

−2.5

−2

−1.5

−1

−0.5

0Measured gain with different Bias

Vin1 (V)

Gai

n

Figure �� Measured gain of the transconductance ampli�er with dynamic load

�� Transconductance ampli�er Vdd = 0.8V

The measured output voltage on Vout1 with di�erent bias voltages and Vin2 =Vdd2 � is

shown in �gure �� The equilibrium current of the inverter Inv�� is 0.4μA� The outputvoltage swing is almost rail�to�rail� it is �� mV from supply rail Vdd and � mV from therail Vss� This gives a total voltage amplitude of �� mV�

Figure �� shows the e�ect of the bias control� as we can see it is possible to adjustthe gain from −0.6 to −2.7� If we should need more ampli�cation it is possible to makethe �oating gate capacitors on the input of the inverter Ci and Ca larger� or if we doneed a larger dynamic adjustment range on the output� we could made the bias controlcapacitors Cb larger�


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8Measured output voltage

Vin1

[ V ]

Vou

t [ V

]V

b << V

b*

Vb* << V

b

Vb << V

b*

Vb* << V

b

Figure �� Measured output voltage with di�erent bias control voltage

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8−3

−2.5

−2

−1.5

−1

−0.5Vdd = 0.8 V Measured gain of the transconductance amplifier with gain control

Vbias [V]

Gai

n




If we are reducing the power supply to Vdd = 0.5V we do still have a proper outputswing� as shown in �gure �� The equilibrium current on the inverter Inv�� is 120nA�The output signal is � mV from the rail Vdd and �� mV from the rail Vss� This givesa total voltage output of � mV�

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45


Vin

[ V ]

Vou

t [ V

]

Vb << V

b*

Vb* << V

b

Vb* << V

b

Vb << V

b*


The output gain with di�erent bias voltage is shown in �� when Vb >> V∗b the

gain is −0.70 and when V ∗b >> Vb the gain is −2.1� We do still have a reasonabledynamic range even with a �� V supply voltage�


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−2.2

−2

−1.8

−1.6

−1.4

−1.2

−1

−0.8

−0.6Vdd = 0.5 V Measured gain of the transconductance amplifier with gain control

Vbias [V]

Gai

n



If we are using a supply voltage of only �� V� we are approaching a limit of operation�The equilibrium current is �� nA� The output signal is �� mV from the rail Vdd and�� mV from the supply rail Vss� The output voltage swing is still satisfying� and givesa total amplitude of �� mV�

The measured gain in �gure �� is −1.15 to −1.9� We do notice that with reducedsupply voltage� we get a reduced dynamic range of the bias control�


0 0.05 0.1 0.15 0.2 0.25 0.30

0.05

0.1

0.15

0.2

0.25


Vin1

[ V ]

Vou

t [ V

]

Vb << V

b*

Vb* << V

b

Vb << V

b*

Vb* << V

b


0 0.05 0.1 0.15 0.2 0.25 0.3

−1.8

−1.7

−1.6

−1.5

−1.4

−1.3

−1.2

−1.1Vdd = 0.3 V Measured gain of the tranceconductance amplifier with gain control

Vbias [V]

Gai

n



Freqency response of the Transconductance Ampli�er

There is not done any measurements of the bandwidth of this circuit� The simulatedfrequency response with supply voltage Vdd at �� V� is presented in �gure �� Thevoltage gain is � dB� and the bandwidth is �� MHz �#��dB�� with �60◦ phase shiftas shown in �gure �� The Gain Bandwidth is �� MHz and the phase shift is −75◦�This result indicates the the stability of the circuit is satisfactory�

100

101

102

103

104

105

106

107

108

109

−15

−13

−11

−9

−7

−5

−3

−1

1

3

5

7

9

Frequence [Hz]

Vol

tage

gai

n [d

B]

Simulated frequency respons of the transconductance amplifier with dynamic load

Vout1

Figure �� Simulated frequency response of the transconductance ampli�er with dy�

namic load

�� TANH AMPLIFIERS ��

100

101

102

103

104

105

106

107

108

109

0

20

40

60

80

100

120

140

160

180

Frequency [Hz]

Pha

se [

Deg

]

Simulated phase response of the transconductance amplifier with dynamic load

Vout1

Figure �� Simulated phase response of the transconductance ampli�er with dynamic

load

�� Tanh Ampli�ers

As mentioned in the introduction of this chapter� by making combinations of a tanhand a sinh OTA� it is possible to make a more linear ampli�er� However if we are goingto use the same building blocks� we have to �nd a combination of the designed circuitswhich gives us a tanh shaped output current� The tanh�ampli�er �� gives us what wewant� It is made by combining an analog inverter with a current sum circuit presentedin chapter �� and the output stage with the n�MOS and the p�MOS is just a summingcircuit�

The Tanh ampli�er is shown in �gure �� and �gure �� The simulated DC�characteristics is shown in �gure �� As we can see� it is possible to make a compactrail�to�rail FGUVMOS OTA� with tanh shaped current� which we can use as a singleampli�er or combinined with a sinh�ampli�er to make a linear OTA�


Ip

Co

In

Cb

Co

Co

Co

Cb

Vb

Vb*

Vout

Iout

V1

V2

Vb

Vb

n~

Vb

��

��

��

��

��

Figure �� The Tanh ampli�er ver ��

Co

p

Co

Co

~

Co

Cb

Cb

A1

A2

Vx

Vy

In

Ip

Vb*

Vb

V2

Vout

Iout

V1

Vb

Vb

Vb

Vb

n~

��

��

��

��

��

��

��

��

Figure �� The Tanh ampli�er ver ��

�� TANH AMPLIFIERS ��

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

V1

[V]

Vou

t [V]

Simulated output voltage of the Tanh amplifier

A1 Vy Vx Vout

Figure �� Simulated output voltage of the Tanh ampli�er

The output current of the tanh ampli�er in �gure �� can be expressed�

Ip = Ibexp{knUT(Vdd2 − Vdd − V1]} × exp{

knUT(Vdd2 − Vx)}

= Ib(exp{ k

nUT(V1−

Vdd2)}

exp{ knUT

(Vx−Vdd2)})

= Ib(exp{ k

nUT(V1−

Vdd2)}

exp{ knUT

(V1−Vdd2)}+exp{ k

nUT(V2−

Vdd2)})

In = Ib(exp{ k

nUT(V2−

Vdd2)}

exp{ knUT

(V1−Vdd2)}+exp{ k

nUT(V2−

Vdd2)})

Iout = Ip − In

= Ib(exp{ k

nUT(V1−

Vdd2)}−exp{ k

nUT(V2−

Vdd2)}

exp{ knUT

(V1−Vdd2)}+exp{ k

nUT(V2−

Vdd2)})

= Ibtanh{k

2nUT(V1 −

Vdd2 − (V2 −

Vdd2 ))}

= Ibtanh{k2nUt(V1 − V2)}

where ko = k and Ib = Ibecexp{kbnUT(Vb −

Vdd2 )}�

The simulated output current of the Tanh ampli�er is shown in �gure ��


0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−10

−8

−6

−4

−2

0

2

4

6

8x 10

−8

V1

I out

Simulated output current of the Tanh amplifier

Figure �� Simulated output current of the Tanh ampli�er

Chapter �

Conclusion and Further

Improvements

�� Summary

This thesis has presented some fully functionals OTA�s� constructed with UV�ProgrammableFloating�Gate Transistors�FGUVMOS�� The measured results are presented and ana�lyzed�

�� FGUVMOS Design

The programming technic used to tune the FGUVMOS circuits is veri�ed� and it isshowed how easy it is to change the equilibrium current of di�erent circuits�

The di�erent building blocks like digital inverters� analog inverters and analog ad�ditive inverters constructed in FGUVMOS design� are working well on their own anddo operate as expected� They have all rail�rail voltage swing� both on the input and onthe output�

The DC�characteristics shows appropriate performance even with low�voltage oper�ations� Theoretical these OTA�s may function with a supply voltage as low as �mV�4UT �� The measured results with �� V� which is far below any commercial OTA design�shows that the circuits are working as we could expect�

The AC�Characteristics is just simulated� but shows suitable results with a low�voltage supply� The designed OTA�s� have a bandwidth more than � MHZ� and wellcontrolled phase response� hence a stabile constructed ampli�er design�

We did face one problem in the UV�programming of the circuit� the di�erent build�ing blocks needed di�erent programming voltages to operate together� Assuming anoperation range with equilibrium current Ibec in weak to moderate inversion� shown inthe table with Vdd = 0.5V �

��

� CHAPTER �� CONCLUSION AND FURTHER IMPROVEMENTS

Building Block Equilibrium current Programming Voltage VssDigital Inverter 1nA � 1μA 1.6− 2.4VAnalog Inverter 1nA � 1μA 2.3− 3.4VAnalog Additive Inverter 1nA � 1μA 3.0− 5.0V

As focused in the table above� it is not easy to connect these blocks together� we do noticeif we are building a block between a Digital inverter and a Analog additive inverter� itis not possible to make optimal combinations� One solution is to have separate supplysof di�erent building blocks� This will make it possible to program the circuit� as we doexpect�

�� Further Improvements

The objective of making a total linear ampli�er� is possible by making OTA�s with thehelp of FGUVMOS transistors� We know by using combinations of a sinh and a tanhOTA�s� it is possible to increase the linearity� for instance by making the output currentIout as a function sinh(tanh(Vin1 − Vin2))� however� there is also another solution�What if we could make an OTA with a arcsinh shape� we could make an almost linearampli�er� hence Iout = sinh(arcsinh(Vin1 − Vin2))�

When we are going to program an analog or digital FGUVMOS circuit with UV�light� we want to use the supply rails as programming terminals� hence the same pro�gramming voltages on the entire chip� At this moment we have not solved this problem�Perhaps changing the length and width of the transistors� and changing the size of theUV�hole in di�erent blocks� can be a solution� This is what we have to look more closelyto in the future� and is left open for further investigation�

The Future Plans

Working with this thesis� have made a growing interest for FGUVMOS design� whichhopefully will lead to some interesting articles in the future�

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Parameters� AMS� �� Document�� Revision��B�

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��

�� BIBLIOGRAPHY

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Oslo� Feb� �� Submitted to Kluver�

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�� Motorola Data Sheet� MC�� One Volt SMARTMOS Rail to Rail Dual

Operational Ampli�er� Motorola Inc� ��

BIBLIOGRAPHY ��

�� T� Shibata and T� Ohmi� A Functional MOS Transistor Featuring Gate�Level Weigheted Sum and Threshold Operations� IEEE Transactions onElectron devices� �� &� ��

�� Yngvar Berg Tor Sverre Lande and Sigbj%rn N�ss� Low Voltage Floating�GateCurrent Mirror� ASIC�� Portland� pages �� & � � ��

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�� K� Yang and A�G Andreou� AMultiple Input di�erential Ampli�er Based onCharge Sharing on a Floating �Gate MOSFET� Journal of Analog IntegratedCircuits and Signal Processing� ��

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