DESIGN OF LOW POWER TPG USING LP-LFSR
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Transcript of DESIGN OF LOW POWER TPG USING LP-LFSR
DESIGN OF LOW POWER
TPG USING LP-LFSR
OUTLINE
• INTRODUCTION
• LITERATURE SURVEY
• BIST
• LFSR
• CUT
• MISR
• LP-LFSR
• TRANSITION COMPARSION
• POWER COMPARSION
• TECHNICAL SPECIFICATION
• CONCLUSION
• REFERENCES
OBJECTIVE
Comparison
of power
consumptions
between
LFSR and
LP-LFSR
INTRODUCTION
• This topic presents a test pattern generator which is
more suitable for Built in self test (BIST) structures
used for testing of VLSI circuits.
• The purpose of the BIST is to reduce power dissipation
without affecting the fault coverage.
• The proposed scheme is evaluated by using a Braun
array multiplier.
LITERATURE SURVEY
• Y.Zorian[1] presented that the power dissipation of a
system in test mode is more than in normal mode.
• Mechrdad Nourani[2] presented low transition test
pattern generator (LT-TPG) which reduces the average
and peak power of a circuit during test.
• The above said techniques can reduce the average power
compared to traditional linear feedback shift register
(LFSR).
BIST BLOCK DIAGRAM
TPG TEST PATTERN GENERATOR
CUT CIRCUIT UNDER TEST
ORA OUTPUT RESPONSE ANALYSER
ORA CUT TPG
TEST CONTROL
PASS/
FAIL
BIST
• BIST controller Unit (BCU): It controls the test execution. It
manages the TPG, ORA and CUT.
• Test pattern generator (TPG): It generates the test patterns
for the CUT. It is a dedicated circuit or a microprocessor. The
patterns may be generated in pseudorandom or
deterministically.
• Circuit Under Test (CUT): It is the portion of the circuit
tested in BIST mode. It can be sequential or combinational.
• Output Response Analyser(ORA): It analyses the sequence
value of CUT and compares it with the expected output.
CONT’D
LFSR
• A Linear feedback shift registers (LFSR) is a special type
of sequence generator.
• They can generate exhaustive and / or pseudorandom
patterns.
• The typical components of an LFSR are D flip-flops and
XOR gates.
• We can use polynomial algebra to predict LFSR behavior.
Typically has (2n -1)states.
Coefficients= 𝐶0, 𝐶1, 𝐶2 , 𝐶3, 𝐶4 = 1 if connection , else = 0 no connection
𝑋4 (degree of polynomial & primary feedback) , 𝑋0 = 1 (principle input to shift register)
Characteristic Primitive polynomial =1+ 𝑿𝟑+ 𝑿𝟒
𝐶0 = 1, 𝐶1= 0 , 𝐶2 = 0, 𝐶3= 1, 𝐶4=1
Reciprocal polynomial, P*(x) , P*(x) = 𝑿𝟒 P(1/x)= 𝑿𝟒 +X+1
CHARACTERISTIC EQUATION OF AN LFSR
𝑋0 𝑋1 𝑋2 𝑋3 𝑋4
𝐶0 𝐶1 𝐶2 𝐶3 𝐶4
Clk
D Flip
Flop
D Flip
Flop
D Flip
Flop
D Flip
Flop
Rst
Q3 Q2 Q1 Q0
XOR
CLK
D
NAND NAND
NAND NAND
NAND
Q
D FLIP-FLOP
D Q
0 0
1 1
LFSR SIMULATION
BRAUN ARRAY MULTIPLIER
+
+ A1B1
A0B1 A0B0
A1B0
0
0
P1 P2 P3 P0
• The simplest parallel multiplier
is the Braun array.
• Braun’s multiplier is an n × n
bit parallel multiplier.Generally
known as carry save multiplier.
• It is constructed with n × (n-1)
adders.
P=AB= (𝑨𝐢𝒏−𝟏𝒋=𝟎
𝒏−𝟏𝒊=𝟎 Bj)2
i+j
XO
R
XO
R
OR
AN
D
AN
D
AN
D
AN
D
AN
D
AN
D
Cin
P0 P1 P2 P3
Q3 Q2 Q1 Q0
XO
R
XO
R
OR
AN
D
AN
D
Q0 Q1 Q2 Q3
FULL
ADDER
FULL
ADDER
MISR
Clk
D Flip
Flop
D Flip
Flop
D Flip
Flop
D Flip
Flop
Rst
d[0]
d[3]
d[2] d[1]
Q[3] Q[2] Q[1] Q[0]
XOR XOR XOR XOR
MISR
• Multiple Input Signature Register designed for signature
analysis.
• MISR are frequently implemented in BIST designs, in which
output response are compressed by MISR.
• These test vectors are applied to the circuit under test and the
output is fed to the MISR. MISR computes the signature.
• When all the test vectors are applied to the circuit, the
signature computed by the MISR is compared with a reference
value learned from a fault free replica of the circuit under test.
If the signatures match, the circuit is considered as fault free
and sets the outputs PASS/FAIL
BIST SIMULATION
ALGORITHM FOR LP-LFSR
• It consists of 4-flip flops in series. A common clock signal is applied for all flip flops as control signal.
• For swapping the output of adjacent flip flops, multiplexers are used.
• The output of the last stage flip flop is taken as a select line. If the output of last stage flip flop is Zero, no swapping will be carried out.
• If the output of last stage flip flop is one, any one of the flip flop output is swapped with its adjacent flip flop output value.
CONT’D
• From other flip flops, the output will be taken as such.
• If the LFSR is moved through a complete cycle of 2n-1 states
then expected transitions are 2n-1.
• When the output of the adjacent flip flops are swapped, the
expected transitions are 2n-2. Thus, the transitions produced
can be reduced to about 50% compared with original LFSR.
LP-LFSR
D Flip
Flop
D Flip
Flop
D Flip
Flop
D Flip
Flop
Rst
Clk
0 1 0 1 0 1 0 1
Q[3] Q[2] Q[1] Q[0]
MUX MUX MUX MUX
XOR
SELECT OUTPUT
0 D0
1 D1
2X1 MULTIPLEXER
D0
D1
SELECT
AND
AND
OR OUTPUT
NOT
COUNT LFSR LP-LFSR
1 0001 0010
2 1000 1000
3 0100 0100
4 0010 0010
5 1001 0110
6 1100 1100
7 0110 0110
8 1011 0111
9 0101 1010
10 1010 1010
11 1101 1110
12 1110 1110
13 1111 1111
14 0111 1011
15 0011 0011
LOW POWER TPG
Gray Code
generator
LP
LFSR
m-bit
Counter
CLK
CLK
K[3:0]
X[3:0]
G[3:0]
4
F[3:0]
AND
NOR
XOR
HIGH
CLK
JK
FF 0
JK
FF 1
JK
FF 2
JK
FF 3
Q0 Q1
Q2
Q3
AND AND
COUNTER
Q3 Q2 Q1 Q0 [OUTPUT]
NAND NAND
NAND NAND
J
K
CLK
S BAR
R BAR
Q
Q BAR
JK FLIP FLOP
B3
B2
B1
B0
G3
G2
G1
G0
XOR
XOR
XOR
GRAY CODE GENERATOR
• Gray code is a binary
numeral system where
two successive values
differ in only one bit.
• Gray codes are widely
used to facilitate error
correction in digital
communications
Binary Gray code
0000 0000
0001 0001
0010 0011
0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101
1010 1111
1011 1110
1100 1010
1101 1011
1110 1001
1111 1000
GR
AY
CO
DE
GE
NE
RA
TO
R
LP-BIST SIMULATION
TRANSITION COMPARSION COUNT LFSR LP-TPG
1 0001 0011
2 1000 0001
3 0100 0000
4 0010 0100
5 1001 0101
6 1100 0111
7 0110 0110
8 1011 1110
9 0101 1111
10 1010 1101
11 1101 1100
12 1110 1000
13 1111 1001
14 0111 1011
15 0011 1010
8+8+7+8 = 31 1+2+4+7 = 14
• Total number of transitions in LFSR =
8+8+7+8 = 31
• Total number of transitions in LP-TPG =
1+2+4+7 = 14
• Reduction in transitions = 31 −14
31 = 54.38%
POWER COMPARISON
Conventional
LFSR
Proposed LP-
LFSR
Proposed LP-
TPG
Total Power
Dissipation (mW)
84.30 63.93 73.74
Dynamic Power
Dissipation (mW)
24.28 4.10 13.83
Static Power
Dissipation (mW)
60.02 59.83 59.91
HARDWARE:
• FPGA SPARTAN 3
(XC3S400-5TQ144).
TECHNICAL SPECIFICATION
SOFTWARE:
• ISim for Simulation.
• Xillinx for power calculation.
LANGUAGES:
• VERILOG.
ADVANTAGES
• High Speed.
• The proposed method gives better power reduction
compared to the exiting method.
• Easy to test for faults.
• Very little hardware.
APPLICATIONS
• Military cryptography.
• Communication system jamming.
• Error detection and testing.
• Can be used as fast counters.
• Computer graphics.
CONCLUSION
• A LP-TPG has been proposed which consists of a
modified low power linear feedback shift register
(LP-LFSR).
• Thus, the proposed method reduces the power
consumption during testing mode with minimum
number of switching activities using LP-LFSR
instead of conventional LFSR.
REFERENCES
• A.Kavitha, G.Seetharaman, T.N.Prabhakar and Shrinithi.S
“Design of Low Power TPG Using LP-LFSR”, 2012 third
international conference on intelligent systems modeling and
simulation.
• BOYE and Tian-Wang Li, ”A novel BIST scheme for low
power testing”, 2010 IEEE.
THANK YOU