Design of High Efficiency DC-DC SMPS
Transcript of Design of High Efficiency DC-DC SMPS
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Design of HighDesign of High--efficiency DCefficiency DC--
DC Power Converter CircuitsDC Power Converter Circuits
Prof. Amit Patra, Department of EE &
Advanced VLSI Design Laboratory,
Indian Institute of Technology, Kharagpur
Advanced VLSI Design Laboratory
Why Power Management Chips Why Power Management Chips??????
Power management chips are the interface between batteries
and different chips (RF, Base-band and Digital)
Different elements need special supply voltage and have also
different requirements in terms of noise, power supplyrejection ratio (PSRR) and quiescent current
Mobile
phone
PC Private mobile
radioCamera PDA
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Power DistributionPower Distribution
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Power Management CircuitsPower Management Circuits
Linear Voltage Regulator (LDOs)
Step-Down Regulator
Switching Voltage Regulator
Buck (Step-Down) Converter
Boost (Step-Up) Converter
Buck-Boost Converter (Inverting / Non-inverting)
Switched Capacitor Converters (Charge-Pumps)
Step-Up Regulator
Step-Down Regulator Inverting Amplifier
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Linear Voltage RegulatorLinear Voltage Regulator
Simple and low noise
Output Voltage is lower than the input voltage
High efficiency only if Vo is close to Vg
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Linear Regulator Power ModelLinear Regulator Power Model
η
Linear regulator efficiency cannot be greater than the ratio o f
the output and the input voltage
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Buck Switching Voltage RegulatorBuck Switching Voltage Regulator
f s = Switching f requency
D = Duty Ratio
D’ = 1 - D
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Switching Voltage RegulatorsSwitching Voltage Regulators
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Switching Voltage Regulator
DC-DC Buck Converter DC-DC Boost Converter
DC-DC Buck-Boost Converter
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Device/Converter SpecificationsDevice/Converter Specifications
Static voltage regulation DC output voltage precision, i.e., % variation wit h
respect to the nominal value over:
input voltage range (“ line regulation”)
output load range (“ load regulation” )
temperature
Dynamic voltage regulation “ Load transient response,” including peak output
voltage variation and settling time for a step loadtransient
“ Line transient response,” including output voltagevariation and settling time for a step input voltagetransient
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Other Features/RequirementsOther Features/Requirements
Overvoltage protection
– prevents the output voltage from rising above a specifiedlimit
Undervoltage shutdown
– turns the device off if the input (battery) voltage drops
below a specified threshold
Current limiting (overload protection)
– limits the load current
Thermal shutdown
– turns the device off if the temperature exceeds a specified
threshold
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Other Features/RequirementsOther Features/Requirements
Frequency synchronization – allows synchronization of the switching fr equency to
an external system clock
Soft start – controlled output vol tage increase during startup
Shut-down and operating-mode control – enables a system controller to shut-down the device,
or to select an operating mode(PWM,PFM,LDO)
Adjustment of the output voltage using – a resistive voltage divider,
– external analog control voltage, or
– digital (pin-select) control
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Buck converter analysisBuck converter analysis
Switch 1 is ON Switch 2 is ON
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Switch in position 1Switch in position 1
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Switch in position 2Switch in position 2
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Inductor Voltage and Current WaveformsInductor Voltage and Current Waveforms
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Average Voltage across the Inductor Average Voltage across the Inductor
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Average Current across the Inductor Average Current across the Inductor
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Inductor Current Conduction ModeInductor Current Conduction Mode
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Implementing ZeroImplementing Zero--cross Detectcross Detect
With the zero-crossing comparator the switch S2 operates
as a diode, resulting in DCM and improved efficiency at light
loads
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CCM vs. DCMCCM vs. DCM
In DCM, the inductor cur rent is always positive
At l igh t loads , in DCM, the dut y cycle is s ign if ican tly low erthan in CCM
CCM operation at light loads is un desirable because thereversal of the inductor current polarity contributes toconduction losses, while it does not contribute to the outputload current
With a diode rectifier, DCM operation occurs automaticallybecause of the diode characteristic
With a synchronous rectifier, DCM operation at light loadscan be accomplished by turning off th e NMOS switch at the
zero-crossing of the inductor current
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Selection of the InductorSelection of the Inductor
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Selection of the CapacitorSelection of the Capacitor
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Switch RealizationSwitch Realization
Switch
control
signals
PMOS
Switch
NMOS switch
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Conduction LossesConduction Losses
Average and RMS values
Switch on-resistance and forward voltage drops result in switch conduction
losses
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Switching LossesSwitching Losses
Switching losses are proportional to the
switching frequency
Switching loss mechanisms:
Charging/discharging of capacitance at
MOSFET gates and sw itch node
Body-diode reverse recovery
Inductor eddy-current and core loss es
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Switching Frequency in PFMSwitching Frequency in PFM
In PFM, the switching frequency is directly proportional to the load current
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Discussion of Operating ModesDiscussion of Operating Modes
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Different Control approachesDifferent Control approaches
Hysteretic voltage control
Voltage-mode contro l The switch duty cycle is control led based on
output voltage compensation
Current-mode contro l
The switch duty cycle is control led based on
output voltage and switch current sensing
Energy based Control
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Asynchronous Buck Converter (in PSM)
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Typical Waveform
Inductor
Current
GatePulses
OutputVoltage
Hysteresis
Band
Time
Mode-I Mode-II
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Inductor Current In PSM
t
Inductor CurrentiLIP
During charging:
During discharging:
IP L is constant. => constant Volt-sec.
Vo- E=- Ldi
dt
Ton =E- Vo
IP L
dVo
dt=C
Vo
R ( i- )
di
dtVo=- L
Toff = Vo
IP L
dVo
dt=C
VoR
( i- )
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Possible Improvements
The efficiency will be lower
for lower output voltage due
to large forward diode drop in
the rectifier
The efficiency can be
improved if the diode is
replaced by a synchronous
switch
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Hysteretic Control of PSM Converter
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Ip
IL
E-IL*rds(on)
Vout
Vg
Vz
Vcomp
Vmono
Ton Toff
PMOS-On NMOS-On
Diode-On
Typical Waveforms
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Advantages and Disadvantage of HMC
Suitable for low load applications
Predetermination of inductor value and peak
inductor current
Variable frequency operation
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Voltage Voltage--Mode Control ArchitectureMode Control Architecture
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Different Blocks for VMC
Band gap reference circuit
Error Amplifier
Ramp Oscillator
PWM Comparator
Dead Time
Drivers
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Error Amplifier
High DC gain > 60db
Unity gain Bandwidth ~= 10 times crossover
Slew Rate > 10times Vdd*Fs
Pole zero compensation of LC filter
Desired loop bandwidth =~ Fs/5 to Fs/10
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Ramp Oscillator
comparator
10/2
R2
R1
v1
dd Supply Voltage
clock
vc
Vref
comparator
200/2 C
Ramp SignalLatch
RS
I
−
+
−
+
I = C * Fsw * v1
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CurrentCurrent--Mode Control ArchitectureMode Control Architecture
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Switching Regulators : Design Steps
1. Define requirements
• Range of input voltages
• Required output voltage(s)• Required output current
2. Find a suitable controller IC
• Web sites; parametric searches
• From a list of suitable IC’s, optimize forefficiency and ease of procurement
3. Read datasheet closely!
4. Find the inductor, capacitor, diode
5. Build prototype
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Switching Regulator ICsFinding Parts
Some manufacturers
www.national.com
www.maxim-ic.com
www.linear.com www.analog.com
www.ti.com
www.intersil.com
www.fairchild.com
www.st.com
Many more or design yourself ….
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Switching Regulators: Passives
Capacitors
‘Low-ESR’ tantalums: medium ESR,Sanyo’s POSCAP—no explosions!
Aluminum electrolytics: high ESR,
Cornell Dubilier’s Organic semiconductor“OSCON”—low ESR, high cost
Solid polymer aluminum: low ESR,
Diodes
Schottky diodes: low voltage drop
SMT are best
Inductors
High current-handling, low resistancerequired
SMT toroids work very well
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Switch Capacitor Circuits
or
Charge Pumps
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Motivations
Inductor-less
On-chip integration
Low cost
High switching frequency
Easy to implement (open-loop system)
Fast transient but large ripple
High efficiency but limited output power
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Ideal Dickson’s Charge Pump(Phase 1)
clk_bar
VDD Vo
C1 C2 C3
clk
VDD-Vt
2VDD-VtVDD
0
VDD
VDD-Vt
VDD-Vt
• Clk=0, Clk_bar=VDD• Finite diode voltage drops, Vt
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Ideal Dickson’s Charge Pump(Phase 2)
clk_bar
VDD Vo
C1 C2 C3
clk
VDD-Vt2VDD-2Vt
2VDD-Vt3VDD-2Vt
VDD
VDD
0
• Clk=VDD, Clk_bar=0• Maximum voltage stress on diodes 2VDD-Vt => reliability issue
• Maximum voltage stress on capacitors VCn =n(VDD-Vt) => reliability issue
VDD-Vt
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Switching Regulators : Switched Capacitor
Produce output voltage
equal to –Vin or 2 x Vin
Output noisy and poorly
regulated, but OK for
certain applications
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Applications
Flash ROM
Substrate Biasing Circuits
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Power Supply Design : Helpful Hints Efficiency not an issue? Linear regulators may be best.
Battery powered? Consider switcher for efficiency.
Vout > Vin? Use a switcher (Boost).
With switchers, stick to simple topologies like Boost andBuck. Advanced topologies not for the faint of heart!
Use a combination of switchers and linear regulators to getmultiple output voltages.
Electrical noise an issue (e.g., with A/D converters)?Strongly consider post-regulation using a linear regulator.
Need to double (2 x Vin) or invert (-Vin)? Consider acapacitive ‘charge pump’ .
Put batteries in series, not parallel. Parallel batteries canrapidly self-discharge, wasting battery life.
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Voltage Regulator Modules
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Next Generation Power Supplies
Decreasing trend of supply voltages
Higher current load together with
increased slew rate
Intel road map of CPU load voltage
and current
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Smaller inductor can be used improves dynamics
Ripple cancellation @ Vo
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Interleaving Technique
Two synchronous Buck Phase Shifted by 180 degree
Current ripple is cancelled for duty ratio of 50%
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Why Multiphase?
Current division Higher current carrying capability
Better thermal performance Low current in each phase reduces the loss and heat
generated
Use of ceramic capacitors for decoupling Inductors are in parallel during load transient fast
settling small multi-layer ceramic capacitors
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Voltage Mode Control Scheme
SW2
SW1
Rds=2m
G2
G1
Rds=2m
Rds=2m
Rds=2m
load
20m1m
ESR
S2
S1
Ramp1
Ramp2
6
VID
Vref
Vout
Ve
Vin
12V
DRIVERS
DRIVERS
+
−
A
C
DCompensator
Voltage
PID
2000uF
2m4 n
400nH
2m
D
Q’
Q−
+
D
Q’
Q−
+
+
−
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Waveforms for VMC
1. Phase shifted ( switching
period divided by number
of phases) ramps are
compared with error
amplifier output
2. D = Vea/Vramp
G2
Vea
TsTs/20 3/2Tst1 t2
Ramp2
VeaRamp1
S2
S1
G1
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Layout Issues
Power MOSFET Design
Current Carrying Capability
Maximum current limit of Metals used
Maximum current in an array
Optimization of Losses
Conduction Loss is inversely proportional to size
Switching loss is directly proportional to size
Conduction Loss = Switching Loss
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Layout of the Power MOSFET
Determine size of the single cell forfixed current carrying capability
which is fraction of total rated
current of POWER MOSFET
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Connect the devices in parallel
Source
Drain
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Array of MOSFETs
S
O
U
R
C
E
D
R A
I
N
Gate
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A POWER MOSFET
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Thank You