Design of Front-End Low-Noise and Radiation Tolerant Readout Systems José Pedro Cardoso.
-
Upload
belinda-rogers -
Category
Documents
-
view
224 -
download
5
Transcript of Design of Front-End Low-Noise and Radiation Tolerant Readout Systems José Pedro Cardoso.
Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
José Pedro Cardoso
Overview
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
2
Introduction
Training
Project
Milestones
Conclusions
Introduction
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
3
“The “GBT Project” is part of the “Radiation Hard Optical
Link Project” which aims at developing a radiation hard bi-
directional optical link for use in the LHC upgrade programs”
( http://cern.ch/proj-gbt ).
There is the need to develop new building blocks to meet
the requirements of the Front-End electronics of the future
experiments.
The goal of the project is to design one or more low-noise,
radiation tolerant circuits, either in 90 nm or 130 nm CMOS
technologies.
In the framework of GBT project, a PLL with a very low
phase noise will be designed, with built-in self-test blocks.
Tape-out of this circuit is foreseen for May 2010
Introduction
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
4
Training• On-job training• Technical Courses
Education• Doctoral
Programmeat FEUP
Project• Low-noise
Radiation Tolerant PLL
Dissemination• Conferences
Milestones• Important dates
for the project
Training
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
5
Training
Self-training
On-Job training
Interaction with experts
Training
Training
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
6
EPLF Course – “PLLs, VCOs and Frequency Synthesizers“
Ali Hajimiri Modelling and Design of High-Speed VCOs Jitter and Phase Noise in PLLs Michiel Steyaert Low-Power Crystal Oscillators Basic Concepts of PLL Topologies CMOS Prescalers & Advanced Loop Filters Integrated VCOs and Synthesizers
Ian Galton Fractional-N PLLs
John Cowles High Speed Synthesizers for Communications
ESSCIRC 2009 Conference
Training
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
7
PhD in Electrical and Computer Engineering
Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
1st semester (2009/2010) Microelectronic and Micro-electro-Mechanical Technologies Test and Design for Testability Digital Communication Systems Seminars
2nd semester (2011/2012) Advanced Microelectronic Systems Design Instrumentation and Systems Testing Measure Theory and Stochastic Processes Individual Topics
Education
Project
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
8
Top-level analisys
using MatLab
IC Design Using
Cadence
Radiation/ performace
tests
Project
Project
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
9
Phase Locked Loop – PLL
Digital communication of data is affected by noise There is the need to develop circuit that does data
recovering The PLL will act as a Jitter-filter, as well as a clock multiplier
and can be used in CDR applications. Is a feedback system that generates an output frequency
according to a reference. Compares the output and the input phase of two signals Main blocks:
Phase-Detector (PD or PFD) Voltage Controlled Oscillator (VCO) Low-Pass Filter (LPF) Divider or Pre-scaler
Project
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
10
Phase Locked Loop – PLL Based on QPLL characteristics
Crystal frequency = 80.1572 MHz Locking range = 40.0786 MHz ± 8 kHz Output Jitter < 15 ps 130 nm CMOS Technology One frequency multiplication mode: × 2 Power voltage: 1.2 V
10 GHz VCO for High-Speed Transceiver Very low-phase noise characteristics
Project
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
11
130 nm CMOS Technology
Main focus of this period was the VCO First approach to oscillator design was done
with a Colpitts oscillator. Later the cross-coupled pair and a mixture of both.
First oscillator designed at schematics level @ 1 GHz
Single-ended oscillator @ 10 GHz Differential oscillator @ 10 GHz
Project Main concerns for the VCO designer
Phase-noise Spurs Variability
How can the above effects be minimized ? Phase-noise
Phase noise in the 1/f and 1/f2 regions can be upconverted to close-in regions.
Symmetry has a tremendous impact on how AM is converted into PM noise, and can be used by designers.
A proper choice of the oscillator’s topology leads us to a better response in terms of phase-noise.
Spurs Proper design of charge-pump and filter
Variability Tank circuit designed with extra capacitors which can be
enabled/disable according to the desired center frequency.
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
12
Project
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
13
Main challenges and novelty Design of the VCO
Low phase noise Low parasitics Insensitive to process variations
Sensitive choice of VCO’s topology Design of several test blocks, that will perform
self-test/auto-calibration of the PLL during functioning
Determination of the parameters that can be controlled by the test mechanism
Project
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
14
What to expect from the circuit ?
A low noise PLL Embedded Built-in self-test
system Jitter Measuring circuit Automatic Amplitude
Control/ Automatic Gain Control
Automatic Frequency Control
Memory to save the settings of the PLL
Milestones
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
15
10th o
f May
201
0
Tape
-out
Cry
stal
PLL
1st of
Oct
ober
201
0
Rad
iation
tes
ts
25th o
f Oct
ober
201
0
Tape
-out
LC P
LL
1st of
Mar
ch 2
011
Rad
iation
tes
ts
1st o
f Aug
ust 20
11
Seco
nd p
art of
the
sec
ondm
ent
1st of
Mar
ch 2
010
Firs
t pa
rt o
f the
sec
ondm
ent
Milestones
Conferences
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
16
Targeted conferences:2010 PRIME 2010 – July 2010 TWEPP 2010 – September 2010 DCIS 2010 – November 2010
2011 IM3STW 2011– June 2011 DATE 2011– March 2011 ITC 2011– October 2011
Dissemination
Conclusions
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
17
A top-level modelling is being used to analyse and specify the system, prior to design
There are two circuits to be developed: Crystal PLL LC VCO for a 10 GHz PLL
The final versions will include self-test building blocks
Tape-out of the first circuit should be done during May 2010
By September 2010 at least one paper should have been published in one of the conferences
01-10-2009Design of Front-End Low-Noise and Radiation Tolerant Readout Systems
18
Thank you for your attention.