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ADVANCES in NATURAL and APPLIED SCIENCES

ISSN: 1995-0772 Published BYAENSI Publication EISSN: 1998-1090 http://www.aensiweb.com/ANAS

2017 June 11(8): pages 530-536 Open Access Journal

ToCite ThisArticle: C. Maheswari, B. Gowthami, K. Neelima., Design of Energy Efficient and Low Power Asynchronous 8*8 Multiplier. Advances in Natural and Applied Sciences. 11(8); Pages: 530-536

Design of Energy Efficient and Low Power Asynchronous 8*8 Multiplier

1C. Maheswari, 2B. Gowthami, 3K. Neelima

1Assistant professor, Sree vidyanikethan engineering college,Ttirupathi,A.P,Iindia. 2Assistant professor, Sree vidyanikethan engineering college,Ttirupathi,A.P,Iindia. 3Assistant professor, Sree vidyanikethan engineering college,Ttirupathi,A.P,Iindia. Received 28 March 2017; Accepted 7 June 2017; Available online 12 June 2017

Address For Correspondence: C. Maheswari, Assistant professor, Sree vidyanikethan engineering college,Ttirupathi,A.P,Iindia.

Copyright © 2017 by authors and American-Eurasian Network for ScientificInformation (AENSI Publication). This work is licensed under the Creative Commons Attribution International License (CC BY). http://creativecommons.org/licenses/by/4.0/

ABSTRACT Background: The retention of logic level and energy efficiency prove to be a big challenge for analog designers especially for high speed, high density circuits. The majority of communication systems, digital filters and modern portable equipment require multipliers. The implementation of multipliers is done by using alternative designs at various levels of abstraction but still the functionality and life time of these analog devices is degrading. Hence energy efficient designs are gaining importance in current era. One such energy efficient method used in complementary metal oxide semiconductor (CMOS) circuits is Gate diffusion Input (GDI) technique. This paper deals with simple design of full adder which is used for 8x8 multiplier. The 8x8 multiplier is designed by using the add-shift concept and is implemented for both conventional and GDI based CMOS designs. The Designs are coded in SPICE (Simulation Program with Integrated Circuit Emphasis) and simulated using Synopsys HSPICE Tools. The Parameters used for comparison are the number of transistors required, delay and power dissipation of the circuit. A hierarchical modular approach is used in coding. The area was improved by nearly 70% due to decreased number of transistors usage in GDI (Gate diffusion Input) technique. KEYWORDS: Add-Shift Concept, CMOS, GDI, Hierarchical modular Approach, SPICE,.

INTRODUCTION

The multipliers play a prominent role in designing any Electronic Devices like Cameras, DSP Systems,

Communication Media, etc. If the Multiplier is cost and area efficient and can operate at high speed, then

certainly there is a requirement of energy efficient circuit. In current scenario, the demand for portable devices

and wireless communication systems has been increased drastically, which enforces demand on high

performance processors. These Processors consumes large amount of power, due to which a cooling system is

necessary that in turn increases device area and cost. Hence development of low power solutions became crucial

in two perspectives i.e., one due to environment and the other to increase the life time of the electronic devices.

A modern technique called Gate diffusion Input (GDI) is an effective solution[3]. This paper deals with design

of an 8*8 multiplier conventionally and by using GDI. Further pass transistor based logic is used for

comparison. This method is useful to reduce the power consumption, propagation delay and transistor count.

GDI is used for low power digital circuits design technique that requires implementation of twin well

CMOS or silicon on insulator (SOI) technologies[3]. The GDI Basic cell is shown in fig.1. The GDI cell differs

from standard CMOS as it contains three inputs, P - input to the outer diffusion node of PMOS transistor, N -

input to the outer diffusion node of the NMOS transistor and G - common gate input of both the NMOS and

PMOS transistor. It can perform same as conventional standard CMOS inverting function if P is connected to

VDD and N is connected to GND or VSS, G is connected to input[3].

531 C. Maheswari et al., 2017/Advances in Natural and Applied Sciences. 11(8) June 2017, Pages: 530-536

Fig. 1: GDI basic cell

However, the transient response of GDI cell and standard CMOS inverter is same as analyzed by using the

Shockley model as shown in fig.2 [4],[5],[6]. The output level deviates from VDD by a value of Vth. Hence the

output level is VDD-Vth. So if this type of inverters are cascaded, the distinction of logic levels may be difficult

at the output.

The GDI cell can be used to develop other gates where the combinations are chosen as shown in Table.I,

where only two transistors, various functions can be performed. Hence this method proves to be area efficient,

as only two transistors are enough to implement even multiplexer. This great reduction of transistor count will

explain how powerful method it is.

Fig. 2: Transient response of GDI cell

Table I: various operations using basic GDI cell

N P G out operation

‘0’ y X

F1

y ‘1’ X

F2

‘1’ y X x+y OR

y ‘0’ X xy AND

z y X

MUX

‘0’ ‘1’ X

NOT

The design of full adder is based on fig.3, where only 10 transistors are required to implement the complete

full adder [1]. It uses only two AND gates instead of three AND gates, so it is mentioned as approximate method

[7],[8],[9]. As each XOR gate uses 8 transistors and both OR and AND gates use 6 transistors. Also as the

modified circuit uses the two AND gates rather than the three AND gates used in conventional full adder to

generate the carry output. But still the error in the output remains zero. Hence works as a normal full adder.

Fig. 3: Basic Full Adder using approximate method.

Table II: Truth Table Of Full Adder

INPUTS OUTPUTS

A B CIN S COUT

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0


1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

The full adder truth table is shown in table II for all combinations of inputs. The layout of Full Adder using

GDI technique is shown in fig.5 which was developed using Microwind Tool at 120nm Technology. The

schematic is drawn using DSCH (Digital Schematic) Tool at 120nm Technology is shown in fig.4.

Fig. 4: Schematic Diagram of GDI Full Adder

Fig. 5: Layout of GDI based Full adder in 120nm Technology

Table III: Comparison of GDI and Conventional Full adder

NUMBER OF TRANSISTORS

REQUIRED XOR GATE AND GATE OR GATE TOTAL NO. OF TRANSISTORS

CONVENTIONAL FULL ADDER 12 6 6 12*2+6*3+6 = 48

GDI BASED FULL ADDER 4 2 2 4*2+2*2+2 = 14

The table.III shows comparison of conventional and GDI based Full adders in terms of the number of

transistors required for implementation. The corresponding simulated waveforms for GDI Implemented full

adder in Synopsys HSPICE Tools are shown in fig.6. All the corresponding combinations are verified and the

logic levels are exact.


Fig. 6: Simulated waveforms of GDI based Full Adder.

Multiplier Design:

The design of asynchronous multiplier has many choices ranging from conventional Add-Shift Multiplier to

high speed Vedic multiplier. For simplicity, the 8 x 8 Add-Shift Multiplier using the GDI based full adder is

considered. This requires 64 full adders and 64 AND gates for implementation [10], [11], [12].

Fig. 6: Example of Add-Shift Multiplier

The arrangement of logic blocks is shown in figure.8. For example consider the inputs A=11001010 and

B=01010011, then the partial products and final product generated are as shown in fig.7.

Fig. 7: 8*8 Add-Shift Multiplier.

Shows the full adders and gates used in the design. The designs are implemented in conventional CMOS

logic and GDI Logic. The comparison of number of transistors required for 8x8 conventional multiplier and

8x8 GDI based Multiplier is performed in Table. IV.


Table IV: Comparison of 8x8 Conventional and GDI based Multipliers

Multiplier Design

Number of

Transistors used in

Full Adders

Number of AND Gates

Required Number of Transistors Required

8x8 Conventional Multiplier Design

48 6 48*64+6*64 = 3456

8x8 GDI based Multiplier design 14 2 14*64+2*64 = 1024

From table IV, we observe that nearly 70% of area will be saved by using GDI which aids in less power

consumption and faster circuit designs with energy efficient circuits.

RESULTS AND DISCUSSION

The designs are simulated in DSCH (Digital Schematic) Tool for schematics, Microwind Tool for Layout

and Synopsys HSPICE Tools for SPICE (Simulation Program with Integrated Circuit Emphasis) coded designs.

For 8x8 multiplier the SPICE code simulation was performed by creating Macros of Full adders as modules

and AND Gates as one module, by using them the multiplier was encoded as a hierarchical design.

Fig. 9: Simulated waveforms of input A with 8 Bits

The corresponding simulated waveforms are shown in fig. 9, for 8 bit A input for different combinations of

input waveforms.

Fig. 10: Simulated Waveforms of Input B with 8 Bits.

Fig.10 shows the 8 bit B input for different combinations of input waveforms

Fig. 11: Simulated Waveforms of Output P with 16 Bits (from P15 to P8 MSB bits of Conventional 8x8

Multiplier) Fig.11 shows the MSB 8-bits of P Output.


Fig. 12: Simulated Waveforms of Output P with 16 Bits (from P7 to P0 LSB bits of Conventional 8x8

Multiplier)Fig.12 shows the LSB 8-bits of P Output for conventional multiplier

.

Fig. 13: Simulated Waveforms of Output P with 16 Bits (from P15 to P8 MSB bits of GDI based 8x8

Multiplier)

Fig. 14: Simulated Waveforms of Output P with 16 Bits (from P7 to P0 LSB bits of GDI based 8x8 Multiplier)

Fig.14.Simulated Waveforms of Output P with 16 Bits (from P7 to P0 LSB bits of GDI based 8x8

Multiplier)Fig.14 shows the LSB 8-bits of P Output for conventional multiplier. Consider the values of A as

11100011 (decimal equivalent = 227) and B as 00001111 (decimal equivalent as 15) then the output obtained is

0000110101001101 (decimal equivalent is 3405). Both the conventional multiplier and GDI based Multiplier

yield the same result but still the difference lies in the output waveform shape is degraded in conventional

multiplier than the GDI based multiplier.

The comparison results are shown in Table V for 8x8 conventional multiplier and GDI based multiplier.

The parameters compared are the delay, power dissipation of circuit.

Table V: Comparison Of 8x8 Conventional And Gdi Based Multiplier

Multiplier Delay (nS) Power Dissipation(μW)

8x8 Conventional Multiplier 1.0100 7.7951

8x8 GDI based Multiplier 1.0100 0.0087022

The simulated results prove that the delay is same for both the circuits as the critical path doesn’t change

with the GDI Technique used. But the power dissipated by the circuit varies largely due to decrease in number of

transistors by nearly 70%. The power Dissipation decreases drastically from microwatts to nanowatts. Also the

energy is efficiently utilized but with a compromise of logic levels and clear distinguish of waveforms. Still the

logic levels are easily recognized to be at good logic level.


Conclusion:

GDI based full adder was verified successfully using SPICE code. The design was further enhanced to

support an energy efficient and low power asynchronous 8*8 multiplier. The design of multiplier was done at

transistor level of abstraction. The GDI technique proves to be a very powerful technique which reduces the area

drastically. They find applications in Digital Filters, Communication Systems, and Cameras etc. The simplest

energy efficient design of 8x8 multiplier is performed. The GDI technique saves the energy, area occupied and

power dissipation considerably. The Designs are developed in SPICE and verified in Synopsys HSPICE Tools.

The Parameters used for comparison are the number of transistors required, delay and power dissipation of the

circuit. A hierarchical modular approach is used in coding for ease of design and to suit the structure represented

directly. The area was improved by nearly 70% due to decreased number of transistors usage in GDI technique.

Also the power dissipation is reduced from microwatts to nanowatts.

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