Solid-State Electronics 124 (2016) 28–34

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Solid-State Electronics

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Design of embedded SCR device to improve ESD robustness of stacked-device output driver in low-voltage CMOS technology

http://dx.doi.org/10.1016/j.sse.2016.07.0290038-1101/� 2016 Elsevier Ltd. All rights reserved.

⇑ Corresponding author.E-mail address: cy.lin@ieee.org (C.-Y. Lin).

Chun-Yu Lin ⇑, Yan-Lian ChiuDepartment of Electrical Engineering, National Taiwan Normal University, Taiwan

a r t i c l e i n f o a b s t r a c t

Article history:Received 13 May 2016Received in revised form 27 July 2016Accepted 30 July 2016Available online 1 August 2016

The review of this paper was arranged byProf. A. Zaslavsky

Keywords:Electrostatic discharge (ESD)Output driverSilicon-controlled rectifier (SCR)

This study proposes a novel design for an embedded silicon-controlled rectifier (SCR) device to improvethe electrostatic discharge (ESD) robustness of a stacked-device output driver. A 3 � VDD-tolerantstacked-device output driver with embedded SCR is demonstrated using a 0.18 lm CMOS process withVDD of 3.3 V. This design is verified in a silicon chip, and it is shown that the proposed output driver withembedded SCR can deliver an output voltage of 3 � VDD. The ESD robustness can be improved without theuse of any additional ESD protection device or layout area. Furthermore, the proposed design can also beused for an n � VDD-tolerant stacked-device output driver to improve its ESD robustness.

� 2016 Elsevier Ltd. All rights reserved.

1. Introduction

In nanoscale CMOS technologies, the feature size has beenscaled down to improve circuit performance when used with adecreased power supply voltage for low-power applications. How-ever, higher output voltage levels, such as 3.3 V and 5 V, are alsoneeded for communication between the external I/O and othercircuits in the microelectronic systems or subsystems in some sig-naling standards. Furthermore, even higher output voltage levels,such as >5 V, are needed for some applications such as biomedicalstimulators [1,2]. Therefore, it is necessary to design a high-voltageoutput driver with consideration of high-voltage tolerance [3,4]. Toavoid overstress issue without using additional high-voltagedevice, stacking low-voltage devices are usually used for thehigh-voltage output driver [1,2,5–7]. Once the voltage drop isdivided equally across the stacked devices, this configurationallows for the higher voltage without overstressing any singledevice. A conventional 3 � VDD-tolerant stacked-device output dri-ver is shown in Fig. 1, and consists of a control circuit and a pair oftriply-stacked MOS in the output stage [8,9].

Electrostatic discharge (ESD) is a significant reliability issue thatcan cause damage in IC products [10], and the transistors currentlyused in CMOS technologies are vulnerable to ESD events. Therefore,to provide the required ESD robustness, on-chip ESD protection

design needs to be added to integrated circuits, including the out-put driver [11]. For example, a typical specification for a commer-cial IC on a human-body-model (HBM) ESD robustness is 2 kV [12].Fig. 2 shows the on-chip ESD protection for a stacked-device out-put driver, which employs the assistance of a high-voltage-tolerant ESD clamp circuit [13–16] and parasitic body-to-draindiodes. The ESD currents can be discharged from Vo to 3 � VDD

(path ①), from GND to Vo (path ②, from Vo to GND (path① +③), and from 3 � VDD to Vo (path③ +②), and this ESD protec-tion design can provide corresponding ESD current paths during allkinds of ESD events at Vo pad.

However, in the output stage, the sizes of PMOS devices areusually larger than those of the NMOS devices to deliver symmet-rical driving ability, thereby causing asymmetrical ESD currentpaths. In addition, with smaller NMOS devices, the ESD robustnessof path ② is usually lower than that of path ①, and the separatedbody of each NMOS may further decrease the ESD robustness ofpath ②. It is, however, possible for the designer to use a dummyNMOS device or additional ESD diodes to improve the ESD robust-ness. Therefore, in this study, a more efficient design is proposedusing an embedded silicon-controlled rectifier (SCR) to improveESD robustness. The technique of using an embedded SCR has beenpresented to improve ESD robustness in many other applications[17–22], but in our work we demonstrate the use of an embeddedSCR to improve ESD robustness of the stacked-device output dri-ver. With the assistance of the embedded SCR, the ESD robustnessof the NMOS part of the stacked-device output driver is improved

Fig. 1. Block diagram of 3 � VDD-tolerant stacked-device output driver.

Fig. 2. ESD current paths in 3 � VDD-tolerant stacked-device output driver withhigh-voltage-tolerant ESD clamp circuit.

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without the use of any additional ESD protection device or layoutarea, and once this discharge path is improved, both GND-to-Vo

and 3 � VDD-to-Vo ESD robustness can be boosted. This improve-ment becomes beneficial for nanoscale technologies that have areduced ESD design window.

2. Proposed ESD protection design for stacked-device outputdriver

A cross-sectional view of the NMOS part in the output stage of aconventional 3 � VDD-tolerant stacked-device output driver isshown in Fig. 3. The N-well and deep N-well regions are used toisolate the P-well region of each stacked NMOS from the commonP-substrate; there is thus no diode path from P-substrate to Vo. Thebody-to-drain (P-well/N+) diodes form the ESD current path fromGND to Vo, and a parasitic SCR (P-well/Deep N-well/P-well/N+) alsohelps to discharge the ESD current from GND to Vo; however, itspath is too long to effectively discharge the ESD current.

To enable symmetrical ESD protection ability in PMOS andNMOS parts, a stacked-device output driver with embedded SCRis proposed, as shown in Fig. 4. In the proposed design, an addi-tional P+ region is added to the N-well region, and an embeddedSCR device is then formed from GND to Vo. The N-well region isusually large enough for overlapping the fringe of deep N-wellregion, and thus an additional P+ region is not required to increasethe layout area. In the proposed design, the SCR device can besafely used without latchup danger because the anode (GND)potential is always lower than the cathode (Vo) potential duringnormal operation; therefore the SCR device cannot keep turningon.

The SCR device has been reported to be useful for ESD protec-tion [23–26]. The equivalent circuit of an embedded SCR consistsof a cross-coupled PNP (P+/N-well/P-well) and NPN (N-well/P-well/N+) BJTs. In the proposed design, the body-to-drain (P-well/N+) diodes play the role of a trigger circuit for the embedded SCRto enhance turn-on speed [23,27]. Since the diode-triggered SCRhas been investigated and shown to have a low overshoot voltage,the proposed design is capable of turning on during fast ESDevents. When ESD stresses from anode (GND) to cathode (Vo) ofthe SCR are applied, the diode path will turn on to discharge theinitial ESD currents, and the SCR path will then take over to dis-charge the primary ESD currents. The positive-feedback regenera-tive mechanism of PNP and NPN BJTs results in ensuring the SCRdevice is highly conductive to making the SCR very robust againstESD stresses.

3. Stacked-device output driver design

Fig. 5 shows the design of the stacked-device output driver,which consists of a control circuit and output stage The 3.3 V tran-sistors from a standard 0.18 lm CMOS process are used. Once thevoltage differences across each transistor are lower than 3.63 V(3.3 V + 10%), the foundry promises their reliability. The output dri-ver is controlled by an input signal (Vi) with a voltage swingbetween 0 V and 3.3 V. This design aims to allow the output signal(Vo) to swing between 0 and �10V (3 � VDD), and the voltage dif-ferences across each transistor to be lower than 3.6 V to preventreliability issues, whether the output driver is turned on or off.The output stage of the stacked MOS configuration is between3 � VDD and GND to sustain �10 V. The control circuit includes avoltage divider, two level shifters, and three buffers. The voltagedivider uses a diode-connected MOS to produce the bias voltagesof 2 � VDD (VDD2) and 1 � VDD (VDD1) from the 3 � VDD. To reducethe bias current to the range of <mA, three PMOS with smallwidth/length ratio are used. The level shifters (1 and 2) transferthe signals with a low-voltage level (1 � VDD) to high-voltage levels(2 � VDD and 3 � VDD), where level shifter 1 with a differentialstructure can transfer Vi and Vib (voltage swing: 0 V � 1 � VDD) toVi2 and Vi2b (voltage swing: 1 � VDD � 2 � VDD), respectively. Simi-larly, level shifter 2 can further transfer Vi2 and Vi2b to Vi3 (voltage

Fig. 3. Cross-sectional view of stacked NMOS devices in output stage of conventional 3 � VDD-tolerant stacked-device output driver.

Fig. 4. Cross-sectional view of stacked NMOS devices with additional P+ region in output stage of proposed 3 � VDD-tolerant stacked-device output driver with embeddedSCR.

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swing: 2 � VDD � 3 � VDD). Furthermore, the buffers controlwhether the output stage is turned on or off.

As Vi is 0 V, the gate potentials of MP1, MP2, andMP3 are designedto be 1 � VDD, 2 � VDD, and 3 � VDD, respectively, so the stackedPMOS are kept off. In addition, the gate potentials of MN1, MN2,and MN3 are all 1 � VDD, so the stacked NMOS conduct the Vo to0V. As Vi is 3.3 V, the gate potentials of MN1, MN2, and MN3 are0 V, 1 � VDD, and 2 � VDD, respectively, and therefore the stackedNMOS are kept off. Furthermore, the gate potentials of MP1, MP2,and MP3 are all 2 � VDD, so the stacked PMOS conduct Vo to 3 � VDD.

The stacked-device output driver is simulated in HSPICE withthe 0.18 lm CMOS process. Fig. 6(a) shows the simulated transientwaveforms of the stacked-device output driver under normal oper-ation. When Vi is 0 V or 3.3 V, Vib is instantaneously inverted. Vi2

and Vi2b swing between 3.3 V and 6.6 V, Vi3 swings between 6.6 Vand 9.9 V, and Vo finally swings between 0 V and 9.9 V. Fig. 6(b)shows the simulated waveforms under fast supply ramp up, whereVo can be kept off during such a fast event.

To verify that the voltage differences across each transistor arelower than 3.6 V during all Vi potentials, a ramp voltage from 0 V to3.3 V is injected into Vi; the voltage of each node is then captured.Fig. 7 shows the simulated |Vgd|, |Vgs|, and |Vds| (black symbols), andtheir projections to each plane (gray symbols), when Vi is between0 V and 3.3 V.

For MN1, each terminal is constrained to swing between 0 V and1 � VDD, as shown in Fig. 7(a). The gate potential of MN2 is main-tained at 1 � VDD, its source potential is constrained to swingbetween 0 V and 1 � VDD, and its drain potential swings between0 V and 2 � VDD. In addition, the voltage differences across eachof the MN2 terminals are still lower than 3.6 V, as shown in Fig. 7(b). For MN3, the gate potential will swing between 1 � VDD and2 � VDD, the source potential will swing between 0 V and 2 � VDD,and its drain potential will swing between 0 V and 3 � VDD. Thesimulation results show that the voltage differences across eachof the MN3 terminals are still lower than 3.6 V, as shown in Fig. 7(c). The operations of MP1 �MP3 are complementary to those ofMN1 �MN3, and therefore similar results can be found, as shownin Fig. 7(d)–(f). With this control circuit design, the PMOS andNMOS transistors in the output stage are well controlled to turnon or off. In addition, simulation results show that the voltage dif-ferences across each transistor are 3.6 V at most, which meets thedesign target.

Since the additional P+ region in the proposed design will notaffect operation of the drain, gate, source, and body terminals ofthree NMOS devices during normal operation, the simulationresults of the stacked-device output driver with embedded SCRare equal to those of the stacked-device output driver withoutembedded SCR.

Fig. 5. Schematic of 3 � VDD-tolerant stacked-device output driver.

Fig. 6. Simulated transient waveforms of 3 � VDD-tolerant stacked-device output driver under: (a) normal operation, and (b) fast supply ramp up.

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Fig. 7. Simulated |Vgd|, |Vgs|, and |Vds|, of transistors in output stage: (a) MN1, (b) MN2, (c) MN3, (d) MP1, (e) MP2, and (f) MP3.

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4. Experimental results

To verify use of the stacked-device output driver in a siliconchip, both circuits with and without the embedded SCR (outputdriver with SCR and pure output driver) are fabricated in a0.18 lm CMOS process. The embedded SCR has dimensions of10 lm, a high-voltage-tolerant ESD clamp circuit is not integratedin the chip, and each circuit occupies a chip area of 250 � 175 lm2,including 3 � VDD, GND, Vi, and Vo pads.

4.1. Transient waveforms

A 9.9 V supply voltage is used for 3 � VDD, a 3.3 V and 10 kHzsquare wave is applied to Vi, and a 100 kX resistance is loaded to

Vo before measuring the Vo swing, as shown in Fig. 8. Fig. 8(a)shows the measured waveforms of the stacked-device output dri-ver without the embedded SCR (pure output driver), and Fig. 8(b)shows those of proposed stacked-device output driver with theembedded SCR (output driver with SCR). As long as the Vi is 0 Vor 3.3 V, the Vo of both circuits can swing between 0 V and �9 V.The embedded SCR in the proposed design is kept off during nor-mal operation so that it has no effect on the transient waveforms.

The measured transient waveforms of both test circuits areshown during fast supply ramp up in Fig. 9. As a fast ramp volt-age from 0 V to 9.9 V is sent to the 3 � VDD, and Vi is connected toGND, Vo can be maintained at 0 V. The embedded SCR thereforehas no effect on the operation of the output driver under sucha fast event.

Fig. 8. Measured transient waveforms of 3 � VDD-tolerant stacked-device outputdriver under normal operation: (a) without embedded SCR (pure output driver) and(b) with embedded SCR (output driver with SCR).

Fig. 9. Measured transient waveforms under fast supply ramp up.

Fig. 10. Measured TLP I-V curves, zapping from Vo to 3 � VDD.

Fig. 11. Measured TLP I-V curves, zapping from GND to Vo.

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4.2. ESD robustness and TLP I-V characteristics

The HBM ESD robustness of each circuit is evaluated using aHBM tester. Failure criterion is defined as I-V characteristics shift-ing over 30% from its original curve after ESD is stressed at everyESD test level. Measurement results show that the Vo-to-3 � VDD

HBM robustness of both circuits is 1.5 kV; the GND-to-Vo HBMrobustness of stacked-device output driver without embeddedSCR is 0.75 kV; while that of proposed stacked-device output driverwith embedded SCR is improved to 1.75 kV.

To investigate the turn-on behavior and I-V characteristics ofthe circuits in the domain of an HBM ESD event, a transmission-line-pulsing (TLP) system with a 10 ns rise time and a 100 ns pulsewidth is used. The current-handling ability, i.e. the secondarybreakdown current (It2), of the test circuit can be obtained fromthe TLP-measured I-V curve, which are shown for both circuits inFigs. 10 and 11. When measuring from Vo to 3 � VDD, both circuitshave almost the same TLP I-V characteristics, and TLP-measured It2are �0.85 A. When measuring from GND to Vo, the embedded SCRin the proposed design can be triggered at 2.5 V, and can then belatched to 1.4 V. The GND-to-Vo It2 of the stacked-device outputdriver without embedded SCR is 0.46 A, while that of the proposedstacked-device output driver with embedded SCR is improved to0.81 A. These results indicate that both of the current paths ①and ② in Fig. 2 can be maintained symmetrical using the proposeddesign.

In this work, the symmetrical ESD protection ability in thePMOS (path ①) and NMOS (path ②) is achieved. However, it isof note that the high-voltage-tolerant ESD clamp circuit must beequipped in the real chip to complete whole-chip ESD protection.

5. Conclusions

A proposed stacked-device output driver with embedded SCR isdeveloped for on-chip ESD protection in the high-voltage-tolerantoutput stage where the signal swing can be as high as n � VDD. The

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3 � VDD-tolerant stacked-device output driver with embedded SCRis verified in a silicon chip. Without the use of any additional ESDprotection device or layout area, the proposed design is shown tohave symmetrical ESD protection ability in GND-to-Vo and Vo-to-3 � VDD paths. In addition, there is no degradation of the transientbehaviors of the proposed design during normal operation. It isthus considered that the proposed design is able to improve theESD robustness of a stacked-device output driver.

Acknowledgments

This work was supported in part by Ministry of Science andTechnology, Taiwan, under Contracts MOST 104-2220-E-003-001and MOST 105-2622-E-003-001-CC2, and in part by BiomedicalElectronics Translational Research Center, National Chiao TungUniversity, Taiwan. The authors would like to thank National ChipImplementation Center (CIC), Taiwan, for the support of chip fabri-cation. The authors would also like to thank Prof. Ming-Dou Kerand his research group in National Chiao Tung University, Taiwan,for their great help during measurement.

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