Design of digital cmos circuits by Using Standard Cell...

International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)

Volume 3 Issue 10, October 2014

ISSN: 2278 – 1323 All Rights Reserved © 2014 IJARCET 3564

Abstract: - IC development is nowadays a huge industry. There

is an almost innate amount of consumer products like mobile

phones, processors, televisions, cameras, refrigerators, ovens

and cars that in one way or another uses custom IC components.

Integrated circuits can provide anything from analog-to-digital

conversion to digital filtering and much more. A digital

integrated circuit can be manufactured with a number of

different approaches, but they all contain the same basic steps. It

all starts with transistors, wiring and all the things that make up

the circuit being placed in a layout, designed in a CAD

(Computer Aided Design) tool and ends up with that layout

being physically created on a chip. The way to create these

layout dyers depending on design requirements. Standard cell

library contains a collection of components that are

standardized at the logic or functional level, and consists of cells

or macro-cells based on the unique layout. The economic and

efficient accomplishment of an IC design depends heavily upon

the choice of the library. Therefore, it is important to build

library that fulfills the design requirement. A library of logic

cells is the set of building blocks for the ASIC design flow. The

library is typically called a standard cell library because of its

common interface implementation and regular structure. The

library provides the functional building blocks used for

synthesis and a layout representation of the cells for

place-and-route. It is very important to note that the process of

HDL synthesis limits the choice of logic cells to those that are

found in the library provided. This guarantees that a physical or

layout representation of the cells exists when the design is

implemented using place and route tools. One way to

understand the required layout characteristics of standard cells

is to understand their history and the reasons behind their

development.

Index Terms—CAD, ASIC, HDL, Libraries.

I. INTRODUCTION

Advances in the typical manufacturing process included

increasing the number of routing layers from one to two or

three metal layers. This added further complexity to the

full-custom layout design process for optimal results. .Even in

a full-custom design flow, the placement of more than 20 cells

is easier when the building-block cells are implemented with

standards. The standardization of cell interfaces is a concept

that is implemented in a library. Today the standard cell is the

foundation of ASIC design [1]. There are companies whose

sole business is the design and migration of libraries into

different manufacturing processes. Various EDA [2] vendors

provide circuit and physical design tools specifically for

libraries as

Well. Initially, a circuit is partitioned into several smaller

blocks, each of which is equivalent to some predefined

function. Within each logic block; cells are implemented from

a set of library cells. In general, the library is much smaller

than a commercial ASIC library, but the methodology is the

same.

II.OBJECTIVE OF THE SYSTEM

The objective of this project is to Design and implement High

Performance Standard Cell Library according to the

specifications and to perform transient analysis on the

implemented designs. Finally to compare there-layout and

post layout results of the cells designed at different process

corners. As explained before, an efficient implementation of a

Semi-Custom Design [3] depends on the Cells in the library.

Standard Cell Libraries often provide 300 or even 500 Cells.

It appears obvious that the design automation tool could do a

better job if the number of cells is large. But in

Newer libraries, the number of functions as well as the

number of layouts are reduced. Thesis because recent

experiments demonstrate that with fewer Cells, the design

Automation tool is more efficient as it has a limited set of

well-chosen cells to synthesize. With a fewer number of cells,

the automation tool can Easily produce an optimized result,

without getting lost in some optimization loops due to large

number of cells.

III.COST OF A SEMICONDUCTOR DEVICE

The cost of a semiconductor conductor device is the sum of

two components Recurring Expense and Non-Recurring

Expense (NRE).

The expenses that are incurred per design are called

Recurring Expenses. This includes silicon processing,

packaging, test, etc. But the Non-Recurring Expenses are the

expenses that are incurred only once for a design. This

includes design time and effort, CAD tools [4], masks, etc.

For the last few years, the NRE has been increasing

unimaginably. It is estimated that a 70-nanometer

Semi-Custom Design will have a four million dollar NRE. As

a Result of this, the companies that can afford sub-micron

Semi-Custom Design will get pretty exclusive. The graph in

Fig.1 projects the NRE cost for the current/future submicron

technologies.

Design of digital cmos circuits by Using

Standard Cell Library for high performance

Mr.P.Balaramudu, Mr.Manoj Kumar, Mr.Chape L.M., Mr.Wankhade S.S., Mr.Phalke Ulhas




Fig.1: cost variation with process geometry

Workstation tool cost includes the tool licenses, plus the

computing hardware, network and IT support, and internal

CAD tool integration expenses. One way to significantly

reduce the NRE is to utilize open source CAD tools. While

these tools are generally considered to be inferior to

commercially available tools, the quality and capabilities of

open source tools has been steadily improving over the last 5

years. Unfortunately, the quality and availability of public

domain Standard Cell Libraries [5] has not kept pace with the

development of design tools. This thesis is an attempt to

address the growing need for Standard Cell Libraries that are

intended for use with open source IC design tools. The

Standard Cell Library developed in this thesis using open

source software requires further verification, like fabricating

the circuits into silicon and testing, before the Cells can be

used for a particular Semi Custom Design. The development

process initiated in this thesis is the first step in addressing the

issue discussed above. IV.SIMULATION

After the transistor level description of a circuit is completed

using the Schematic Editor, the electrical performance and the

functionality of the circuit must be verified using a Simulation

tool. Here we have designed the various gates that are their

schematic, layout and simulation is done by using cadence

software [6]. The detailed transistor-level simulation of your

design will be the first in-depth validation of its operation;

hence, it is extremely important to complete this step before

proceeding with the subsequent design optimization steps.

Based on simulation results, the designer usually modifies

some of the device properties (such as transistor width to

length ratio) in order to optimize the performance. The initial

simulation phase also serves to detect some of the design

errors that may have been created during the schematic entry

step. It is quite common to discover errors such as a missing

connection or an unintended crossing of two signals in the

schematic. The second simulation phase follows the

extraction of a mask layout (post layout simulation), to

accurately assess the electrical performance of the completed

design. The creation of the mask layout is one of the most

important steps in the full-custom (bottom-up) design flow,

where the designer describes the detailed geometries and the

relative positioning of each mask layer to be used in actual

fabrication, using a Layout Editor. Physical layout design is

very tightly linked to overall circuit performance (area, speed

and power dissipation) since the physical structure

determines the Trans conductance of the transistors, the

parasitic capacitances and resistances, and obviously, the

silicon area which is used to realize a certain function. On the

other hand, the detailed mask layout of logic gates requires a

very intensive and time-Consuming design effort. The

physical (mask layout) design of CMOS logic gates is an

iterative process which starts with the circuit topology and the

initial sizing of the transistors. It is extremely important that

the layout design must not violate of the layout Design Rules,

in order to ensure a high probability of defect free fabrication

of all features described in the mask layout. The design flow is

shown in fig.2.

Fig.2: Design flow

A) Drc, Design Rule Check:

The created mask layout must conform to a complex set of

design rules, in order to ensure a lower probability of

fabrication defects. A tool built into the Layout Editor, called

Design Rule Checker [7] is used to detect any design rule

violations during and after the mask layout design. The

detected errors are displayed on the layout editor window as

error markers, and the corresponding rule is also displayed in

a separate window. The designer must perform DRC (in a

large design, DRC is usually performed frequently before the

entire design is completed), and make sure that all layout

errors are eventually removed from the mask layout, before

the final design is saved. Extraction: Circuit extraction is

performed after the mask layout design is completed, in order

to create detailed net-list (or circuit description) for the

simulation tool. The circuit extractor is capable of identifying

the individual transistors and their interconnections (on

various layers), as well as the parasitic resistances and

capacitances that are inevitably present between these layers.

Thus, the extracted net-list can provide a very accurate

estimation of the actual device dimensions and device

parasitic that ultimately determine the circuit performance.

The extracted net-list and parameters are subsequently used in

Layout-versus-Schematic comparison and in detailed

transistor- level simulations (post-layout simulation).

B) LVS, Layout versus Schematic Check

After the mask layout design of the circuit is completed, the

design should be checked against the schematic circuit

description created earlier. The designs called Layout versus

Schematic (LVS) [8] Check will compare the original

network with the one extracted from the mask layout, and

prove that the two networks are indeed equivalent. The LVS

step provides an additional level of confidence for the

integrity of the design, and ensures that the mask layout is a




correct realization of the intended circuit topology. Note that

the LVS check only guarantees topological match: A

successful LVS will not guarantee that the extracted circuit

will actually satisfy the performance requirements. Any errors

that may show up during LVS (such as unintended

connections between transistors, or missing

connections/devices, etc.) should be corrected in the mask

layout before proceeding to post-layout simulation. Also note

that the extraction step must be repeated every time you

modify the mask layout. Post Layout simulation: The

electrical performance of a full-custom design can be best

analyzed by performing a post layout simulation on the

extracted circuit net list. At this point, the designer should

have a complete mask layout of the intended circuit/system,

and should have passed the DRC and LVS steps with no

violations. The detailed (transistor-level) simulation

performed using the extracted net list will provide a clear

assessment of the circuit speed, the influence of circuit

parasitic (such as parasitic capacitances and resistances), and

any glitches that may occur due to signal delay mismatches. If

the results of post-layout simulation are not satisfactory, the

designer should modify some of the transistor dimensions

and/or the circuit topology, in order to achieve the desired

circuit performance under realistic conditions, i.e., taking into

accounts all of the circuit parasitic. This may require multiple

iterations on the design, until the post-layout simulation

results satisfy the original design requirements.

C) Parameters

a) Output Slew (Transition) Time

The transition times (slews) [9] on output pins are defined as

the time interval between the signal crossing 10% of Vdd and

90% of. Fig.3 illustrates transition time measurements for

rising and falling signals. Factors that affect propagation

delays and transition time include: temperature, supply

voltage, process variations, fan out loading, interconnect

loading, input-transition time, input signal polarity, and

timing constraints. The timing models provided with this

library include the effects of input-transition time on

propagation delays.

Rise time (TR): The time for a waveform to rise from 10% to

90% of its steady state value.

Fall time (FT): The time for a waveform to fall from 90% to

10% of its steady state value.

Fig.3: Transition time

b) Propagation Delay

The propagation delay through a cell is the sum of the intrinsic

delay, the load-dependent delay, and the input-slew

dependent delay. Delays are defined as the time interval

between the input stimuli crossing 50% of and the output

crossing 50% .is shown in Fig 4.

Fig.4: propagation delay

c) Timing Constraints

Timing constraints [10] define minimum time intervals during

which specific signals must be held steady in order to ensure

the correct functioning of any given cell. Timing constraints

include: setup time, hold time, recovery time, And minimum

pulse width. Timing constraints can affect propagation delays.

The intrinsic delays given in the datasheets are measured with

relaxed timing constraints (longer than necessary setup times,

hold times, recovery times, and pulse widths).The use of

shorter timing constraint intervals may increase delay. Each

cell is considered functional as long as the actual delay does

not exceed the delay given in the datasheets by more than

10%.

i) Setup Time

The setup time for a sequential cell is the minimum length of

time the data-input signal must remain stable before the active

edge of the clock (or other specified signal) to ensure correct

functioning of the cell. The cell is considered functional as

long as the delay for the output reaching its expected value

does not exceed the reference delay (measured with a large

setup time) by more than 10%. Setup constraint values are

measured as the interval between the data signal crossing 50%

of for rising data (or 50% of for falling data) and the clock

signal crossing 50 and is explained through fig.5.

Fig.5: setup time

ii) Hold Time

The hold time for a sequential cell is the minimum length of

time the data-input signal must remain stable after the active

edge of the clock (or other specified signal) to ensure correct




hold time) by more than 10%. Hold-constraint values are

measured as the interval between the data signal crossing 50%

of for rising data (or 50% of for falling data) and the clock

signal crosses 50% of for rising clocks (or 50% of for falling

clocks). For the measurement of hold time, the data input

signal is held stable before the active clock edge for an infinite

setup time. Fig.6 shows hold time.




Fig .6: Hold Time

iii) Recovery Time

Recovery time for sequential cells is the minimum length of

time that the active low set or reset signal must remain high

before the active edge of the clock to ensure correct




recovery time) by more than 10%. Recovery constraint values

are measured as the interval between the set or reset signal

crossing 50% of and the clock signal crossing 50% of for

rising clocks (or 50% of for falling clocks). For The

measurement of recovery time, the set or reset signals is held

stable after the active clock edge for an infinite hold time.

Fig.7 illustrates recovery time.

Fig .7: Recovery Time

iv) Removal Time

Removal time for sequential cells is the minimum length of

time that the active low set or reset signal must remain low

after the active edge of the clock to ensure correct functioning

of the cell. The cell is considered functional as long as the

active clock edge does not latch in a new data value from that

programmed by the asynchronous set or reset signal. Removal

constraint values are measured as the interval between the set

or reset signal crossing 50% of and the clock signal crossing

50% of for rising clocks (or 50% of for falling clocks). For the

measurement of removal time, the set or reset signal is held

stable before the active clock edge for an infinite setup time.

Fig.8 illustrates removal time.

Figure .8: Removal Time

V) SEQUENTIAL CELLS

LAYOUT, SCHEMATIC CIRCUIT AND SIMULATION RESULTS OF

DESIGNED DIGITAL CIRCUITS USING CADENCE SOFTWARE

A) Mux4

In electronics, a multiplexer (or mux) is a device that selects

one of several analog or digital input signals and forwards the

selected input into a single line. A multiplexer of 2n inputs has

n select lines, which are used to select which input line to send

to the output. Multiplexers are mainly used to increase the

amount of data that can be sent over the network within a

certain amount of time and bandwidth. A multiplexer is also

called a data Selector. The mux4 schematic and symbol is

shown in fig.9 and fig.10.

Fig.9:mux4 schematic

Fig.10:mux4 symbol

B) Nand3

Fig.11:Nand3 layout

Fig.12:Nand3 waveform

Process

corners

rise

time(PS)

fall

time(PS)

propagation

delay(ps)

tt 47.67 53.26 56.34

ss 56.89 63.14 75.18

ff 41.87 50.90 47.57

Table .1: Nand3_1X




Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

Tt 42.37 38.43 48.62

ss 46.38 46.46 59.27

ff 36.15 33.81 41.91

Table .2: Nand3_2X

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 36.5 37.04 44.17

ss 41.59 45.28 55.16

ff 32.85 31.77 39.17

Table .3: Nand3_4X

C) Nor2

Fig.13:Nor2 layout

Fig.14:Nor2 waveform Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

Tt 38.14 16.89 39.62

Ss 43.57 33.89 46.50

Ff 35.67 23.45 34.68

Table .3: Nor2_1X Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 38.04 26.41 41

ss 44.7 35.9 45.4

ff 36.57 24.35 33.58

Table .4: Nor2_2X

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 40.79 35.25 44.63

ss 45.42 42.86 52.20

ff 37.28 31.96 39.36

Table .5: Nor2_4X

D) Or3

Fig.15:Or3 layout

Fig.16:Or3 waveform Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 54.43 57.34 121.4

ss 62.34 59.4 149.66

ff 55.4 49.2 101.165

Table.6: Or3_1X

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 43.15 45.97 108.96

ss 51.42 53.9 134.38

ff 38.1 41.91 91.12

Table .7: Or3_2X

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 42.81 40.44 78.29

ss 47.77 47.1 116.2

ff 38.53 37.66 84.25

Table .8: Or3_4X

E) Xor




Fig.17: Xor layout

Fig.18: Xor waveform

Proces

s

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 46.93 47.16 121.4

ss 57.37 63.66 149.66

ff 42.86 38.38 99.165

Table.9: Xor

F) Aoi21

Fig.19:Aoi21 layout

Fig.20:Aoi21 waveform

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

Tt 44.8 39.52 133.7

Ss 50.32 31.07 169.05

Ff 42.7 51.4 110.15

Table.9: AOI21_1X

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 47.86 47.11 138.2

ss 34.1 33.1 175.55

ff 31.0 31.0 116.6

Table.10: AOI21_2X

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 44.3 30.12 132.8

ss 55.15 53.65 164.05

ff 43.82 40.52 114.15

Table .11: AOI21_4X

G) Oai21

Fig.21: Oai 21 layout

Fig.22: Oai 21 waveform

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 50.35 37.89 42.11

ss 60.69 49.33 53.10

ff 43.21 31.78 35.85

Table.12: Oai 21_1X

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 53.58 46.98 42.68

ss 62.95 58.35 51.62

ff 48.30 39.98 37.44

Table.14: Oai 21_2X

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 53.48 54.35 42.83

ss 60.76 64.85 50.74

Ff 48.57 46.32 38.03

Table.15: Oai 21_4X




H) Mux2

Fig.23: Mux2 waveform

Fig.24:mux2 waveform

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 46.87 44.10 23.85

ss 45.23 48.95 28.16

ff 41.87 38.74 29.99

Table .16: Mux2_1X

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 44.85 43.66 25.155

ss 50.74 50.23 29.28

ff 46.510 47.53 22.11

Table.17: Mux2_2X

Process

corners

rise

time(ps)

fall

time(ps)

propagation

delay(ps)

tt 42.6 41.91 24.08

ss 46.41 47.83 27.39

ff 43.09 40.98 21.89

Table.18: Mux2_4X

I) Half Adder

The half adder adds two single binary digits A and B. It has

two out-puts, sum (S) and carry (C). The carry signal

represents an overflow into thenext digit of a multi-digit

addition. The half-adder ads two input bits and generate carry

and sum which are the two outputs of half-adder. The

summand carry of the half adder is represented by the

equation:

SUM = A: B + A: B, CARRY = A: B

The schematic & symbol is as shown in

Fig.25: half adder schematic

Fig.26: Half adder symbol

Fig.27: Half adder layout

Fig.28: half adder waveform PVT Sumtr

(ps)

Sumtf(

ps)

Carrytr(

ps)

Carrytf(

ps)

Sumtp(

ps)

Carrytp(

ps)

Tt 60.75 50.51 62.20 43.58 121.35 212.7

Ss 73.7 62.27 75.47 52.07 153.4 205.44

Ff 51.64 43.66 52.88 38.07 101.76 218.8

Table.19: half adder

J) Full Adder

A full adder adds binary numbers and accounts for values

carried in as well as out. A one-bit full adder adds three

one-bit numbers, often written as A, B, and Cin; A and B are

the operands, and Cin is a bit carried in from .The next less

significant stage

SUM = (A) xor (B) xor (Cin)

CARRY = A.B + B.Cin + A.Cin

The schematic & symbol is as shown in




Fig.29: full adder schematic

Fig.30: full adder schematic

Fig.31: full adder layout

Fig.32: full adder waveform

P

V

T

Sumtr

(ps)

Sumtf(

ps)

Carrytr(

ps)

Carrytf(

ps)

Sumtp(p

s)

Carrytp(

ps)

tt 60.4 54.22 44.07 41.64 169.42 106.29

ss 70.7 64.95 52.06 48.62 213.07 127.18

ff 54.1 47.7 39.10 37.48 140.86 92.151

Table.20: full adder

VI) CONCLUSION AND FUTURE SCOPE

That main objective of this system is to design high

performance standard cell library and it is achieved by

meeting the given specification. The required specifications

to be met are cell height, rise & fall time, & propagation

delay. This system meets pre layout and post layout results as

per the design specifications. From the results we found that

the designed library meets the required specification and is

ready to be used in the semi customer design. In the future

work we can generate a technology timing library which is a

text containing information regarding timing and functional

characteristics of an ASIC cell library. Several components of

a technology library used by an ASIC design at various phases

of design procedure are listed below: 1. Global parameters:

These include PVT corner specifications, unit definitions,

threshold values for input and output transitions and

maximum output Capacitance and slew limits.2. Functionality

for mapping during synthesis and functional simulations.

Area, power, timing constraints and delay values for

optimization and delay simulation. 4. Pin locations, geometry

of cells, routing blockages and grids for place and route.

REFERENCES

[1] Asic Design in the Silicon Sandbox: A Complete Guide to Building

Mixed-Signal Integrated Circuits, Keith Barr McGraw Hill

Professional, 2007.

[2] Harnessing VLSI System Design with Eda Tools by Santosh A. Shinde,

Pawan K. Gaikwad.

[3] Closing the Gap between Asic & Custom: Tools and Techniques for

High by David Chinnery, Kurt Keutzer.

[4] Low-Power Cmos Circuits: Technology, Logic Design and Cad Tools

by Christian Piguet.

[5] Engineering the Cmos Library: Enhancing Digital Design Kits For

Competitive By David Doman.

[6] Digital VLSI Chip Design with Cadence and Synopsys Cad Tools Erik

Brunvand Addison-Wesley, 2010.

[7] Cmos VLSI Design: A Circuits and Systems Perspective by Neil H. E.

Weste, David Money Harri.

[8] Mixed-Signal Methodology Guide by Jess Chen, Michael Henrie,

Monte F. Mar, Ph.D., Mladen Nizic.

[9] Digital Design by Wakerly.

[10] Engineering the Cmos Library: Enhancing Digital Design Kits For

Competitive By David Doma.

Author1: Name:-Mr. P.Balaramudu Qualification :-M.Tech (Prof.) College:-Sahyadri Valley college of Engineering and Technology University:-Pune University Experience:-8 years(Teaching)

Author2: Name:- Mr. Manoj Kumar Qualification :-M.E (Prof.) College:-Sahyadri Valley college of Engineering and Technology University:-Pune University Experience:-8 years(Teaching)

Author3: Name:-Mr. Chape Laxman Murlidhar Qualification :-M.E(VLSI &ESD) Appear College:-Sahyadri Valley college of Engineering and Technology University:-Pune Universit

Author4: Name:-Mr. Wankhade Sachin Sudamrao Qualification:-M.E(VLSI&ESD)Appear College:-Sahyadri Valley college of Engineering and Technology University:-Pune University

Author5: Name:-Phalke Ulhas Qualification :-M.E(VLSI & ESD)-Appear College:-Sahyadri Valley college of Engineering and Technology University:-Pune University

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