Design of Digital Circuits - ETH Z
Transcript of Design of Digital Circuits - ETH Z
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Design of Digital CircuitsLab 2 Supplement:
Mapping Your Circuit to an FPGA
Prof. Onur MutluETH ZurichSpring 2021
16 March 2021
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What Will We Learn?
n In Lab 2, you will:
q Design a 4-bit adder.
n Design a 1-bit full-adder.
n Use full-adders to design a 4-bit adder.
q Learn how to map your circuits to an FPGA.
q Program your FPGA using the Vivado Design Suite for HDL design.
q Work with your FPGA board and see the results of your designs on the FPGA output.
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Binary Addition
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Binary Addition (1)
0 1 1 1+ 1 0 1 0
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A
B
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Binary Addition (2)
10 1 1 1
+ 1 0 1 00 1
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Carry
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Binary Addition (3)
1 1 10 1 1 1
+ 1 0 1 01 0 0 0 1
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A
B
Sum
Overflow
Carry
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The Full-Adder (1)
1 1 10 1 1 1
+ 1 0 1 01 0 0 0 1
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The Full-Adder (2)
1 1 10 1 1 1
+ 1 0 1 01 0 0 0 1
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Inputs• Carry-in (Cin)• Input 1 (A)• Input 2 (B)
Outputs• Sum (S)• Carry-out (Cout)
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Design an Adder (1)n Design a full-adder:
q Inputs: input 1 (A), input 2 (B), carry-in (Cin).
q Outputs: sum (S), carry-out (Cout).
q All inputs and outputs are 1-bit wide.
n Example:q A = 1, B = 1, Cin = 1
q S = 1, Cout = 1
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Full-adder
A
B
S
Cout
1-bit
1-bit
Cin1-bit
1-bit
1-bit
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Design an Adder (2)n Design a 4-bit adder:
q Receives two 1-bit numbers A and B and a 1-bit input carry (Cin)q Returns outputs S and C as sum and carry of the operation,
respectively.n Example: A = 1110, B =0001, Cin=1
q S = 0000q C = 1
n Hint: Use four full-adders to design a 4-bit adder.
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Full Adder
a0b0
s0
0c1Full Adder
a1b1
s1
c2Full Adder
a2b2
s2
c3Full Adder
a3b3
s3
c4
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Design an Adder (Overview)
1. You will use truth tables to derive the Boolean equation of the adder.
2. You will design the schematic of the circuit using logic gates.
3. You will use Vivado to write your design in Verilog.
4. You will use Vivado to program the FPGA.
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Vivado Design Suite
n We will use the Vivado Design Suite for FPGA programming.
q Vivado is installed in the computers in the lab rooms.
q If you wish to use your own computer, you can follow these instructions:
https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-getting-started/start
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Verilog
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Defining a Module in Verilogn A module is the main building block in Verilog.
n We first need to define:q Name of the moduleq Directions of its ports (e.g., input, output)q Names of its ports
n Then:q Describe the functionality of the module.
ab yc
VerilogModule
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inputs output
example
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Implementing a Module in Verilog
ab yc
VerilogModule
module example (a, b, c, y);input a;input b; input c;output y;
// here comes the circuit description
endmodule
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Port list(inputs and outputs)
ports have a declared type
a module definition
name of module
example
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Structural HDL: Instantiating a Module
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Schematic of module “top” that is built from two instances of module “small”
i_firsti_second
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Structural HDL Example (1)n Module Definitions in Verilog
module small (A, B, Y);input A;input B;output Y;
// description of small
endmodule
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i_firsti_second
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Structural HDL Example (2)n Module Definitions in Verilog
module top (A, SEL, C, Y);input A, SEL, C;output Y;wire n1;
endmodule
module small (A, B, Y);input A;input B;output Y;
// description of small
endmodule
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i_firsti_second
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module top (A, SEL, C, Y);input A, SEL, C;output Y;wire n1;
endmodule
module small (A, B, Y);input A;input B;output Y;
// description of small
endmodule
Structural HDL Example (3)n Defining wires (module interconnections)
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i_firsti_second
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n The first instantiation of the “small” modulemodule top (A, SEL, C, Y);input A, SEL, C;output Y;wire n1;
// instantiate small oncesmall i_first ( .A(A),
.B(SEL),
.Y(n1) );
endmodule
module small (A, B, Y);input A;input B;output Y;
// description of small
endmodule
Structural HDL Example (4)
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i_firsti_second
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n The second instantiation of the “small” module
module top (A, SEL, C, Y);input A, SEL, C;output Y;wire n1;
// instantiate small oncesmall i_first ( .A(A),
.B(SEL),
.Y(n1) );
// instantiate small second timesmall i_second ( .A(n1),
.B(C),
.Y(Y) );
endmodule
module small (A, B, Y);input A;input B;output Y;
// description of small
endmodule
Structural HDL Example (5)
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i_firsti_second
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n Short form of module instantiation
module top (A, SEL, C, Y);input A, SEL, C;output Y;wire n1;
// alternativesmall i_first ( A, SEL, n1 );
/* Shorter instantiation,pin order very important */
// any pin order, safer choicesmall i_second ( .B(C),
.Y(Y),
.A(n1) );
endmodule
module small (A, B, Y);input A;input B;output Y;
// description of small
endmodule
Structural HDL Example (6)
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i_firsti_second
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What about logic gates?
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Instantiating Logic Gates: The NOT Gate
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not my_not(output, input);
gate type gate name output signal input signal
input output𝑨 𝑨0 11 0
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Instantiating Logic Gates: The AND Gate (1)
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and my_and(output, input1, input2);
gate type gate name output signal input signals
AB A • B
𝑨 𝑩 𝑨 • 𝑩0 0 00 1 01 0 01 1 1
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Instantiating Logic Gates: The AND Gate (2)
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and my_and(output, input1, input2);
or…
and my_and(output, input1, input2, input3, ...);
gate type gate name output signal input signals(as many as you want)
gate type gate name output signal input signals
AB A • B
𝑨 𝑩 𝑨 • 𝑩0 0 00 1 01 0 01 1 1
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Instantiating Logic Gates: More Gates…
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not my_not(output, input);
and my_and(output, input1, input2, ...),
or my_or(output, input1, input2, ...);
xor my_xor(output, input1, input2, ...);
nand my_nand(output, input1, input2, ...);
nor my_nor(output, input1, input2, ...);
xnor my_xnor(output, input1, input2, ...);
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Instantiating Logic Gates: A Simple Example (1)
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𝒐𝒖𝒕 = %𝑨 ' %𝑩
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Instantiating Logic Gates: A Simple Example (2)
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𝒐𝒖𝒕 = %𝑨 ' %𝑩
// Notice the alternative port declarationmodule check_zeros (
input A,input B,output out);
// wires for the intermediate signalswire not_a, not_b;
// instantiate the NOT gatesnot(not_a, A);not(not_b, B);
// instantiate the AND gateand(out, not_a, not_b);
endmodule
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Basys 3 FPGA Board
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In this course, we will be using the Basys 3 boards from Digilent, as shown below.
You can learn more about the Basys 3 Starter Board from:
http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/
Output LEDsInput Switches
For this week’s lab:
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Last Wordsn In this lab, you will map your circuit to an FPGA.
n First you will design a full-adder. You will then use the full-adder as a building block to build a 4-bit adder.
n Then, you will learn how to use Xilinx Vivado for writing Verilog and how to connect to the Basys 3 board.
n Finally, you will program the FPGA and get the circuit running on the FPGA board.
n You will find more exercises in the lab report.
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Report Deadline
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23:59, 2 April 2021
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Design of Digital CircuitsLab 2 Supplement:
Mapping Your Circuit to FPGA
Prof. Onur MutluETH ZurichSpring 2021
16 March 2021